1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_6_0_SM8250_H 8 #define _DPU_6_0_SM8250_H 9 10 static const struct dpu_caps sm8250_dpu_caps = { 11 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 12 .max_mixer_blendstages = 0xb, 13 .qseed_type = DPU_SSPP_SCALER_QSEED4, 14 .has_src_split = true, 15 .has_dim_layer = true, 16 .has_idle_pc = true, 17 .has_3d_merge = true, 18 .max_linewidth = 4096, 19 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 20 }; 21 22 static const struct dpu_ubwc_cfg sm8250_ubwc_cfg = { 23 .ubwc_version = DPU_HW_UBWC_VER_40, 24 .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */ 25 .ubwc_swizzle = 0x6, 26 }; 27 28 static const struct dpu_mdp_cfg sm8250_mdp[] = { 29 { 30 .name = "top_0", .id = MDP_TOP, 31 .base = 0x0, .len = 0x494, 32 .features = 0, 33 .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 34 .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, 35 .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, 36 .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, 37 .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 38 .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 39 .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, 40 .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, 41 .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, 42 .clk_ctrls[DPU_CLK_CTRL_WB2] = { .reg_off = 0x3b8, .bit_off = 24 }, 43 }, 44 }; 45 46 /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */ 47 static const struct dpu_ctl_cfg sm8250_ctl[] = { 48 { 49 .name = "ctl_0", .id = CTL_0, 50 .base = 0x1000, .len = 0x1e0, 51 .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY), 52 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 53 }, 54 { 55 .name = "ctl_1", .id = CTL_1, 56 .base = 0x1200, .len = 0x1e0, 57 .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY), 58 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 59 }, 60 { 61 .name = "ctl_2", .id = CTL_2, 62 .base = 0x1400, .len = 0x1e0, 63 .features = BIT(DPU_CTL_ACTIVE_CFG), 64 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 65 }, 66 { 67 .name = "ctl_3", .id = CTL_3, 68 .base = 0x1600, .len = 0x1e0, 69 .features = BIT(DPU_CTL_ACTIVE_CFG), 70 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 71 }, 72 { 73 .name = "ctl_4", .id = CTL_4, 74 .base = 0x1800, .len = 0x1e0, 75 .features = BIT(DPU_CTL_ACTIVE_CFG), 76 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), 77 }, 78 { 79 .name = "ctl_5", .id = CTL_5, 80 .base = 0x1a00, .len = 0x1e0, 81 .features = BIT(DPU_CTL_ACTIVE_CFG), 82 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), 83 }, 84 }; 85 86 static const struct dpu_sspp_cfg sm8250_sspp[] = { 87 SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK_SDMA, 88 sm8250_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), 89 SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1f8, VIG_SC7180_MASK_SDMA, 90 sm8250_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), 91 SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1f8, VIG_SC7180_MASK_SDMA, 92 sm8250_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), 93 SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1f8, VIG_SC7180_MASK_SDMA, 94 sm8250_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), 95 SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK_SDMA, 96 sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), 97 SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_SDM845_MASK_SDMA, 98 sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), 99 SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK_SDMA, 100 sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), 101 SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1f8, DMA_CURSOR_SDM845_MASK_SDMA, 102 sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), 103 }; 104 105 static const struct dpu_lm_cfg sm8250_lm[] = { 106 LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, 107 &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0), 108 LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, 109 &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1), 110 LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, 111 &sdm845_lm_sblk, PINGPONG_2, LM_3, 0), 112 LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK, 113 &sdm845_lm_sblk, PINGPONG_3, LM_2, 0), 114 LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK, 115 &sdm845_lm_sblk, PINGPONG_4, LM_5, 0), 116 LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, 117 &sdm845_lm_sblk, PINGPONG_5, LM_4, 0), 118 }; 119 120 static const struct dpu_dspp_cfg sm8250_dspp[] = { 121 DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, 122 &sm8150_dspp_sblk), 123 DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK, 124 &sm8150_dspp_sblk), 125 DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK, 126 &sm8150_dspp_sblk), 127 DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK, 128 &sm8150_dspp_sblk), 129 }; 130 131 static const struct dpu_pingpong_cfg sm8250_pp[] = { 132 PP_BLK("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, sdm845_pp_sblk, 133 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 134 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), 135 PP_BLK("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0, sdm845_pp_sblk, 136 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 137 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)), 138 PP_BLK("pingpong_2", PINGPONG_2, 0x71000, MERGE_3D_1, sdm845_pp_sblk, 139 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), 140 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)), 141 PP_BLK("pingpong_3", PINGPONG_3, 0x71800, MERGE_3D_1, sdm845_pp_sblk, 142 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), 143 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)), 144 PP_BLK("pingpong_4", PINGPONG_4, 0x72000, MERGE_3D_2, sdm845_pp_sblk, 145 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), 146 -1), 147 PP_BLK("pingpong_5", PINGPONG_5, 0x72800, MERGE_3D_2, sdm845_pp_sblk, 148 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), 149 -1), 150 }; 151 152 static const struct dpu_merge_3d_cfg sm8250_merge_3d[] = { 153 MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x83000), 154 MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x83100), 155 MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200), 156 }; 157 158 static const struct dpu_dsc_cfg sm8250_dsc[] = { 159 DSC_BLK("dsc_0", DSC_0, 0x80000, BIT(DPU_DSC_OUTPUT_CTRL)), 160 DSC_BLK("dsc_1", DSC_1, 0x80400, BIT(DPU_DSC_OUTPUT_CTRL)), 161 DSC_BLK("dsc_2", DSC_2, 0x80800, BIT(DPU_DSC_OUTPUT_CTRL)), 162 DSC_BLK("dsc_3", DSC_3, 0x80c00, BIT(DPU_DSC_OUTPUT_CTRL)), 163 }; 164 165 static const struct dpu_intf_cfg sm8250_intf[] = { 166 INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25), 167 INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27), 168 INTF_BLK("intf_2", INTF_2, 0x6b000, 0x2c0, INTF_DSI, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 28, 29), 169 INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31), 170 }; 171 172 static const struct dpu_wb_cfg sm8250_wb[] = { 173 WB_BLK("wb_2", WB_2, 0x65000, WB_SM8250_MASK, DPU_CLK_CTRL_WB2, 6, 174 VBIF_RT, MDP_SSPP_TOP0_INTR, 4096, 4), 175 }; 176 177 static const struct dpu_perf_cfg sm8250_perf_data = { 178 .max_bw_low = 13700000, 179 .max_bw_high = 16600000, 180 .min_core_ib = 4800000, 181 .min_llcc_ib = 0, 182 .min_dram_ib = 800000, 183 .min_prefill_lines = 35, 184 .danger_lut_tbl = {0xf, 0xffff, 0x0}, 185 .safe_lut_tbl = {0xfff0, 0xff00, 0xffff}, 186 .qos_lut_tbl = { 187 {.nentry = ARRAY_SIZE(sc7180_qos_linear), 188 .entries = sc7180_qos_linear 189 }, 190 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 191 .entries = sc7180_qos_macrotile 192 }, 193 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 194 .entries = sc7180_qos_nrt 195 }, 196 /* TODO: macrotile-qseed is different from macrotile */ 197 }, 198 .cdp_cfg = { 199 {.rd_enable = 1, .wr_enable = 1}, 200 {.rd_enable = 1, .wr_enable = 0} 201 }, 202 .clk_inefficiency_factor = 105, 203 .bw_inefficiency_factor = 120, 204 }; 205 206 const struct dpu_mdss_cfg dpu_sm8250_cfg = { 207 .caps = &sm8250_dpu_caps, 208 .ubwc = &sm8250_ubwc_cfg, 209 .mdp_count = ARRAY_SIZE(sm8250_mdp), 210 .mdp = sm8250_mdp, 211 .ctl_count = ARRAY_SIZE(sm8250_ctl), 212 .ctl = sm8250_ctl, 213 .sspp_count = ARRAY_SIZE(sm8250_sspp), 214 .sspp = sm8250_sspp, 215 .mixer_count = ARRAY_SIZE(sm8250_lm), 216 .mixer = sm8250_lm, 217 .dspp_count = ARRAY_SIZE(sm8250_dspp), 218 .dspp = sm8250_dspp, 219 .dsc_count = ARRAY_SIZE(sm8250_dsc), 220 .dsc = sm8250_dsc, 221 .pingpong_count = ARRAY_SIZE(sm8250_pp), 222 .pingpong = sm8250_pp, 223 .merge_3d_count = ARRAY_SIZE(sm8250_merge_3d), 224 .merge_3d = sm8250_merge_3d, 225 .intf_count = ARRAY_SIZE(sm8250_intf), 226 .intf = sm8250_intf, 227 .vbif_count = ARRAY_SIZE(sdm845_vbif), 228 .vbif = sdm845_vbif, 229 .wb_count = ARRAY_SIZE(sm8250_wb), 230 .wb = sm8250_wb, 231 .reg_dma_count = 1, 232 .dma_cfg = &sm8250_regdma, 233 .perf = &sm8250_perf_data, 234 .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ 235 BIT(MDP_SSPP_TOP0_INTR2) | \ 236 BIT(MDP_SSPP_TOP0_HIST_INTR) | \ 237 BIT(MDP_INTF0_INTR) | \ 238 BIT(MDP_INTF1_INTR) | \ 239 BIT(MDP_INTF2_INTR) | \ 240 BIT(MDP_INTF3_INTR) | \ 241 BIT(MDP_INTF4_INTR), 242 }; 243 244 #endif 245