1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2023 Marijn Suijten <marijn.suijten@somainline.org>. All rights reserved. 4 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 5 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 6 */ 7 8 #ifndef _DPU_5_4_SM6125_H 9 #define _DPU_5_4_SM6125_H 10 11 static const struct dpu_caps sm6125_dpu_caps = { 12 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 13 .max_mixer_blendstages = 0x6, 14 .has_dim_layer = true, 15 .has_idle_pc = true, 16 .max_linewidth = 2160, 17 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 18 .max_hdeci_exp = MAX_HORZ_DECIMATION, 19 .max_vdeci_exp = MAX_VERT_DECIMATION, 20 }; 21 22 static const struct dpu_ubwc_cfg sm6125_ubwc_cfg = { 23 .ubwc_version = DPU_HW_UBWC_VER_10, 24 .highest_bank_bit = 0x1, 25 .ubwc_swizzle = 0x1, 26 }; 27 28 static const struct dpu_mdp_cfg sm6125_mdp = { 29 .name = "top_0", 30 .base = 0x0, .len = 0x45c, 31 .features = 0, 32 .clk_ctrls = { 33 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 34 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 35 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 36 }, 37 }; 38 39 static const struct dpu_ctl_cfg sm6125_ctl[] = { 40 { 41 .name = "ctl_0", .id = CTL_0, 42 .base = 0x1000, .len = 0x1e0, 43 .features = BIT(DPU_CTL_ACTIVE_CFG), 44 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 45 }, { 46 .name = "ctl_1", .id = CTL_1, 47 .base = 0x1200, .len = 0x1e0, 48 .features = BIT(DPU_CTL_ACTIVE_CFG), 49 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 50 }, { 51 .name = "ctl_2", .id = CTL_2, 52 .base = 0x1400, .len = 0x1e0, 53 .features = BIT(DPU_CTL_ACTIVE_CFG), 54 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 55 }, { 56 .name = "ctl_3", .id = CTL_3, 57 .base = 0x1600, .len = 0x1e0, 58 .features = BIT(DPU_CTL_ACTIVE_CFG), 59 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 60 }, { 61 .name = "ctl_4", .id = CTL_4, 62 .base = 0x1800, .len = 0x1e0, 63 .features = BIT(DPU_CTL_ACTIVE_CFG), 64 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), 65 }, { 66 .name = "ctl_5", .id = CTL_5, 67 .base = 0x1a00, .len = 0x1e0, 68 .features = BIT(DPU_CTL_ACTIVE_CFG), 69 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), 70 }, 71 }; 72 73 static const struct dpu_sspp_cfg sm6125_sspp[] = { 74 { 75 .name = "sspp_0", .id = SSPP_VIG0, 76 .base = 0x4000, .len = 0x1f0, 77 .features = VIG_SM6125_MASK, 78 .sblk = &sm6125_vig_sblk_0, 79 .xin_id = 0, 80 .type = SSPP_TYPE_VIG, 81 .clk_ctrl = DPU_CLK_CTRL_VIG0, 82 }, { 83 .name = "sspp_8", .id = SSPP_DMA0, 84 .base = 0x24000, .len = 0x1f0, 85 .features = DMA_SDM845_MASK, 86 .sblk = &sdm845_dma_sblk_0, 87 .xin_id = 1, 88 .type = SSPP_TYPE_DMA, 89 .clk_ctrl = DPU_CLK_CTRL_DMA0, 90 }, { 91 .name = "sspp_9", .id = SSPP_DMA1, 92 .base = 0x26000, .len = 0x1f0, 93 .features = DMA_SDM845_MASK, 94 .sblk = &sdm845_dma_sblk_1, 95 .xin_id = 5, 96 .type = SSPP_TYPE_DMA, 97 .clk_ctrl = DPU_CLK_CTRL_DMA1, 98 }, 99 }; 100 101 static const struct dpu_lm_cfg sm6125_lm[] = { 102 { 103 .name = "lm_0", .id = LM_0, 104 .base = 0x44000, .len = 0x320, 105 .features = MIXER_QCM2290_MASK, 106 .sblk = &sdm845_lm_sblk, 107 .pingpong = PINGPONG_0, 108 .dspp = DSPP_0, 109 .lm_pair = LM_1, 110 }, { 111 .name = "lm_1", .id = LM_1, 112 .base = 0x45000, .len = 0x320, 113 .features = MIXER_QCM2290_MASK, 114 .sblk = &sdm845_lm_sblk, 115 .pingpong = PINGPONG_1, 116 .dspp = 0, 117 .lm_pair = LM_0, 118 }, 119 }; 120 121 static const struct dpu_dspp_cfg sm6125_dspp[] = { 122 { 123 .name = "dspp_0", .id = DSPP_0, 124 .base = 0x54000, .len = 0x1800, 125 .features = DSPP_SC7180_MASK, 126 .sblk = &sdm845_dspp_sblk, 127 }, 128 }; 129 130 static const struct dpu_pingpong_cfg sm6125_pp[] = { 131 { 132 .name = "pingpong_0", .id = PINGPONG_0, 133 .base = 0x70000, .len = 0xd4, 134 .features = PINGPONG_SM8150_MASK, 135 .merge_3d = 0, 136 .sblk = &sdm845_pp_sblk, 137 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 138 .intr_rdptr = -1, 139 }, { 140 .name = "pingpong_1", .id = PINGPONG_1, 141 .base = 0x70800, .len = 0xd4, 142 .features = PINGPONG_SM8150_MASK, 143 .merge_3d = 0, 144 .sblk = &sdm845_pp_sblk, 145 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 146 .intr_rdptr = -1, 147 }, 148 }; 149 150 static const struct dpu_intf_cfg sm6125_intf[] = { 151 { 152 .name = "intf_0", .id = INTF_0, 153 .base = 0x6a000, .len = 0x280, 154 .features = INTF_SC7180_MASK, 155 .type = INTF_DP, 156 .controller_id = MSM_DP_CONTROLLER_0, 157 .prog_fetch_lines_worst_case = 24, 158 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), 159 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), 160 .intr_tear_rd_ptr = -1, 161 }, { 162 .name = "intf_1", .id = INTF_1, 163 .base = 0x6a800, .len = 0x2c0, 164 .features = INTF_SC7180_MASK, 165 .type = INTF_DSI, 166 .controller_id = 0, 167 .prog_fetch_lines_worst_case = 24, 168 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 169 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), 170 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), 171 }, 172 }; 173 174 static const struct dpu_perf_cfg sm6125_perf_data = { 175 .max_bw_low = 4100000, 176 .max_bw_high = 4100000, 177 .min_core_ib = 2400000, 178 .min_llcc_ib = 0, /* No LLCC on this SoC */ 179 .min_dram_ib = 800000, 180 .min_prefill_lines = 24, 181 .danger_lut_tbl = {0xf, 0xffff, 0x0}, 182 .safe_lut_tbl = {0xfff8, 0xf000, 0xffff}, 183 .qos_lut_tbl = { 184 {.nentry = ARRAY_SIZE(sm8150_qos_linear), 185 .entries = sm8150_qos_linear 186 }, 187 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 188 .entries = sc7180_qos_macrotile 189 }, 190 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 191 .entries = sc7180_qos_nrt 192 }, 193 /* TODO: macrotile-qseed is different from macrotile */ 194 }, 195 .cdp_cfg = { 196 {.rd_enable = 1, .wr_enable = 1}, 197 {.rd_enable = 1, .wr_enable = 0} 198 }, 199 .clk_inefficiency_factor = 105, 200 .bw_inefficiency_factor = 120, 201 }; 202 203 static const struct dpu_mdss_version sm6125_mdss_ver = { 204 .core_major_ver = 5, 205 .core_minor_ver = 4, 206 }; 207 208 const struct dpu_mdss_cfg dpu_sm6125_cfg = { 209 .mdss_ver = &sm6125_mdss_ver, 210 .caps = &sm6125_dpu_caps, 211 .ubwc = &sm6125_ubwc_cfg, 212 .mdp = &sm6125_mdp, 213 .ctl_count = ARRAY_SIZE(sm6125_ctl), 214 .ctl = sm6125_ctl, 215 .sspp_count = ARRAY_SIZE(sm6125_sspp), 216 .sspp = sm6125_sspp, 217 .mixer_count = ARRAY_SIZE(sm6125_lm), 218 .mixer = sm6125_lm, 219 .dspp_count = ARRAY_SIZE(sm6125_dspp), 220 .dspp = sm6125_dspp, 221 .pingpong_count = ARRAY_SIZE(sm6125_pp), 222 .pingpong = sm6125_pp, 223 .intf_count = ARRAY_SIZE(sm6125_intf), 224 .intf = sm6125_intf, 225 .vbif_count = ARRAY_SIZE(sdm845_vbif), 226 .vbif = sdm845_vbif, 227 .perf = &sm6125_perf_data, 228 .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ 229 BIT(MDP_SSPP_TOP0_INTR2) | \ 230 BIT(MDP_SSPP_TOP0_HIST_INTR) | \ 231 BIT(MDP_INTF0_INTR) | \ 232 BIT(MDP_INTF1_INTR) | \ 233 BIT(MDP_INTF1_TEAR_INTR), 234 }; 235 236 #endif 237