1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (c) 2023 Marijn Suijten <marijn.suijten@somainline.org>. All rights reserved.
4  * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
5  * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
6  */
7 
8 #ifndef _DPU_5_4_SM6125_H
9 #define _DPU_5_4_SM6125_H
10 
11 static const struct dpu_caps sm6125_dpu_caps = {
12 	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
13 	.max_mixer_blendstages = 0x6,
14 	.has_dim_layer = true,
15 	.has_idle_pc = true,
16 	.max_linewidth = 2160,
17 	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
18 	.max_hdeci_exp = MAX_HORZ_DECIMATION,
19 	.max_vdeci_exp = MAX_VERT_DECIMATION,
20 };
21 
22 static const struct dpu_mdp_cfg sm6125_mdp = {
23 	.name = "top_0",
24 	.base = 0x0, .len = 0x45c,
25 	.features = 0,
26 	.clk_ctrls = {
27 		[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
28 		[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
29 		[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
30 	},
31 };
32 
33 static const struct dpu_ctl_cfg sm6125_ctl[] = {
34 	{
35 		.name = "ctl_0", .id = CTL_0,
36 		.base = 0x1000, .len = 0x1e0,
37 		.features = BIT(DPU_CTL_ACTIVE_CFG),
38 		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
39 	}, {
40 		.name = "ctl_1", .id = CTL_1,
41 		.base = 0x1200, .len = 0x1e0,
42 		.features = BIT(DPU_CTL_ACTIVE_CFG),
43 		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
44 	}, {
45 		.name = "ctl_2", .id = CTL_2,
46 		.base = 0x1400, .len = 0x1e0,
47 		.features = BIT(DPU_CTL_ACTIVE_CFG),
48 		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
49 	}, {
50 		.name = "ctl_3", .id = CTL_3,
51 		.base = 0x1600, .len = 0x1e0,
52 		.features = BIT(DPU_CTL_ACTIVE_CFG),
53 		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
54 	}, {
55 		.name = "ctl_4", .id = CTL_4,
56 		.base = 0x1800, .len = 0x1e0,
57 		.features = BIT(DPU_CTL_ACTIVE_CFG),
58 		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
59 	}, {
60 		.name = "ctl_5", .id = CTL_5,
61 		.base = 0x1a00, .len = 0x1e0,
62 		.features = BIT(DPU_CTL_ACTIVE_CFG),
63 		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
64 	},
65 };
66 
67 static const struct dpu_sspp_cfg sm6125_sspp[] = {
68 	{
69 		.name = "sspp_0", .id = SSPP_VIG0,
70 		.base = 0x4000, .len = 0x1f0,
71 		.features = VIG_SM6125_MASK,
72 		.sblk = &sm6125_vig_sblk_0,
73 		.xin_id = 0,
74 		.type = SSPP_TYPE_VIG,
75 		.clk_ctrl = DPU_CLK_CTRL_VIG0,
76 	}, {
77 		.name = "sspp_8", .id = SSPP_DMA0,
78 		.base = 0x24000, .len = 0x1f0,
79 		.features = DMA_SDM845_MASK,
80 		.sblk = &sdm845_dma_sblk_0,
81 		.xin_id = 1,
82 		.type = SSPP_TYPE_DMA,
83 		.clk_ctrl = DPU_CLK_CTRL_DMA0,
84 	}, {
85 		.name = "sspp_9", .id = SSPP_DMA1,
86 		.base = 0x26000, .len = 0x1f0,
87 		.features = DMA_SDM845_MASK,
88 		.sblk = &sdm845_dma_sblk_1,
89 		.xin_id = 5,
90 		.type = SSPP_TYPE_DMA,
91 		.clk_ctrl = DPU_CLK_CTRL_DMA1,
92 	},
93 };
94 
95 static const struct dpu_lm_cfg sm6125_lm[] = {
96 	{
97 		.name = "lm_0", .id = LM_0,
98 		.base = 0x44000, .len = 0x320,
99 		.features = MIXER_QCM2290_MASK,
100 		.sblk = &sdm845_lm_sblk,
101 		.pingpong = PINGPONG_0,
102 		.dspp = DSPP_0,
103 		.lm_pair = LM_1,
104 	}, {
105 		.name = "lm_1", .id = LM_1,
106 		.base = 0x45000, .len = 0x320,
107 		.features = MIXER_QCM2290_MASK,
108 		.sblk = &sdm845_lm_sblk,
109 		.pingpong = PINGPONG_1,
110 		.dspp = 0,
111 		.lm_pair = LM_0,
112 	},
113 };
114 
115 static const struct dpu_dspp_cfg sm6125_dspp[] = {
116 	{
117 		.name = "dspp_0", .id = DSPP_0,
118 		.base = 0x54000, .len = 0x1800,
119 		.features = DSPP_SC7180_MASK,
120 		.sblk = &sdm845_dspp_sblk,
121 	},
122 };
123 
124 static const struct dpu_pingpong_cfg sm6125_pp[] = {
125 	{
126 		.name = "pingpong_0", .id = PINGPONG_0,
127 		.base = 0x70000, .len = 0xd4,
128 		.features = PINGPONG_SM8150_MASK,
129 		.merge_3d = 0,
130 		.sblk = &sdm845_pp_sblk,
131 		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
132 		.intr_rdptr = -1,
133 	}, {
134 		.name = "pingpong_1", .id = PINGPONG_1,
135 		.base = 0x70800, .len = 0xd4,
136 		.features = PINGPONG_SM8150_MASK,
137 		.merge_3d = 0,
138 		.sblk = &sdm845_pp_sblk,
139 		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
140 		.intr_rdptr = -1,
141 	},
142 };
143 
144 static const struct dpu_intf_cfg sm6125_intf[] = {
145 	{
146 		.name = "intf_0", .id = INTF_0,
147 		.base = 0x6a000, .len = 0x280,
148 		.features = INTF_SC7180_MASK,
149 		.type = INTF_DP,
150 		.controller_id = MSM_DP_CONTROLLER_0,
151 		.prog_fetch_lines_worst_case = 24,
152 		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
153 		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
154 		.intr_tear_rd_ptr = -1,
155 	}, {
156 		.name = "intf_1", .id = INTF_1,
157 		.base = 0x6a800, .len = 0x2c0,
158 		.features = INTF_SC7180_MASK,
159 		.type = INTF_DSI,
160 		.controller_id = 0,
161 		.prog_fetch_lines_worst_case = 24,
162 		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
163 		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
164 		.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
165 	},
166 };
167 
168 static const struct dpu_perf_cfg sm6125_perf_data = {
169 	.max_bw_low = 4100000,
170 	.max_bw_high = 4100000,
171 	.min_core_ib = 2400000,
172 	.min_llcc_ib = 0, /* No LLCC on this SoC */
173 	.min_dram_ib = 800000,
174 	.min_prefill_lines = 24,
175 	.danger_lut_tbl = {0xf, 0xffff, 0x0},
176 	.safe_lut_tbl = {0xfff8, 0xf000, 0xffff},
177 	.qos_lut_tbl = {
178 		{.nentry = ARRAY_SIZE(sm8150_qos_linear),
179 		.entries = sm8150_qos_linear
180 		},
181 		{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
182 		.entries = sc7180_qos_macrotile
183 		},
184 		{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
185 		.entries = sc7180_qos_nrt
186 		},
187 		/* TODO: macrotile-qseed is different from macrotile */
188 	},
189 	.cdp_cfg = {
190 		{.rd_enable = 1, .wr_enable = 1},
191 		{.rd_enable = 1, .wr_enable = 0}
192 	},
193 	.clk_inefficiency_factor = 105,
194 	.bw_inefficiency_factor = 120,
195 };
196 
197 static const struct dpu_mdss_version sm6125_mdss_ver = {
198 	.core_major_ver = 5,
199 	.core_minor_ver = 4,
200 };
201 
202 const struct dpu_mdss_cfg dpu_sm6125_cfg = {
203 	.mdss_ver = &sm6125_mdss_ver,
204 	.caps = &sm6125_dpu_caps,
205 	.mdp = &sm6125_mdp,
206 	.ctl_count = ARRAY_SIZE(sm6125_ctl),
207 	.ctl = sm6125_ctl,
208 	.sspp_count = ARRAY_SIZE(sm6125_sspp),
209 	.sspp = sm6125_sspp,
210 	.mixer_count = ARRAY_SIZE(sm6125_lm),
211 	.mixer = sm6125_lm,
212 	.dspp_count = ARRAY_SIZE(sm6125_dspp),
213 	.dspp = sm6125_dspp,
214 	.pingpong_count = ARRAY_SIZE(sm6125_pp),
215 	.pingpong = sm6125_pp,
216 	.intf_count = ARRAY_SIZE(sm6125_intf),
217 	.intf = sm6125_intf,
218 	.vbif_count = ARRAY_SIZE(sdm845_vbif),
219 	.vbif = sdm845_vbif,
220 	.perf = &sm6125_perf_data,
221 };
222 
223 #endif
224