1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_5_1_SC8180X_H 8 #define _DPU_5_1_SC8180X_H 9 10 static const struct dpu_caps sc8180x_dpu_caps = { 11 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 12 .max_mixer_blendstages = 0xb, 13 .qseed_type = DPU_SSPP_SCALER_QSEED3, 14 .has_src_split = true, 15 .has_dim_layer = true, 16 .has_idle_pc = true, 17 .has_3d_merge = true, 18 .max_linewidth = 4096, 19 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 20 .max_hdeci_exp = MAX_HORZ_DECIMATION, 21 .max_vdeci_exp = MAX_VERT_DECIMATION, 22 }; 23 24 static const struct dpu_ubwc_cfg sc8180x_ubwc_cfg = { 25 .ubwc_version = DPU_HW_UBWC_VER_30, 26 .highest_bank_bit = 0x3, 27 }; 28 29 static const struct dpu_mdp_cfg sc8180x_mdp[] = { 30 { 31 .name = "top_0", .id = MDP_TOP, 32 .base = 0x0, .len = 0x45c, 33 .features = BIT(DPU_MDP_AUDIO_SELECT), 34 .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 35 .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, 36 .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, 37 .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, 38 .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 39 .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 40 .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, 41 .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, 42 }, 43 }; 44 45 static const struct dpu_ctl_cfg sc8180x_ctl[] = { 46 { 47 .name = "ctl_0", .id = CTL_0, 48 .base = 0x1000, .len = 0x1e0, 49 .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY), 50 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 51 }, 52 { 53 .name = "ctl_1", .id = CTL_1, 54 .base = 0x1200, .len = 0x1e0, 55 .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY), 56 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 57 }, 58 { 59 .name = "ctl_2", .id = CTL_2, 60 .base = 0x1400, .len = 0x1e0, 61 .features = BIT(DPU_CTL_ACTIVE_CFG), 62 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 63 }, 64 { 65 .name = "ctl_3", .id = CTL_3, 66 .base = 0x1600, .len = 0x1e0, 67 .features = BIT(DPU_CTL_ACTIVE_CFG), 68 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 69 }, 70 { 71 .name = "ctl_4", .id = CTL_4, 72 .base = 0x1800, .len = 0x1e0, 73 .features = BIT(DPU_CTL_ACTIVE_CFG), 74 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), 75 }, 76 { 77 .name = "ctl_5", .id = CTL_5, 78 .base = 0x1a00, .len = 0x1e0, 79 .features = BIT(DPU_CTL_ACTIVE_CFG), 80 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), 81 }, 82 }; 83 84 static const struct dpu_sspp_cfg sc8180x_sspp[] = { 85 SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f0, VIG_SDM845_MASK, 86 sdm845_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), 87 SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1f0, VIG_SDM845_MASK, 88 sdm845_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), 89 SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1f0, VIG_SDM845_MASK, 90 sdm845_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), 91 SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1f0, VIG_SDM845_MASK, 92 sdm845_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), 93 SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f0, DMA_SDM845_MASK, 94 sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), 95 SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f0, DMA_SDM845_MASK, 96 sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), 97 SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f0, DMA_CURSOR_SDM845_MASK, 98 sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), 99 SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1f0, DMA_CURSOR_SDM845_MASK, 100 sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), 101 }; 102 103 static const struct dpu_lm_cfg sc8180x_lm[] = { 104 LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, 105 &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0), 106 LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, 107 &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1), 108 LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, 109 &sdm845_lm_sblk, PINGPONG_2, LM_3, 0), 110 LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK, 111 &sdm845_lm_sblk, PINGPONG_3, LM_2, 0), 112 LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK, 113 &sdm845_lm_sblk, PINGPONG_4, LM_5, 0), 114 LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, 115 &sdm845_lm_sblk, PINGPONG_5, LM_4, 0), 116 }; 117 118 static const struct dpu_dspp_cfg sc8180x_dspp[] = { 119 DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, 120 &sm8150_dspp_sblk), 121 DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK, 122 &sm8150_dspp_sblk), 123 DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK, 124 &sm8150_dspp_sblk), 125 DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK, 126 &sm8150_dspp_sblk), 127 }; 128 129 static const struct dpu_pingpong_cfg sc8180x_pp[] = { 130 PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, MERGE_3D_0, sdm845_pp_sblk, 131 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 132 -1), 133 PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, MERGE_3D_0, sdm845_pp_sblk, 134 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 135 -1), 136 PP_BLK("pingpong_2", PINGPONG_2, 0x71000, PINGPONG_SM8150_MASK, MERGE_3D_1, sdm845_pp_sblk, 137 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), 138 -1), 139 PP_BLK("pingpong_3", PINGPONG_3, 0x71800, PINGPONG_SM8150_MASK, MERGE_3D_1, sdm845_pp_sblk, 140 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), 141 -1), 142 PP_BLK("pingpong_4", PINGPONG_4, 0x72000, PINGPONG_SM8150_MASK, MERGE_3D_2, sdm845_pp_sblk, 143 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), 144 -1), 145 PP_BLK("pingpong_5", PINGPONG_5, 0x72800, PINGPONG_SM8150_MASK, MERGE_3D_2, sdm845_pp_sblk, 146 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), 147 -1), 148 }; 149 150 static const struct dpu_merge_3d_cfg sc8180x_merge_3d[] = { 151 MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x83000), 152 MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x83100), 153 MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200), 154 }; 155 156 static const struct dpu_dsc_cfg sc8180x_dsc[] = { 157 DSC_BLK("dsc_0", DSC_0, 0x80000, BIT(DPU_DSC_OUTPUT_CTRL)), 158 DSC_BLK("dsc_1", DSC_1, 0x80400, BIT(DPU_DSC_OUTPUT_CTRL)), 159 DSC_BLK("dsc_2", DSC_2, 0x80800, BIT(DPU_DSC_OUTPUT_CTRL)), 160 DSC_BLK("dsc_3", DSC_3, 0x80c00, BIT(DPU_DSC_OUTPUT_CTRL)), 161 DSC_BLK("dsc_4", DSC_4, 0x81000, BIT(DPU_DSC_OUTPUT_CTRL)), 162 DSC_BLK("dsc_5", DSC_5, 0x81400, BIT(DPU_DSC_OUTPUT_CTRL)), 163 }; 164 165 static const struct dpu_intf_cfg sc8180x_intf[] = { 166 INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, 167 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), 168 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)), 169 INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2bc, INTF_DSI, 0, 24, INTF_SC7180_MASK, 170 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 171 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), 172 DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)), 173 INTF_BLK_DSI_TE("intf_2", INTF_2, 0x6b000, 0x2bc, INTF_DSI, 1, 24, INTF_SC7180_MASK, 174 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), 175 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), 176 DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2)), 177 /* INTF_3 is for MST, wired to INTF_DP 0 and 1, use dummy index until this is supported */ 178 INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 999, 24, INTF_SC7180_MASK, 179 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), 180 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)), 181 INTF_BLK("intf_4", INTF_4, 0x6c000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7180_MASK, 182 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20), 183 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21)), 184 INTF_BLK("intf_5", INTF_5, 0x6c800, 0x280, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC7180_MASK, 185 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22), 186 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23)), 187 }; 188 189 static const struct dpu_perf_cfg sc8180x_perf_data = { 190 .max_bw_low = 9600000, 191 .max_bw_high = 9600000, 192 .min_core_ib = 2400000, 193 .min_llcc_ib = 800000, 194 .min_dram_ib = 800000, 195 .danger_lut_tbl = {0xf, 0xffff, 0x0}, 196 .qos_lut_tbl = { 197 {.nentry = ARRAY_SIZE(sc7180_qos_linear), 198 .entries = sc7180_qos_linear 199 }, 200 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 201 .entries = sc7180_qos_macrotile 202 }, 203 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 204 .entries = sc7180_qos_nrt 205 }, 206 /* TODO: macrotile-qseed is different from macrotile */ 207 }, 208 .cdp_cfg = { 209 {.rd_enable = 1, .wr_enable = 1}, 210 {.rd_enable = 1, .wr_enable = 0} 211 }, 212 .clk_inefficiency_factor = 105, 213 .bw_inefficiency_factor = 120, 214 }; 215 216 const struct dpu_mdss_cfg dpu_sc8180x_cfg = { 217 .caps = &sc8180x_dpu_caps, 218 .ubwc = &sc8180x_ubwc_cfg, 219 .mdp_count = ARRAY_SIZE(sc8180x_mdp), 220 .mdp = sc8180x_mdp, 221 .ctl_count = ARRAY_SIZE(sc8180x_ctl), 222 .ctl = sc8180x_ctl, 223 .sspp_count = ARRAY_SIZE(sc8180x_sspp), 224 .sspp = sc8180x_sspp, 225 .mixer_count = ARRAY_SIZE(sc8180x_lm), 226 .mixer = sc8180x_lm, 227 .dspp_count = ARRAY_SIZE(sc8180x_dspp), 228 .dspp = sc8180x_dspp, 229 .dsc_count = ARRAY_SIZE(sc8180x_dsc), 230 .dsc = sc8180x_dsc, 231 .pingpong_count = ARRAY_SIZE(sc8180x_pp), 232 .pingpong = sc8180x_pp, 233 .merge_3d_count = ARRAY_SIZE(sc8180x_merge_3d), 234 .merge_3d = sc8180x_merge_3d, 235 .intf_count = ARRAY_SIZE(sc8180x_intf), 236 .intf = sc8180x_intf, 237 .vbif_count = ARRAY_SIZE(sdm845_vbif), 238 .vbif = sdm845_vbif, 239 .perf = &sc8180x_perf_data, 240 .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ 241 BIT(MDP_SSPP_TOP0_INTR2) | \ 242 BIT(MDP_SSPP_TOP0_HIST_INTR) | \ 243 BIT(MDP_INTF0_INTR) | \ 244 BIT(MDP_INTF1_INTR) | \ 245 BIT(MDP_INTF1_TEAR_INTR) | \ 246 BIT(MDP_INTF2_INTR) | \ 247 BIT(MDP_INTF2_TEAR_INTR) | \ 248 BIT(MDP_INTF3_INTR) | \ 249 BIT(MDP_INTF4_INTR) | \ 250 BIT(MDP_INTF5_INTR) | \ 251 BIT(MDP_AD4_0_INTR) | \ 252 BIT(MDP_AD4_1_INTR), 253 }; 254 255 #endif 256