1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_5_0_SM8150_H 8 #define _DPU_5_0_SM8150_H 9 10 static const struct dpu_caps sm8150_dpu_caps = { 11 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 12 .max_mixer_blendstages = 0xb, 13 .qseed_type = DPU_SSPP_SCALER_QSEED3, 14 .has_src_split = true, 15 .has_dim_layer = true, 16 .has_idle_pc = true, 17 .has_3d_merge = true, 18 .max_linewidth = 4096, 19 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 20 .max_hdeci_exp = MAX_HORZ_DECIMATION, 21 .max_vdeci_exp = MAX_VERT_DECIMATION, 22 }; 23 24 static const struct dpu_ubwc_cfg sm8150_ubwc_cfg = { 25 .ubwc_version = DPU_HW_UBWC_VER_30, 26 .highest_bank_bit = 0x2, 27 }; 28 29 static const struct dpu_mdp_cfg sm8150_mdp[] = { 30 { 31 .name = "top_0", .id = MDP_TOP, 32 .base = 0x0, .len = 0x45c, 33 .features = BIT(DPU_MDP_AUDIO_SELECT), 34 .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 35 .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, 36 .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, 37 .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, 38 .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 39 .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 40 .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, 41 .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, 42 }, 43 }; 44 45 /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */ 46 static const struct dpu_ctl_cfg sm8150_ctl[] = { 47 { 48 .name = "ctl_0", .id = CTL_0, 49 .base = 0x1000, .len = 0x1e0, 50 .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY), 51 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 52 }, 53 { 54 .name = "ctl_1", .id = CTL_1, 55 .base = 0x1200, .len = 0x1e0, 56 .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY), 57 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 58 }, 59 { 60 .name = "ctl_2", .id = CTL_2, 61 .base = 0x1400, .len = 0x1e0, 62 .features = BIT(DPU_CTL_ACTIVE_CFG), 63 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 64 }, 65 { 66 .name = "ctl_3", .id = CTL_3, 67 .base = 0x1600, .len = 0x1e0, 68 .features = BIT(DPU_CTL_ACTIVE_CFG), 69 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 70 }, 71 { 72 .name = "ctl_4", .id = CTL_4, 73 .base = 0x1800, .len = 0x1e0, 74 .features = BIT(DPU_CTL_ACTIVE_CFG), 75 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), 76 }, 77 { 78 .name = "ctl_5", .id = CTL_5, 79 .base = 0x1a00, .len = 0x1e0, 80 .features = BIT(DPU_CTL_ACTIVE_CFG), 81 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), 82 }, 83 }; 84 85 static const struct dpu_sspp_cfg sm8150_sspp[] = { 86 SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f0, VIG_SDM845_MASK, 87 sdm845_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), 88 SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1f0, VIG_SDM845_MASK, 89 sdm845_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), 90 SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1f0, VIG_SDM845_MASK, 91 sdm845_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), 92 SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1f0, VIG_SDM845_MASK, 93 sdm845_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), 94 SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f0, DMA_SDM845_MASK, 95 sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), 96 SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f0, DMA_SDM845_MASK, 97 sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), 98 SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f0, DMA_CURSOR_SDM845_MASK, 99 sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), 100 SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1f0, DMA_CURSOR_SDM845_MASK, 101 sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), 102 }; 103 104 static const struct dpu_lm_cfg sm8150_lm[] = { 105 LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, 106 &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0), 107 LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, 108 &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1), 109 LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, 110 &sdm845_lm_sblk, PINGPONG_2, LM_3, 0), 111 LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK, 112 &sdm845_lm_sblk, PINGPONG_3, LM_2, 0), 113 LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK, 114 &sdm845_lm_sblk, PINGPONG_4, LM_5, 0), 115 LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, 116 &sdm845_lm_sblk, PINGPONG_5, LM_4, 0), 117 }; 118 119 static const struct dpu_dspp_cfg sm8150_dspp[] = { 120 DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, 121 &sm8150_dspp_sblk), 122 DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK, 123 &sm8150_dspp_sblk), 124 DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK, 125 &sm8150_dspp_sblk), 126 DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK, 127 &sm8150_dspp_sblk), 128 }; 129 130 static const struct dpu_pingpong_cfg sm8150_pp[] = { 131 PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, sdm845_pp_sblk_te, 132 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 133 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), 134 PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0, sdm845_pp_sblk_te, 135 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 136 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)), 137 PP_BLK("pingpong_2", PINGPONG_2, 0x71000, MERGE_3D_1, sdm845_pp_sblk, 138 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), 139 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)), 140 PP_BLK("pingpong_3", PINGPONG_3, 0x71800, MERGE_3D_1, sdm845_pp_sblk, 141 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), 142 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)), 143 PP_BLK("pingpong_4", PINGPONG_4, 0x72000, MERGE_3D_2, sdm845_pp_sblk, 144 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), 145 -1), 146 PP_BLK("pingpong_5", PINGPONG_5, 0x72800, MERGE_3D_2, sdm845_pp_sblk, 147 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), 148 -1), 149 }; 150 151 static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = { 152 MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x83000), 153 MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x83100), 154 MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200), 155 }; 156 157 static const struct dpu_dsc_cfg sm8150_dsc[] = { 158 DSC_BLK("dsc_0", DSC_0, 0x80000, BIT(DPU_DSC_OUTPUT_CTRL)), 159 DSC_BLK("dsc_1", DSC_1, 0x80400, BIT(DPU_DSC_OUTPUT_CTRL)), 160 DSC_BLK("dsc_2", DSC_2, 0x80800, BIT(DPU_DSC_OUTPUT_CTRL)), 161 DSC_BLK("dsc_3", DSC_3, 0x80c00, BIT(DPU_DSC_OUTPUT_CTRL)), 162 }; 163 164 static const struct dpu_intf_cfg sm8150_intf[] = { 165 INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25), 166 INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2bc, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27), 167 INTF_BLK("intf_2", INTF_2, 0x6b000, 0x2bc, INTF_DSI, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 28, 29), 168 INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31), 169 }; 170 171 static const struct dpu_perf_cfg sm8150_perf_data = { 172 .max_bw_low = 12800000, 173 .max_bw_high = 12800000, 174 .min_core_ib = 2400000, 175 .min_llcc_ib = 800000, 176 .min_dram_ib = 800000, 177 .min_prefill_lines = 24, 178 .danger_lut_tbl = {0xf, 0xffff, 0x0}, 179 .safe_lut_tbl = {0xfff8, 0xf000, 0xffff}, 180 .qos_lut_tbl = { 181 {.nentry = ARRAY_SIZE(sm8150_qos_linear), 182 .entries = sm8150_qos_linear 183 }, 184 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 185 .entries = sc7180_qos_macrotile 186 }, 187 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 188 .entries = sc7180_qos_nrt 189 }, 190 /* TODO: macrotile-qseed is different from macrotile */ 191 }, 192 .cdp_cfg = { 193 {.rd_enable = 1, .wr_enable = 1}, 194 {.rd_enable = 1, .wr_enable = 0} 195 }, 196 .clk_inefficiency_factor = 105, 197 .bw_inefficiency_factor = 120, 198 }; 199 200 const struct dpu_mdss_cfg dpu_sm8150_cfg = { 201 .caps = &sm8150_dpu_caps, 202 .ubwc = &sm8150_ubwc_cfg, 203 .mdp_count = ARRAY_SIZE(sm8150_mdp), 204 .mdp = sm8150_mdp, 205 .ctl_count = ARRAY_SIZE(sm8150_ctl), 206 .ctl = sm8150_ctl, 207 .sspp_count = ARRAY_SIZE(sm8150_sspp), 208 .sspp = sm8150_sspp, 209 .mixer_count = ARRAY_SIZE(sm8150_lm), 210 .mixer = sm8150_lm, 211 .dspp_count = ARRAY_SIZE(sm8150_dspp), 212 .dspp = sm8150_dspp, 213 .dsc_count = ARRAY_SIZE(sm8150_dsc), 214 .dsc = sm8150_dsc, 215 .pingpong_count = ARRAY_SIZE(sm8150_pp), 216 .pingpong = sm8150_pp, 217 .merge_3d_count = ARRAY_SIZE(sm8150_merge_3d), 218 .merge_3d = sm8150_merge_3d, 219 .intf_count = ARRAY_SIZE(sm8150_intf), 220 .intf = sm8150_intf, 221 .vbif_count = ARRAY_SIZE(sdm845_vbif), 222 .vbif = sdm845_vbif, 223 .reg_dma_count = 1, 224 .dma_cfg = &sm8150_regdma, 225 .perf = &sm8150_perf_data, 226 .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ 227 BIT(MDP_SSPP_TOP0_INTR2) | \ 228 BIT(MDP_SSPP_TOP0_HIST_INTR) | \ 229 BIT(MDP_INTF0_INTR) | \ 230 BIT(MDP_INTF1_INTR) | \ 231 BIT(MDP_INTF2_INTR) | \ 232 BIT(MDP_INTF3_INTR) | \ 233 BIT(MDP_AD4_0_INTR) | \ 234 BIT(MDP_AD4_1_INTR), 235 }; 236 237 #endif 238