1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_4_0_SDM845_H 8 #define _DPU_4_0_SDM845_H 9 10 static const struct dpu_caps sdm845_dpu_caps = { 11 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 12 .max_mixer_blendstages = 0xb, 13 .qseed_type = DPU_SSPP_SCALER_QSEED3, 14 .has_src_split = true, 15 .has_dim_layer = true, 16 .has_idle_pc = true, 17 .has_3d_merge = true, 18 .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 19 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 20 .max_hdeci_exp = MAX_HORZ_DECIMATION, 21 .max_vdeci_exp = MAX_VERT_DECIMATION, 22 }; 23 24 static const struct dpu_ubwc_cfg sdm845_ubwc_cfg = { 25 .ubwc_version = DPU_HW_UBWC_VER_20, 26 .highest_bank_bit = 0x2, 27 }; 28 29 static const struct dpu_mdp_cfg sdm845_mdp[] = { 30 { 31 .name = "top_0", .id = MDP_TOP, 32 .base = 0x0, .len = 0x45c, 33 .features = BIT(DPU_MDP_AUDIO_SELECT), 34 .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 35 .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, 36 .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, 37 .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, 38 .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 39 .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 40 .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, 41 .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, 42 }, 43 }; 44 45 static const struct dpu_ctl_cfg sdm845_ctl[] = { 46 { 47 .name = "ctl_0", .id = CTL_0, 48 .base = 0x1000, .len = 0xe4, 49 .features = BIT(DPU_CTL_SPLIT_DISPLAY), 50 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 51 }, 52 { 53 .name = "ctl_1", .id = CTL_1, 54 .base = 0x1200, .len = 0xe4, 55 .features = BIT(DPU_CTL_SPLIT_DISPLAY), 56 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 57 }, 58 { 59 .name = "ctl_2", .id = CTL_2, 60 .base = 0x1400, .len = 0xe4, 61 .features = 0, 62 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 63 }, 64 { 65 .name = "ctl_3", .id = CTL_3, 66 .base = 0x1600, .len = 0xe4, 67 .features = 0, 68 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 69 }, 70 { 71 .name = "ctl_4", .id = CTL_4, 72 .base = 0x1800, .len = 0xe4, 73 .features = 0, 74 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), 75 }, 76 }; 77 78 static const struct dpu_sspp_cfg sdm845_sspp[] = { 79 SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1c8, VIG_SDM845_MASK_SDMA, 80 sdm845_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), 81 SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1c8, VIG_SDM845_MASK_SDMA, 82 sdm845_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), 83 SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1c8, VIG_SDM845_MASK_SDMA, 84 sdm845_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), 85 SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1c8, VIG_SDM845_MASK_SDMA, 86 sdm845_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), 87 SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1c8, DMA_SDM845_MASK_SDMA, 88 sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), 89 SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1c8, DMA_SDM845_MASK_SDMA, 90 sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), 91 SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1c8, DMA_CURSOR_SDM845_MASK_SDMA, 92 sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), 93 SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1c8, DMA_CURSOR_SDM845_MASK_SDMA, 94 sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), 95 }; 96 97 static const struct dpu_lm_cfg sdm845_lm[] = { 98 LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, 99 &sdm845_lm_sblk, PINGPONG_0, LM_1, 0), 100 LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, 101 &sdm845_lm_sblk, PINGPONG_1, LM_0, 0), 102 LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, 103 &sdm845_lm_sblk, PINGPONG_2, LM_5, 0), 104 LM_BLK("lm_3", LM_3, 0x0, MIXER_SDM845_MASK, 105 &sdm845_lm_sblk, PINGPONG_MAX, 0, 0), 106 LM_BLK("lm_4", LM_4, 0x0, MIXER_SDM845_MASK, 107 &sdm845_lm_sblk, PINGPONG_MAX, 0, 0), 108 LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, 109 &sdm845_lm_sblk, PINGPONG_3, LM_2, 0), 110 }; 111 112 static const struct dpu_pingpong_cfg sdm845_pp[] = { 113 PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te, 114 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 115 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), 116 PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te, 117 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 118 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)), 119 PP_BLK("pingpong_2", PINGPONG_2, 0x71000, 0, sdm845_pp_sblk, 120 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), 121 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)), 122 PP_BLK("pingpong_3", PINGPONG_3, 0x71800, 0, sdm845_pp_sblk, 123 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), 124 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)), 125 }; 126 127 static const struct dpu_dsc_cfg sdm845_dsc[] = { 128 DSC_BLK("dsc_0", DSC_0, 0x80000, 0), 129 DSC_BLK("dsc_1", DSC_1, 0x80400, 0), 130 DSC_BLK("dsc_2", DSC_2, 0x80800, 0), 131 DSC_BLK("dsc_3", DSC_3, 0x80c00, 0), 132 }; 133 134 static const struct dpu_intf_cfg sdm845_intf[] = { 135 INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25), 136 INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27), 137 INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, 1, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29), 138 INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 1, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31), 139 }; 140 141 static const struct dpu_perf_cfg sdm845_perf_data = { 142 .max_bw_low = 6800000, 143 .max_bw_high = 6800000, 144 .min_core_ib = 2400000, 145 .min_llcc_ib = 800000, 146 .min_dram_ib = 800000, 147 .undersized_prefill_lines = 2, 148 .xtra_prefill_lines = 2, 149 .dest_scale_prefill_lines = 3, 150 .macrotile_prefill_lines = 4, 151 .yuv_nv12_prefill_lines = 8, 152 .linear_prefill_lines = 1, 153 .downscaling_prefill_lines = 1, 154 .amortizable_threshold = 25, 155 .min_prefill_lines = 24, 156 .danger_lut_tbl = {0xf, 0xffff, 0x0}, 157 .safe_lut_tbl = {0xfff0, 0xf000, 0xffff}, 158 .qos_lut_tbl = { 159 {.nentry = ARRAY_SIZE(sdm845_qos_linear), 160 .entries = sdm845_qos_linear 161 }, 162 {.nentry = ARRAY_SIZE(sdm845_qos_macrotile), 163 .entries = sdm845_qos_macrotile 164 }, 165 {.nentry = ARRAY_SIZE(sdm845_qos_nrt), 166 .entries = sdm845_qos_nrt 167 }, 168 }, 169 .cdp_cfg = { 170 {.rd_enable = 1, .wr_enable = 1}, 171 {.rd_enable = 1, .wr_enable = 0} 172 }, 173 .clk_inefficiency_factor = 105, 174 .bw_inefficiency_factor = 120, 175 }; 176 177 const struct dpu_mdss_cfg dpu_sdm845_cfg = { 178 .caps = &sdm845_dpu_caps, 179 .ubwc = &sdm845_ubwc_cfg, 180 .mdp_count = ARRAY_SIZE(sdm845_mdp), 181 .mdp = sdm845_mdp, 182 .ctl_count = ARRAY_SIZE(sdm845_ctl), 183 .ctl = sdm845_ctl, 184 .sspp_count = ARRAY_SIZE(sdm845_sspp), 185 .sspp = sdm845_sspp, 186 .mixer_count = ARRAY_SIZE(sdm845_lm), 187 .mixer = sdm845_lm, 188 .pingpong_count = ARRAY_SIZE(sdm845_pp), 189 .pingpong = sdm845_pp, 190 .dsc_count = ARRAY_SIZE(sdm845_dsc), 191 .dsc = sdm845_dsc, 192 .intf_count = ARRAY_SIZE(sdm845_intf), 193 .intf = sdm845_intf, 194 .vbif_count = ARRAY_SIZE(sdm845_vbif), 195 .vbif = sdm845_vbif, 196 .reg_dma_count = 1, 197 .dma_cfg = &sdm845_regdma, 198 .perf = &sdm845_perf_data, 199 .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ 200 BIT(MDP_SSPP_TOP0_INTR2) | \ 201 BIT(MDP_SSPP_TOP0_HIST_INTR) | \ 202 BIT(MDP_INTF0_INTR) | \ 203 BIT(MDP_INTF1_INTR) | \ 204 BIT(MDP_INTF2_INTR) | \ 205 BIT(MDP_INTF3_INTR) | \ 206 BIT(MDP_AD4_0_INTR) | \ 207 BIT(MDP_AD4_1_INTR), 208 }; 209 210 #endif 211