1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_4_0_SDM845_H 8 #define _DPU_4_0_SDM845_H 9 10 static const struct dpu_caps sdm845_dpu_caps = { 11 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 12 .max_mixer_blendstages = 0xb, 13 .qseed_type = DPU_SSPP_SCALER_QSEED3, 14 .has_src_split = true, 15 .has_dim_layer = true, 16 .has_idle_pc = true, 17 .has_3d_merge = true, 18 .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 19 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 20 .max_hdeci_exp = MAX_HORZ_DECIMATION, 21 .max_vdeci_exp = MAX_VERT_DECIMATION, 22 }; 23 24 static const struct dpu_ubwc_cfg sdm845_ubwc_cfg = { 25 .ubwc_version = DPU_HW_UBWC_VER_20, 26 .highest_bank_bit = 0x2, 27 }; 28 29 static const struct dpu_mdp_cfg sdm845_mdp = { 30 .name = "top_0", 31 .base = 0x0, .len = 0x45c, 32 .features = BIT(DPU_MDP_AUDIO_SELECT) | BIT(DPU_MDP_VSYNC_SEL), 33 .clk_ctrls = { 34 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 35 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, 36 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, 37 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, 38 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 39 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 40 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, 41 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, 42 }, 43 }; 44 45 static const struct dpu_ctl_cfg sdm845_ctl[] = { 46 { 47 .name = "ctl_0", .id = CTL_0, 48 .base = 0x1000, .len = 0xe4, 49 .features = BIT(DPU_CTL_SPLIT_DISPLAY), 50 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 51 }, { 52 .name = "ctl_1", .id = CTL_1, 53 .base = 0x1200, .len = 0xe4, 54 .features = BIT(DPU_CTL_SPLIT_DISPLAY), 55 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 56 }, { 57 .name = "ctl_2", .id = CTL_2, 58 .base = 0x1400, .len = 0xe4, 59 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 60 }, { 61 .name = "ctl_3", .id = CTL_3, 62 .base = 0x1600, .len = 0xe4, 63 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 64 }, { 65 .name = "ctl_4", .id = CTL_4, 66 .base = 0x1800, .len = 0xe4, 67 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), 68 }, 69 }; 70 71 static const struct dpu_sspp_cfg sdm845_sspp[] = { 72 { 73 .name = "sspp_0", .id = SSPP_VIG0, 74 .base = 0x4000, .len = 0x1c8, 75 .features = VIG_SDM845_MASK_SDMA, 76 .sblk = &sdm845_vig_sblk_0, 77 .xin_id = 0, 78 .type = SSPP_TYPE_VIG, 79 .clk_ctrl = DPU_CLK_CTRL_VIG0, 80 }, { 81 .name = "sspp_1", .id = SSPP_VIG1, 82 .base = 0x6000, .len = 0x1c8, 83 .features = VIG_SDM845_MASK_SDMA, 84 .sblk = &sdm845_vig_sblk_1, 85 .xin_id = 4, 86 .type = SSPP_TYPE_VIG, 87 .clk_ctrl = DPU_CLK_CTRL_VIG1, 88 }, { 89 .name = "sspp_2", .id = SSPP_VIG2, 90 .base = 0x8000, .len = 0x1c8, 91 .features = VIG_SDM845_MASK_SDMA, 92 .sblk = &sdm845_vig_sblk_2, 93 .xin_id = 8, 94 .type = SSPP_TYPE_VIG, 95 .clk_ctrl = DPU_CLK_CTRL_VIG2, 96 }, { 97 .name = "sspp_3", .id = SSPP_VIG3, 98 .base = 0xa000, .len = 0x1c8, 99 .features = VIG_SDM845_MASK_SDMA, 100 .sblk = &sdm845_vig_sblk_3, 101 .xin_id = 12, 102 .type = SSPP_TYPE_VIG, 103 .clk_ctrl = DPU_CLK_CTRL_VIG3, 104 }, { 105 .name = "sspp_8", .id = SSPP_DMA0, 106 .base = 0x24000, .len = 0x1c8, 107 .features = DMA_SDM845_MASK_SDMA, 108 .sblk = &sdm845_dma_sblk_0, 109 .xin_id = 1, 110 .type = SSPP_TYPE_DMA, 111 .clk_ctrl = DPU_CLK_CTRL_DMA0, 112 }, { 113 .name = "sspp_9", .id = SSPP_DMA1, 114 .base = 0x26000, .len = 0x1c8, 115 .features = DMA_SDM845_MASK_SDMA, 116 .sblk = &sdm845_dma_sblk_1, 117 .xin_id = 5, 118 .type = SSPP_TYPE_DMA, 119 .clk_ctrl = DPU_CLK_CTRL_DMA1, 120 }, { 121 .name = "sspp_10", .id = SSPP_DMA2, 122 .base = 0x28000, .len = 0x1c8, 123 .features = DMA_CURSOR_SDM845_MASK_SDMA, 124 .sblk = &sdm845_dma_sblk_2, 125 .xin_id = 9, 126 .type = SSPP_TYPE_DMA, 127 .clk_ctrl = DPU_CLK_CTRL_DMA2, 128 }, { 129 .name = "sspp_11", .id = SSPP_DMA3, 130 .base = 0x2a000, .len = 0x1c8, 131 .features = DMA_CURSOR_SDM845_MASK_SDMA, 132 .sblk = &sdm845_dma_sblk_3, 133 .xin_id = 13, 134 .type = SSPP_TYPE_DMA, 135 .clk_ctrl = DPU_CLK_CTRL_DMA3, 136 }, 137 }; 138 139 static const struct dpu_lm_cfg sdm845_lm[] = { 140 { 141 .name = "lm_0", .id = LM_0, 142 .base = 0x44000, .len = 0x320, 143 .features = MIXER_SDM845_MASK, 144 .sblk = &sdm845_lm_sblk, 145 .lm_pair = LM_1, 146 .pingpong = PINGPONG_0, 147 .dspp = DSPP_0, 148 }, { 149 .name = "lm_1", .id = LM_1, 150 .base = 0x45000, .len = 0x320, 151 .features = MIXER_SDM845_MASK, 152 .sblk = &sdm845_lm_sblk, 153 .lm_pair = LM_0, 154 .pingpong = PINGPONG_1, 155 .dspp = DSPP_1, 156 }, { 157 .name = "lm_2", .id = LM_2, 158 .base = 0x46000, .len = 0x320, 159 .features = MIXER_SDM845_MASK, 160 .sblk = &sdm845_lm_sblk, 161 .lm_pair = LM_5, 162 .pingpong = PINGPONG_2, 163 .dspp = DSPP_2, 164 }, { 165 .name = "lm_3", .id = LM_3, 166 .base = 0x0, .len = 0x320, 167 .features = MIXER_SDM845_MASK, 168 .sblk = &sdm845_lm_sblk, 169 .pingpong = PINGPONG_NONE, 170 .dspp = DSPP_3, 171 }, { 172 .name = "lm_4", .id = LM_4, 173 .base = 0x0, .len = 0x320, 174 .features = MIXER_SDM845_MASK, 175 .sblk = &sdm845_lm_sblk, 176 .pingpong = PINGPONG_NONE, 177 }, { 178 .name = "lm_5", .id = LM_5, 179 .base = 0x49000, .len = 0x320, 180 .features = MIXER_SDM845_MASK, 181 .sblk = &sdm845_lm_sblk, 182 .lm_pair = LM_2, 183 .pingpong = PINGPONG_3, 184 }, 185 }; 186 187 static const struct dpu_dspp_cfg sdm845_dspp[] = { 188 { 189 .name = "dspp_0", .id = DSPP_0, 190 .base = 0x54000, .len = 0x1800, 191 .features = DSPP_SC7180_MASK, 192 .sblk = &sdm845_dspp_sblk, 193 }, { 194 .name = "dspp_1", .id = DSPP_1, 195 .base = 0x56000, .len = 0x1800, 196 .features = DSPP_SC7180_MASK, 197 .sblk = &sdm845_dspp_sblk, 198 }, { 199 .name = "dspp_2", .id = DSPP_2, 200 .base = 0x58000, .len = 0x1800, 201 .features = DSPP_SC7180_MASK, 202 .sblk = &sdm845_dspp_sblk, 203 }, { 204 .name = "dspp_3", .id = DSPP_3, 205 .base = 0x5a000, .len = 0x1800, 206 .features = DSPP_SC7180_MASK, 207 .sblk = &sdm845_dspp_sblk, 208 }, 209 }; 210 211 static const struct dpu_pingpong_cfg sdm845_pp[] = { 212 { 213 .name = "pingpong_0", .id = PINGPONG_0, 214 .base = 0x70000, .len = 0xd4, 215 .features = PINGPONG_SDM845_TE2_MASK, 216 .sblk = &sdm845_pp_sblk_te, 217 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 218 .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), 219 }, { 220 .name = "pingpong_1", .id = PINGPONG_1, 221 .base = 0x70800, .len = 0xd4, 222 .features = PINGPONG_SDM845_TE2_MASK, 223 .sblk = &sdm845_pp_sblk_te, 224 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 225 .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13), 226 }, { 227 .name = "pingpong_2", .id = PINGPONG_2, 228 .base = 0x71000, .len = 0xd4, 229 .features = PINGPONG_SDM845_MASK, 230 .sblk = &sdm845_pp_sblk, 231 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), 232 .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14), 233 }, { 234 .name = "pingpong_3", .id = PINGPONG_3, 235 .base = 0x71800, .len = 0xd4, 236 .features = PINGPONG_SDM845_MASK, 237 .sblk = &sdm845_pp_sblk, 238 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), 239 .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15), 240 }, 241 }; 242 243 static const struct dpu_dsc_cfg sdm845_dsc[] = { 244 { 245 .name = "dsc_0", .id = DSC_0, 246 .base = 0x80000, .len = 0x140, 247 }, { 248 .name = "dsc_1", .id = DSC_1, 249 .base = 0x80400, .len = 0x140, 250 }, { 251 .name = "dsc_2", .id = DSC_2, 252 .base = 0x80800, .len = 0x140, 253 }, { 254 .name = "dsc_3", .id = DSC_3, 255 .base = 0x80c00, .len = 0x140, 256 }, 257 }; 258 259 static const struct dpu_intf_cfg sdm845_intf[] = { 260 INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SDM845_MASK, 261 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), 262 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)), 263 INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SDM845_MASK, 264 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 265 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)), 266 INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, MSM_DSI_CONTROLLER_1, 24, INTF_SDM845_MASK, 267 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), 268 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29)), 269 INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SDM845_MASK, 270 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), 271 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)), 272 }; 273 274 static const struct dpu_perf_cfg sdm845_perf_data = { 275 .max_bw_low = 6800000, 276 .max_bw_high = 6800000, 277 .min_core_ib = 2400000, 278 .min_llcc_ib = 800000, 279 .min_dram_ib = 800000, 280 .undersized_prefill_lines = 2, 281 .xtra_prefill_lines = 2, 282 .dest_scale_prefill_lines = 3, 283 .macrotile_prefill_lines = 4, 284 .yuv_nv12_prefill_lines = 8, 285 .linear_prefill_lines = 1, 286 .downscaling_prefill_lines = 1, 287 .amortizable_threshold = 25, 288 .min_prefill_lines = 24, 289 .danger_lut_tbl = {0xf, 0xffff, 0x0}, 290 .safe_lut_tbl = {0xfff0, 0xf000, 0xffff}, 291 .qos_lut_tbl = { 292 {.nentry = ARRAY_SIZE(sdm845_qos_linear), 293 .entries = sdm845_qos_linear 294 }, 295 {.nentry = ARRAY_SIZE(sdm845_qos_macrotile), 296 .entries = sdm845_qos_macrotile 297 }, 298 {.nentry = ARRAY_SIZE(sdm845_qos_nrt), 299 .entries = sdm845_qos_nrt 300 }, 301 }, 302 .cdp_cfg = { 303 {.rd_enable = 1, .wr_enable = 1}, 304 {.rd_enable = 1, .wr_enable = 0} 305 }, 306 .clk_inefficiency_factor = 105, 307 .bw_inefficiency_factor = 120, 308 }; 309 310 const struct dpu_mdss_cfg dpu_sdm845_cfg = { 311 .caps = &sdm845_dpu_caps, 312 .ubwc = &sdm845_ubwc_cfg, 313 .mdp = &sdm845_mdp, 314 .ctl_count = ARRAY_SIZE(sdm845_ctl), 315 .ctl = sdm845_ctl, 316 .sspp_count = ARRAY_SIZE(sdm845_sspp), 317 .sspp = sdm845_sspp, 318 .mixer_count = ARRAY_SIZE(sdm845_lm), 319 .mixer = sdm845_lm, 320 .dspp_count = ARRAY_SIZE(sdm845_dspp), 321 .dspp = sdm845_dspp, 322 .pingpong_count = ARRAY_SIZE(sdm845_pp), 323 .pingpong = sdm845_pp, 324 .dsc_count = ARRAY_SIZE(sdm845_dsc), 325 .dsc = sdm845_dsc, 326 .intf_count = ARRAY_SIZE(sdm845_intf), 327 .intf = sdm845_intf, 328 .vbif_count = ARRAY_SIZE(sdm845_vbif), 329 .vbif = sdm845_vbif, 330 .perf = &sdm845_perf_data, 331 .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ 332 BIT(MDP_SSPP_TOP0_INTR2) | \ 333 BIT(MDP_SSPP_TOP0_HIST_INTR) | \ 334 BIT(MDP_INTF0_INTR) | \ 335 BIT(MDP_INTF1_INTR) | \ 336 BIT(MDP_INTF2_INTR) | \ 337 BIT(MDP_INTF3_INTR) | \ 338 BIT(MDP_AD4_0_INTR) | \ 339 BIT(MDP_AD4_1_INTR), 340 }; 341 342 #endif 343