1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_3_0_MSM8998_H 8 #define _DPU_3_0_MSM8998_H 9 10 static const struct dpu_caps msm8998_dpu_caps = { 11 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 12 .max_mixer_blendstages = 0x7, 13 .qseed_type = DPU_SSPP_SCALER_QSEED3, 14 .has_src_split = true, 15 .has_dim_layer = true, 16 .has_idle_pc = true, 17 .has_3d_merge = true, 18 .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 19 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 20 .max_hdeci_exp = MAX_HORZ_DECIMATION, 21 .max_vdeci_exp = MAX_VERT_DECIMATION, 22 }; 23 24 static const struct dpu_ubwc_cfg msm8998_ubwc_cfg = { 25 .ubwc_version = DPU_HW_UBWC_VER_10, 26 .highest_bank_bit = 0x2, 27 }; 28 29 static const struct dpu_mdp_cfg msm8998_mdp[] = { 30 { 31 .name = "top_0", .id = MDP_TOP, 32 .base = 0x0, .len = 0x458, 33 .features = 0, 34 .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 35 .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, 36 .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, 37 .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, 38 .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 39 .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 40 .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 }, 41 .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 12 }, 42 .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 15 }, 43 .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { .reg_off = 0x3b0, .bit_off = 15 }, 44 }, 45 }; 46 47 static const struct dpu_ctl_cfg msm8998_ctl[] = { 48 { 49 .name = "ctl_0", .id = CTL_0, 50 .base = 0x1000, .len = 0x94, 51 .features = BIT(DPU_CTL_SPLIT_DISPLAY), 52 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 53 }, 54 { 55 .name = "ctl_1", .id = CTL_1, 56 .base = 0x1200, .len = 0x94, 57 .features = 0, 58 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 59 }, 60 { 61 .name = "ctl_2", .id = CTL_2, 62 .base = 0x1400, .len = 0x94, 63 .features = BIT(DPU_CTL_SPLIT_DISPLAY), 64 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 65 }, 66 { 67 .name = "ctl_3", .id = CTL_3, 68 .base = 0x1600, .len = 0x94, 69 .features = 0, 70 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 71 }, 72 { 73 .name = "ctl_4", .id = CTL_4, 74 .base = 0x1800, .len = 0x94, 75 .features = 0, 76 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), 77 }, 78 }; 79 80 static const struct dpu_sspp_cfg msm8998_sspp[] = { 81 SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1ac, VIG_MSM8998_MASK, 82 msm8998_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), 83 SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1ac, VIG_MSM8998_MASK, 84 msm8998_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), 85 SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1ac, VIG_MSM8998_MASK, 86 msm8998_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), 87 SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1ac, VIG_MSM8998_MASK, 88 msm8998_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), 89 SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1ac, DMA_MSM8998_MASK, 90 sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), 91 SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1ac, DMA_MSM8998_MASK, 92 sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), 93 SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1ac, DMA_CURSOR_MSM8998_MASK, 94 sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), 95 SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1ac, DMA_CURSOR_MSM8998_MASK, 96 sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), 97 }; 98 99 static const struct dpu_lm_cfg msm8998_lm[] = { 100 LM_BLK("lm_0", LM_0, 0x44000, MIXER_MSM8998_MASK, 101 &msm8998_lm_sblk, PINGPONG_0, LM_2, DSPP_0), 102 LM_BLK("lm_1", LM_1, 0x45000, MIXER_MSM8998_MASK, 103 &msm8998_lm_sblk, PINGPONG_1, LM_5, DSPP_1), 104 LM_BLK("lm_2", LM_2, 0x46000, MIXER_MSM8998_MASK, 105 &msm8998_lm_sblk, PINGPONG_2, LM_0, 0), 106 LM_BLK("lm_3", LM_3, 0x47000, MIXER_MSM8998_MASK, 107 &msm8998_lm_sblk, PINGPONG_MAX, 0, 0), 108 LM_BLK("lm_4", LM_4, 0x48000, MIXER_MSM8998_MASK, 109 &msm8998_lm_sblk, PINGPONG_MAX, 0, 0), 110 LM_BLK("lm_5", LM_5, 0x49000, MIXER_MSM8998_MASK, 111 &msm8998_lm_sblk, PINGPONG_3, LM_1, 0), 112 }; 113 114 static const struct dpu_pingpong_cfg msm8998_pp[] = { 115 PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te, 116 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 117 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), 118 PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te, 119 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 120 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)), 121 PP_BLK("pingpong_2", PINGPONG_2, 0x71000, 0, sdm845_pp_sblk, 122 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), 123 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)), 124 PP_BLK("pingpong_3", PINGPONG_3, 0x71800, 0, sdm845_pp_sblk, 125 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), 126 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)), 127 }; 128 129 static const struct dpu_dspp_cfg msm8998_dspp[] = { 130 DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_MSM8998_MASK, 131 &msm8998_dspp_sblk), 132 DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_MSM8998_MASK, 133 &msm8998_dspp_sblk), 134 }; 135 136 static const struct dpu_intf_cfg msm8998_intf[] = { 137 INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25), 138 INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27), 139 INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, 1, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29), 140 INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_HDMI, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31), 141 }; 142 143 static const struct dpu_perf_cfg msm8998_perf_data = { 144 .max_bw_low = 6700000, 145 .max_bw_high = 6700000, 146 .min_core_ib = 2400000, 147 .min_llcc_ib = 800000, 148 .min_dram_ib = 800000, 149 .undersized_prefill_lines = 2, 150 .xtra_prefill_lines = 2, 151 .dest_scale_prefill_lines = 3, 152 .macrotile_prefill_lines = 4, 153 .yuv_nv12_prefill_lines = 8, 154 .linear_prefill_lines = 1, 155 .downscaling_prefill_lines = 1, 156 .amortizable_threshold = 25, 157 .min_prefill_lines = 25, 158 .danger_lut_tbl = {0xf, 0xffff, 0x0}, 159 .safe_lut_tbl = {0xfffc, 0xff00, 0xffff}, 160 .qos_lut_tbl = { 161 {.nentry = ARRAY_SIZE(msm8998_qos_linear), 162 .entries = msm8998_qos_linear 163 }, 164 {.nentry = ARRAY_SIZE(msm8998_qos_macrotile), 165 .entries = msm8998_qos_macrotile 166 }, 167 {.nentry = ARRAY_SIZE(msm8998_qos_nrt), 168 .entries = msm8998_qos_nrt 169 }, 170 }, 171 .cdp_cfg = { 172 {.rd_enable = 1, .wr_enable = 1}, 173 {.rd_enable = 1, .wr_enable = 0} 174 }, 175 .clk_inefficiency_factor = 200, 176 .bw_inefficiency_factor = 120, 177 }; 178 179 const struct dpu_mdss_cfg dpu_msm8998_cfg = { 180 .caps = &msm8998_dpu_caps, 181 .ubwc = &msm8998_ubwc_cfg, 182 .mdp_count = ARRAY_SIZE(msm8998_mdp), 183 .mdp = msm8998_mdp, 184 .ctl_count = ARRAY_SIZE(msm8998_ctl), 185 .ctl = msm8998_ctl, 186 .sspp_count = ARRAY_SIZE(msm8998_sspp), 187 .sspp = msm8998_sspp, 188 .mixer_count = ARRAY_SIZE(msm8998_lm), 189 .mixer = msm8998_lm, 190 .dspp_count = ARRAY_SIZE(msm8998_dspp), 191 .dspp = msm8998_dspp, 192 .pingpong_count = ARRAY_SIZE(msm8998_pp), 193 .pingpong = msm8998_pp, 194 .intf_count = ARRAY_SIZE(msm8998_intf), 195 .intf = msm8998_intf, 196 .vbif_count = ARRAY_SIZE(msm8998_vbif), 197 .vbif = msm8998_vbif, 198 .reg_dma_count = 0, 199 .perf = &msm8998_perf_data, 200 .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ 201 BIT(MDP_SSPP_TOP0_INTR2) | \ 202 BIT(MDP_SSPP_TOP0_HIST_INTR) | \ 203 BIT(MDP_INTF0_INTR) | \ 204 BIT(MDP_INTF1_INTR) | \ 205 BIT(MDP_INTF2_INTR) | \ 206 BIT(MDP_INTF3_INTR) | \ 207 BIT(MDP_INTF4_INTR), 208 }; 209 210 #endif 211