1*1c611c48SDmitry Baryshkov /* SPDX-License-Identifier: GPL-2.0-only */ 2*1c611c48SDmitry Baryshkov /* 3*1c611c48SDmitry Baryshkov * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4*1c611c48SDmitry Baryshkov * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5*1c611c48SDmitry Baryshkov */ 6*1c611c48SDmitry Baryshkov 7*1c611c48SDmitry Baryshkov #ifndef _DPU_3_0_MSM8998_H 8*1c611c48SDmitry Baryshkov #define _DPU_3_0_MSM8998_H 9*1c611c48SDmitry Baryshkov 10*1c611c48SDmitry Baryshkov static const struct dpu_caps msm8998_dpu_caps = { 11*1c611c48SDmitry Baryshkov .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 12*1c611c48SDmitry Baryshkov .max_mixer_blendstages = 0x7, 13*1c611c48SDmitry Baryshkov .qseed_type = DPU_SSPP_SCALER_QSEED3, 14*1c611c48SDmitry Baryshkov .has_src_split = true, 15*1c611c48SDmitry Baryshkov .has_dim_layer = true, 16*1c611c48SDmitry Baryshkov .has_idle_pc = true, 17*1c611c48SDmitry Baryshkov .has_3d_merge = true, 18*1c611c48SDmitry Baryshkov .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 19*1c611c48SDmitry Baryshkov .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 20*1c611c48SDmitry Baryshkov .max_hdeci_exp = MAX_HORZ_DECIMATION, 21*1c611c48SDmitry Baryshkov .max_vdeci_exp = MAX_VERT_DECIMATION, 22*1c611c48SDmitry Baryshkov }; 23*1c611c48SDmitry Baryshkov 24*1c611c48SDmitry Baryshkov static const struct dpu_ubwc_cfg msm8998_ubwc_cfg = { 25*1c611c48SDmitry Baryshkov .ubwc_version = DPU_HW_UBWC_VER_10, 26*1c611c48SDmitry Baryshkov .highest_bank_bit = 0x2, 27*1c611c48SDmitry Baryshkov }; 28*1c611c48SDmitry Baryshkov 29*1c611c48SDmitry Baryshkov static const struct dpu_mdp_cfg msm8998_mdp[] = { 30*1c611c48SDmitry Baryshkov { 31*1c611c48SDmitry Baryshkov .name = "top_0", .id = MDP_TOP, 32*1c611c48SDmitry Baryshkov .base = 0x0, .len = 0x458, 33*1c611c48SDmitry Baryshkov .features = 0, 34*1c611c48SDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 35*1c611c48SDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, 36*1c611c48SDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, 37*1c611c48SDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, 38*1c611c48SDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 39*1c611c48SDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 40*1c611c48SDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 }, 41*1c611c48SDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 12 }, 42*1c611c48SDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 15 }, 43*1c611c48SDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { .reg_off = 0x3b0, .bit_off = 15 }, 44*1c611c48SDmitry Baryshkov }, 45*1c611c48SDmitry Baryshkov }; 46*1c611c48SDmitry Baryshkov 47*1c611c48SDmitry Baryshkov static const struct dpu_ctl_cfg msm8998_ctl[] = { 48*1c611c48SDmitry Baryshkov { 49*1c611c48SDmitry Baryshkov .name = "ctl_0", .id = CTL_0, 50*1c611c48SDmitry Baryshkov .base = 0x1000, .len = 0x94, 51*1c611c48SDmitry Baryshkov .features = BIT(DPU_CTL_SPLIT_DISPLAY), 52*1c611c48SDmitry Baryshkov .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 53*1c611c48SDmitry Baryshkov }, 54*1c611c48SDmitry Baryshkov { 55*1c611c48SDmitry Baryshkov .name = "ctl_1", .id = CTL_1, 56*1c611c48SDmitry Baryshkov .base = 0x1200, .len = 0x94, 57*1c611c48SDmitry Baryshkov .features = 0, 58*1c611c48SDmitry Baryshkov .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 59*1c611c48SDmitry Baryshkov }, 60*1c611c48SDmitry Baryshkov { 61*1c611c48SDmitry Baryshkov .name = "ctl_2", .id = CTL_2, 62*1c611c48SDmitry Baryshkov .base = 0x1400, .len = 0x94, 63*1c611c48SDmitry Baryshkov .features = BIT(DPU_CTL_SPLIT_DISPLAY), 64*1c611c48SDmitry Baryshkov .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 65*1c611c48SDmitry Baryshkov }, 66*1c611c48SDmitry Baryshkov { 67*1c611c48SDmitry Baryshkov .name = "ctl_3", .id = CTL_3, 68*1c611c48SDmitry Baryshkov .base = 0x1600, .len = 0x94, 69*1c611c48SDmitry Baryshkov .features = 0, 70*1c611c48SDmitry Baryshkov .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 71*1c611c48SDmitry Baryshkov }, 72*1c611c48SDmitry Baryshkov { 73*1c611c48SDmitry Baryshkov .name = "ctl_4", .id = CTL_4, 74*1c611c48SDmitry Baryshkov .base = 0x1800, .len = 0x94, 75*1c611c48SDmitry Baryshkov .features = 0, 76*1c611c48SDmitry Baryshkov .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), 77*1c611c48SDmitry Baryshkov }, 78*1c611c48SDmitry Baryshkov }; 79*1c611c48SDmitry Baryshkov 80*1c611c48SDmitry Baryshkov static const struct dpu_sspp_cfg msm8998_sspp[] = { 81*1c611c48SDmitry Baryshkov SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1ac, VIG_MSM8998_MASK, 82*1c611c48SDmitry Baryshkov msm8998_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), 83*1c611c48SDmitry Baryshkov SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1ac, VIG_MSM8998_MASK, 84*1c611c48SDmitry Baryshkov msm8998_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), 85*1c611c48SDmitry Baryshkov SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1ac, VIG_MSM8998_MASK, 86*1c611c48SDmitry Baryshkov msm8998_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), 87*1c611c48SDmitry Baryshkov SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1ac, VIG_MSM8998_MASK, 88*1c611c48SDmitry Baryshkov msm8998_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), 89*1c611c48SDmitry Baryshkov SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1ac, DMA_MSM8998_MASK, 90*1c611c48SDmitry Baryshkov sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), 91*1c611c48SDmitry Baryshkov SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1ac, DMA_MSM8998_MASK, 92*1c611c48SDmitry Baryshkov sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), 93*1c611c48SDmitry Baryshkov SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1ac, DMA_CURSOR_MSM8998_MASK, 94*1c611c48SDmitry Baryshkov sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), 95*1c611c48SDmitry Baryshkov SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1ac, DMA_CURSOR_MSM8998_MASK, 96*1c611c48SDmitry Baryshkov sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), 97*1c611c48SDmitry Baryshkov }; 98*1c611c48SDmitry Baryshkov 99*1c611c48SDmitry Baryshkov static const struct dpu_lm_cfg msm8998_lm[] = { 100*1c611c48SDmitry Baryshkov LM_BLK("lm_0", LM_0, 0x44000, MIXER_MSM8998_MASK, 101*1c611c48SDmitry Baryshkov &msm8998_lm_sblk, PINGPONG_0, LM_2, DSPP_0), 102*1c611c48SDmitry Baryshkov LM_BLK("lm_1", LM_1, 0x45000, MIXER_MSM8998_MASK, 103*1c611c48SDmitry Baryshkov &msm8998_lm_sblk, PINGPONG_1, LM_5, DSPP_1), 104*1c611c48SDmitry Baryshkov LM_BLK("lm_2", LM_2, 0x46000, MIXER_MSM8998_MASK, 105*1c611c48SDmitry Baryshkov &msm8998_lm_sblk, PINGPONG_2, LM_0, 0), 106*1c611c48SDmitry Baryshkov LM_BLK("lm_3", LM_3, 0x47000, MIXER_MSM8998_MASK, 107*1c611c48SDmitry Baryshkov &msm8998_lm_sblk, PINGPONG_MAX, 0, 0), 108*1c611c48SDmitry Baryshkov LM_BLK("lm_4", LM_4, 0x48000, MIXER_MSM8998_MASK, 109*1c611c48SDmitry Baryshkov &msm8998_lm_sblk, PINGPONG_MAX, 0, 0), 110*1c611c48SDmitry Baryshkov LM_BLK("lm_5", LM_5, 0x49000, MIXER_MSM8998_MASK, 111*1c611c48SDmitry Baryshkov &msm8998_lm_sblk, PINGPONG_3, LM_1, 0), 112*1c611c48SDmitry Baryshkov }; 113*1c611c48SDmitry Baryshkov 114*1c611c48SDmitry Baryshkov static const struct dpu_dspp_cfg msm8998_dspp[] = { 115*1c611c48SDmitry Baryshkov DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_MSM8998_MASK, 116*1c611c48SDmitry Baryshkov &msm8998_dspp_sblk), 117*1c611c48SDmitry Baryshkov DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_MSM8998_MASK, 118*1c611c48SDmitry Baryshkov &msm8998_dspp_sblk), 119*1c611c48SDmitry Baryshkov }; 120*1c611c48SDmitry Baryshkov 121*1c611c48SDmitry Baryshkov static const struct dpu_intf_cfg msm8998_intf[] = { 122*1c611c48SDmitry Baryshkov INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25), 123*1c611c48SDmitry Baryshkov INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27), 124*1c611c48SDmitry Baryshkov INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, 1, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29), 125*1c611c48SDmitry Baryshkov INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_HDMI, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31), 126*1c611c48SDmitry Baryshkov }; 127*1c611c48SDmitry Baryshkov 128*1c611c48SDmitry Baryshkov static const struct dpu_perf_cfg msm8998_perf_data = { 129*1c611c48SDmitry Baryshkov .max_bw_low = 6700000, 130*1c611c48SDmitry Baryshkov .max_bw_high = 6700000, 131*1c611c48SDmitry Baryshkov .min_core_ib = 2400000, 132*1c611c48SDmitry Baryshkov .min_llcc_ib = 800000, 133*1c611c48SDmitry Baryshkov .min_dram_ib = 800000, 134*1c611c48SDmitry Baryshkov .undersized_prefill_lines = 2, 135*1c611c48SDmitry Baryshkov .xtra_prefill_lines = 2, 136*1c611c48SDmitry Baryshkov .dest_scale_prefill_lines = 3, 137*1c611c48SDmitry Baryshkov .macrotile_prefill_lines = 4, 138*1c611c48SDmitry Baryshkov .yuv_nv12_prefill_lines = 8, 139*1c611c48SDmitry Baryshkov .linear_prefill_lines = 1, 140*1c611c48SDmitry Baryshkov .downscaling_prefill_lines = 1, 141*1c611c48SDmitry Baryshkov .amortizable_threshold = 25, 142*1c611c48SDmitry Baryshkov .min_prefill_lines = 25, 143*1c611c48SDmitry Baryshkov .danger_lut_tbl = {0xf, 0xffff, 0x0}, 144*1c611c48SDmitry Baryshkov .safe_lut_tbl = {0xfffc, 0xff00, 0xffff}, 145*1c611c48SDmitry Baryshkov .qos_lut_tbl = { 146*1c611c48SDmitry Baryshkov {.nentry = ARRAY_SIZE(msm8998_qos_linear), 147*1c611c48SDmitry Baryshkov .entries = msm8998_qos_linear 148*1c611c48SDmitry Baryshkov }, 149*1c611c48SDmitry Baryshkov {.nentry = ARRAY_SIZE(msm8998_qos_macrotile), 150*1c611c48SDmitry Baryshkov .entries = msm8998_qos_macrotile 151*1c611c48SDmitry Baryshkov }, 152*1c611c48SDmitry Baryshkov {.nentry = ARRAY_SIZE(msm8998_qos_nrt), 153*1c611c48SDmitry Baryshkov .entries = msm8998_qos_nrt 154*1c611c48SDmitry Baryshkov }, 155*1c611c48SDmitry Baryshkov }, 156*1c611c48SDmitry Baryshkov .cdp_cfg = { 157*1c611c48SDmitry Baryshkov {.rd_enable = 1, .wr_enable = 1}, 158*1c611c48SDmitry Baryshkov {.rd_enable = 1, .wr_enable = 0} 159*1c611c48SDmitry Baryshkov }, 160*1c611c48SDmitry Baryshkov .clk_inefficiency_factor = 200, 161*1c611c48SDmitry Baryshkov .bw_inefficiency_factor = 120, 162*1c611c48SDmitry Baryshkov }; 163*1c611c48SDmitry Baryshkov 164*1c611c48SDmitry Baryshkov static const struct dpu_mdss_cfg msm8998_dpu_cfg = { 165*1c611c48SDmitry Baryshkov .caps = &msm8998_dpu_caps, 166*1c611c48SDmitry Baryshkov .ubwc = &msm8998_ubwc_cfg, 167*1c611c48SDmitry Baryshkov .mdp_count = ARRAY_SIZE(msm8998_mdp), 168*1c611c48SDmitry Baryshkov .mdp = msm8998_mdp, 169*1c611c48SDmitry Baryshkov .ctl_count = ARRAY_SIZE(msm8998_ctl), 170*1c611c48SDmitry Baryshkov .ctl = msm8998_ctl, 171*1c611c48SDmitry Baryshkov .sspp_count = ARRAY_SIZE(msm8998_sspp), 172*1c611c48SDmitry Baryshkov .sspp = msm8998_sspp, 173*1c611c48SDmitry Baryshkov .mixer_count = ARRAY_SIZE(msm8998_lm), 174*1c611c48SDmitry Baryshkov .mixer = msm8998_lm, 175*1c611c48SDmitry Baryshkov .dspp_count = ARRAY_SIZE(msm8998_dspp), 176*1c611c48SDmitry Baryshkov .dspp = msm8998_dspp, 177*1c611c48SDmitry Baryshkov .pingpong_count = ARRAY_SIZE(sdm845_pp), 178*1c611c48SDmitry Baryshkov .pingpong = sdm845_pp, 179*1c611c48SDmitry Baryshkov .intf_count = ARRAY_SIZE(msm8998_intf), 180*1c611c48SDmitry Baryshkov .intf = msm8998_intf, 181*1c611c48SDmitry Baryshkov .vbif_count = ARRAY_SIZE(msm8998_vbif), 182*1c611c48SDmitry Baryshkov .vbif = msm8998_vbif, 183*1c611c48SDmitry Baryshkov .reg_dma_count = 0, 184*1c611c48SDmitry Baryshkov .perf = &msm8998_perf_data, 185*1c611c48SDmitry Baryshkov .mdss_irqs = IRQ_SM8250_MASK, 186*1c611c48SDmitry Baryshkov }; 187*1c611c48SDmitry Baryshkov 188*1c611c48SDmitry Baryshkov #endif 189