1 #ifndef ADRENO_PM4_XML 2 #define ADRENO_PM4_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14) 12 - /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14) 13 - /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14) 14 - /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14) 15 - /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14) 16 - /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14) 17 - /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14) 18 - /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14) 19 - /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14) 20 - /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14) 21 - /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14) 22 - /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14) 23 - /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14) 24 25 Copyright (C) 2013-2020 by the following authors: 26 - Rob Clark <robdclark@gmail.com> (robclark) 27 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) 28 29 Permission is hereby granted, free of charge, to any person obtaining 30 a copy of this software and associated documentation files (the 31 "Software"), to deal in the Software without restriction, including 32 without limitation the rights to use, copy, modify, merge, publish, 33 distribute, sublicense, and/or sell copies of the Software, and to 34 permit persons to whom the Software is furnished to do so, subject to 35 the following conditions: 36 37 The above copyright notice and this permission notice (including the 38 next paragraph) shall be included in all copies or substantial 39 portions of the Software. 40 41 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 42 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 43 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 44 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 45 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 46 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 47 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 48 */ 49 50 51 enum vgt_event_type { 52 VS_DEALLOC = 0, 53 PS_DEALLOC = 1, 54 VS_DONE_TS = 2, 55 PS_DONE_TS = 3, 56 CACHE_FLUSH_TS = 4, 57 CONTEXT_DONE = 5, 58 CACHE_FLUSH = 6, 59 VIZQUERY_START = 7, 60 HLSQ_FLUSH = 7, 61 VIZQUERY_END = 8, 62 SC_WAIT_WC = 9, 63 WRITE_PRIMITIVE_COUNTS = 9, 64 START_PRIMITIVE_CTRS = 11, 65 STOP_PRIMITIVE_CTRS = 12, 66 RST_PIX_CNT = 13, 67 RST_VTX_CNT = 14, 68 TILE_FLUSH = 15, 69 STAT_EVENT = 16, 70 CACHE_FLUSH_AND_INV_TS_EVENT = 20, 71 ZPASS_DONE = 21, 72 CACHE_FLUSH_AND_INV_EVENT = 22, 73 RB_DONE_TS = 22, 74 PERFCOUNTER_START = 23, 75 PERFCOUNTER_STOP = 24, 76 VS_FETCH_DONE = 27, 77 FACENESS_FLUSH = 28, 78 WT_DONE_TS = 8, 79 FLUSH_SO_0 = 17, 80 FLUSH_SO_1 = 18, 81 FLUSH_SO_2 = 19, 82 FLUSH_SO_3 = 20, 83 PC_CCU_INVALIDATE_DEPTH = 24, 84 PC_CCU_INVALIDATE_COLOR = 25, 85 PC_CCU_RESOLVE_TS = 26, 86 PC_CCU_FLUSH_DEPTH_TS = 28, 87 PC_CCU_FLUSH_COLOR_TS = 29, 88 BLIT = 30, 89 UNK_25 = 37, 90 LRZ_FLUSH = 38, 91 BLIT_OP_FILL_2D = 39, 92 BLIT_OP_COPY_2D = 40, 93 BLIT_OP_SCALE_2D = 42, 94 CONTEXT_DONE_2D = 43, 95 UNK_2C = 44, 96 UNK_2D = 45, 97 CACHE_INVALIDATE = 49, 98 }; 99 100 enum pc_di_primtype { 101 DI_PT_NONE = 0, 102 DI_PT_POINTLIST_PSIZE = 1, 103 DI_PT_LINELIST = 2, 104 DI_PT_LINESTRIP = 3, 105 DI_PT_TRILIST = 4, 106 DI_PT_TRIFAN = 5, 107 DI_PT_TRISTRIP = 6, 108 DI_PT_LINELOOP = 7, 109 DI_PT_RECTLIST = 8, 110 DI_PT_POINTLIST = 9, 111 DI_PT_LINE_ADJ = 10, 112 DI_PT_LINESTRIP_ADJ = 11, 113 DI_PT_TRI_ADJ = 12, 114 DI_PT_TRISTRIP_ADJ = 13, 115 DI_PT_PATCHES0 = 31, 116 DI_PT_PATCHES1 = 32, 117 DI_PT_PATCHES2 = 33, 118 DI_PT_PATCHES3 = 34, 119 DI_PT_PATCHES4 = 35, 120 DI_PT_PATCHES5 = 36, 121 DI_PT_PATCHES6 = 37, 122 DI_PT_PATCHES7 = 38, 123 DI_PT_PATCHES8 = 39, 124 DI_PT_PATCHES9 = 40, 125 DI_PT_PATCHES10 = 41, 126 DI_PT_PATCHES11 = 42, 127 DI_PT_PATCHES12 = 43, 128 DI_PT_PATCHES13 = 44, 129 DI_PT_PATCHES14 = 45, 130 DI_PT_PATCHES15 = 46, 131 DI_PT_PATCHES16 = 47, 132 DI_PT_PATCHES17 = 48, 133 DI_PT_PATCHES18 = 49, 134 DI_PT_PATCHES19 = 50, 135 DI_PT_PATCHES20 = 51, 136 DI_PT_PATCHES21 = 52, 137 DI_PT_PATCHES22 = 53, 138 DI_PT_PATCHES23 = 54, 139 DI_PT_PATCHES24 = 55, 140 DI_PT_PATCHES25 = 56, 141 DI_PT_PATCHES26 = 57, 142 DI_PT_PATCHES27 = 58, 143 DI_PT_PATCHES28 = 59, 144 DI_PT_PATCHES29 = 60, 145 DI_PT_PATCHES30 = 61, 146 DI_PT_PATCHES31 = 62, 147 }; 148 149 enum pc_di_src_sel { 150 DI_SRC_SEL_DMA = 0, 151 DI_SRC_SEL_IMMEDIATE = 1, 152 DI_SRC_SEL_AUTO_INDEX = 2, 153 DI_SRC_SEL_AUTO_XFB = 3, 154 }; 155 156 enum pc_di_face_cull_sel { 157 DI_FACE_CULL_NONE = 0, 158 DI_FACE_CULL_FETCH = 1, 159 DI_FACE_BACKFACE_CULL = 2, 160 DI_FACE_FRONTFACE_CULL = 3, 161 }; 162 163 enum pc_di_index_size { 164 INDEX_SIZE_IGN = 0, 165 INDEX_SIZE_16_BIT = 0, 166 INDEX_SIZE_32_BIT = 1, 167 INDEX_SIZE_8_BIT = 2, 168 INDEX_SIZE_INVALID = 0, 169 }; 170 171 enum pc_di_vis_cull_mode { 172 IGNORE_VISIBILITY = 0, 173 USE_VISIBILITY = 1, 174 }; 175 176 enum adreno_pm4_packet_type { 177 CP_TYPE0_PKT = 0, 178 CP_TYPE1_PKT = 0x40000000, 179 CP_TYPE2_PKT = 0x80000000, 180 CP_TYPE3_PKT = 0xc0000000, 181 CP_TYPE4_PKT = 0x40000000, 182 CP_TYPE7_PKT = 0x70000000, 183 }; 184 185 enum adreno_pm4_type3_packets { 186 CP_ME_INIT = 72, 187 CP_NOP = 16, 188 CP_PREEMPT_ENABLE = 28, 189 CP_PREEMPT_TOKEN = 30, 190 CP_INDIRECT_BUFFER = 63, 191 CP_INDIRECT_BUFFER_CHAIN = 87, 192 CP_INDIRECT_BUFFER_PFD = 55, 193 CP_WAIT_FOR_IDLE = 38, 194 CP_WAIT_REG_MEM = 60, 195 CP_WAIT_REG_EQ = 82, 196 CP_WAIT_REG_GTE = 83, 197 CP_WAIT_UNTIL_READ = 92, 198 CP_WAIT_IB_PFD_COMPLETE = 93, 199 CP_REG_RMW = 33, 200 CP_SET_BIN_DATA = 47, 201 CP_SET_BIN_DATA5 = 47, 202 CP_REG_TO_MEM = 62, 203 CP_MEM_WRITE = 61, 204 CP_MEM_WRITE_CNTR = 79, 205 CP_COND_EXEC = 68, 206 CP_COND_WRITE = 69, 207 CP_COND_WRITE5 = 69, 208 CP_EVENT_WRITE = 70, 209 CP_EVENT_WRITE_SHD = 88, 210 CP_EVENT_WRITE_CFL = 89, 211 CP_EVENT_WRITE_ZPD = 91, 212 CP_RUN_OPENCL = 49, 213 CP_DRAW_INDX = 34, 214 CP_DRAW_INDX_2 = 54, 215 CP_DRAW_INDX_BIN = 52, 216 CP_DRAW_INDX_2_BIN = 53, 217 CP_VIZ_QUERY = 35, 218 CP_SET_STATE = 37, 219 CP_SET_CONSTANT = 45, 220 CP_IM_LOAD = 39, 221 CP_IM_LOAD_IMMEDIATE = 43, 222 CP_LOAD_CONSTANT_CONTEXT = 46, 223 CP_INVALIDATE_STATE = 59, 224 CP_SET_SHADER_BASES = 74, 225 CP_SET_BIN_MASK = 80, 226 CP_SET_BIN_SELECT = 81, 227 CP_CONTEXT_UPDATE = 94, 228 CP_INTERRUPT = 64, 229 CP_IM_STORE = 44, 230 CP_SET_DRAW_INIT_FLAGS = 75, 231 CP_SET_PROTECTED_MODE = 95, 232 CP_BOOTSTRAP_UCODE = 111, 233 CP_LOAD_STATE = 48, 234 CP_LOAD_STATE4 = 48, 235 CP_COND_INDIRECT_BUFFER_PFE = 58, 236 CP_COND_INDIRECT_BUFFER_PFD = 50, 237 CP_INDIRECT_BUFFER_PFE = 63, 238 CP_SET_BIN = 76, 239 CP_TEST_TWO_MEMS = 113, 240 CP_REG_WR_NO_CTXT = 120, 241 CP_RECORD_PFP_TIMESTAMP = 17, 242 CP_SET_SECURE_MODE = 102, 243 CP_WAIT_FOR_ME = 19, 244 CP_SET_DRAW_STATE = 67, 245 CP_DRAW_INDX_OFFSET = 56, 246 CP_DRAW_INDIRECT = 40, 247 CP_DRAW_INDX_INDIRECT = 41, 248 CP_DRAW_INDIRECT_MULTI = 42, 249 CP_DRAW_AUTO = 36, 250 CP_UNKNOWN_19 = 25, 251 CP_UNKNOWN_1A = 26, 252 CP_UNKNOWN_4E = 78, 253 CP_WIDE_REG_WRITE = 116, 254 CP_SCRATCH_TO_REG = 77, 255 CP_REG_TO_SCRATCH = 74, 256 CP_WAIT_MEM_WRITES = 18, 257 CP_COND_REG_EXEC = 71, 258 CP_MEM_TO_REG = 66, 259 CP_EXEC_CS_INDIRECT = 65, 260 CP_EXEC_CS = 51, 261 CP_PERFCOUNTER_ACTION = 80, 262 CP_SMMU_TABLE_UPDATE = 83, 263 CP_SET_MARKER = 101, 264 CP_SET_PSEUDO_REG = 86, 265 CP_CONTEXT_REG_BUNCH = 92, 266 CP_YIELD_ENABLE = 28, 267 CP_SKIP_IB2_ENABLE_GLOBAL = 29, 268 CP_SKIP_IB2_ENABLE_LOCAL = 35, 269 CP_SET_SUBDRAW_SIZE = 53, 270 CP_SET_VISIBILITY_OVERRIDE = 100, 271 CP_PREEMPT_ENABLE_GLOBAL = 105, 272 CP_PREEMPT_ENABLE_LOCAL = 106, 273 CP_CONTEXT_SWITCH_YIELD = 107, 274 CP_SET_RENDER_MODE = 108, 275 CP_COMPUTE_CHECKPOINT = 110, 276 CP_MEM_TO_MEM = 115, 277 CP_BLIT = 44, 278 CP_REG_TEST = 57, 279 CP_SET_MODE = 99, 280 CP_LOAD_STATE6_GEOM = 50, 281 CP_LOAD_STATE6_FRAG = 52, 282 CP_LOAD_STATE6 = 54, 283 IN_IB_PREFETCH_END = 23, 284 IN_SUBBLK_PREFETCH = 31, 285 IN_INSTR_PREFETCH = 32, 286 IN_INSTR_MATCH = 71, 287 IN_CONST_PREFETCH = 73, 288 IN_INCR_UPDT_STATE = 85, 289 IN_INCR_UPDT_CONST = 86, 290 IN_INCR_UPDT_INSTR = 87, 291 PKT4 = 4, 292 CP_SCRATCH_WRITE = 76, 293 CP_REG_TO_MEM_OFFSET_MEM = 116, 294 CP_REG_TO_MEM_OFFSET_REG = 114, 295 CP_WAIT_MEM_GTE = 20, 296 CP_WAIT_TWO_REGS = 112, 297 CP_MEMCPY = 117, 298 CP_SET_BIN_DATA5_OFFSET = 46, 299 CP_SET_CTXSWITCH_IB = 85, 300 CP_REG_WRITE = 109, 301 }; 302 303 enum adreno_state_block { 304 SB_VERT_TEX = 0, 305 SB_VERT_MIPADDR = 1, 306 SB_FRAG_TEX = 2, 307 SB_FRAG_MIPADDR = 3, 308 SB_VERT_SHADER = 4, 309 SB_GEOM_SHADER = 5, 310 SB_FRAG_SHADER = 6, 311 SB_COMPUTE_SHADER = 7, 312 }; 313 314 enum adreno_state_type { 315 ST_SHADER = 0, 316 ST_CONSTANTS = 1, 317 }; 318 319 enum adreno_state_src { 320 SS_DIRECT = 0, 321 SS_INVALID_ALL_IC = 2, 322 SS_INVALID_PART_IC = 3, 323 SS_INDIRECT = 4, 324 SS_INDIRECT_TCM = 5, 325 SS_INDIRECT_STM = 6, 326 }; 327 328 enum a4xx_state_block { 329 SB4_VS_TEX = 0, 330 SB4_HS_TEX = 1, 331 SB4_DS_TEX = 2, 332 SB4_GS_TEX = 3, 333 SB4_FS_TEX = 4, 334 SB4_CS_TEX = 5, 335 SB4_VS_SHADER = 8, 336 SB4_HS_SHADER = 9, 337 SB4_DS_SHADER = 10, 338 SB4_GS_SHADER = 11, 339 SB4_FS_SHADER = 12, 340 SB4_CS_SHADER = 13, 341 SB4_SSBO = 14, 342 SB4_CS_SSBO = 15, 343 }; 344 345 enum a4xx_state_type { 346 ST4_SHADER = 0, 347 ST4_CONSTANTS = 1, 348 ST4_UBO = 2, 349 }; 350 351 enum a4xx_state_src { 352 SS4_DIRECT = 0, 353 SS4_INDIRECT = 2, 354 }; 355 356 enum a6xx_state_block { 357 SB6_VS_TEX = 0, 358 SB6_HS_TEX = 1, 359 SB6_DS_TEX = 2, 360 SB6_GS_TEX = 3, 361 SB6_FS_TEX = 4, 362 SB6_CS_TEX = 5, 363 SB6_VS_SHADER = 8, 364 SB6_HS_SHADER = 9, 365 SB6_DS_SHADER = 10, 366 SB6_GS_SHADER = 11, 367 SB6_FS_SHADER = 12, 368 SB6_CS_SHADER = 13, 369 SB6_IBO = 14, 370 SB6_CS_IBO = 15, 371 }; 372 373 enum a6xx_state_type { 374 ST6_SHADER = 0, 375 ST6_CONSTANTS = 1, 376 ST6_UBO = 2, 377 ST6_IBO = 3, 378 }; 379 380 enum a6xx_state_src { 381 SS6_DIRECT = 0, 382 SS6_BINDLESS = 1, 383 SS6_INDIRECT = 2, 384 SS6_UBO = 3, 385 }; 386 387 enum a4xx_index_size { 388 INDEX4_SIZE_8_BIT = 0, 389 INDEX4_SIZE_16_BIT = 1, 390 INDEX4_SIZE_32_BIT = 2, 391 }; 392 393 enum a6xx_patch_type { 394 TESS_QUADS = 0, 395 TESS_TRIANGLES = 1, 396 TESS_ISOLINES = 2, 397 }; 398 399 enum a6xx_draw_indirect_opcode { 400 INDIRECT_OP_NORMAL = 2, 401 INDIRECT_OP_INDEXED = 4, 402 }; 403 404 enum cp_cond_function { 405 WRITE_ALWAYS = 0, 406 WRITE_LT = 1, 407 WRITE_LE = 2, 408 WRITE_EQ = 3, 409 WRITE_NE = 4, 410 WRITE_GE = 5, 411 WRITE_GT = 6, 412 }; 413 414 enum render_mode_cmd { 415 BYPASS = 1, 416 BINNING = 2, 417 GMEM = 3, 418 BLIT2D = 5, 419 BLIT2DSCALE = 7, 420 END2D = 8, 421 }; 422 423 enum cp_blit_cmd { 424 BLIT_OP_FILL = 0, 425 BLIT_OP_COPY = 1, 426 BLIT_OP_SCALE = 3, 427 }; 428 429 enum a6xx_render_mode { 430 RM6_BYPASS = 1, 431 RM6_BINNING = 2, 432 RM6_GMEM = 4, 433 RM6_ENDVIS = 5, 434 RM6_RESOLVE = 6, 435 RM6_YIELD = 7, 436 RM6_COMPUTE = 8, 437 RM6_BLIT2DSCALE = 12, 438 RM6_IB1LIST_START = 13, 439 RM6_IB1LIST_END = 14, 440 RM6_IFPC_ENABLE = 256, 441 RM6_IFPC_DISABLE = 257, 442 }; 443 444 enum pseudo_reg { 445 SMMU_INFO = 0, 446 NON_SECURE_SAVE_ADDR = 1, 447 SECURE_SAVE_ADDR = 2, 448 NON_PRIV_SAVE_ADDR = 3, 449 COUNTER = 4, 450 }; 451 452 enum compare_mode { 453 PRED_TEST = 1, 454 REG_COMPARE = 2, 455 RENDER_MODE = 3, 456 }; 457 458 enum ctxswitch_ib { 459 RESTORE_IB = 0, 460 YIELD_RESTORE_IB = 1, 461 SAVE_IB = 2, 462 RB_SAVE_IB = 3, 463 }; 464 465 enum reg_tracker { 466 TRACK_CNTL_REG = 1, 467 TRACK_RENDER_CNTL = 2, 468 UNK_EVENT_WRITE = 4, 469 }; 470 471 #define REG_CP_LOAD_STATE_0 0x00000000 472 #define CP_LOAD_STATE_0_DST_OFF__MASK 0x0000ffff 473 #define CP_LOAD_STATE_0_DST_OFF__SHIFT 0 474 static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val) 475 { 476 return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK; 477 } 478 #define CP_LOAD_STATE_0_STATE_SRC__MASK 0x00070000 479 #define CP_LOAD_STATE_0_STATE_SRC__SHIFT 16 480 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val) 481 { 482 return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK; 483 } 484 #define CP_LOAD_STATE_0_STATE_BLOCK__MASK 0x00380000 485 #define CP_LOAD_STATE_0_STATE_BLOCK__SHIFT 19 486 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val) 487 { 488 return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK; 489 } 490 #define CP_LOAD_STATE_0_NUM_UNIT__MASK 0xffc00000 491 #define CP_LOAD_STATE_0_NUM_UNIT__SHIFT 22 492 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val) 493 { 494 return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK; 495 } 496 497 #define REG_CP_LOAD_STATE_1 0x00000001 498 #define CP_LOAD_STATE_1_STATE_TYPE__MASK 0x00000003 499 #define CP_LOAD_STATE_1_STATE_TYPE__SHIFT 0 500 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val) 501 { 502 return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK; 503 } 504 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK 0xfffffffc 505 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT 2 506 static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val) 507 { 508 return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK; 509 } 510 511 #define REG_CP_LOAD_STATE4_0 0x00000000 512 #define CP_LOAD_STATE4_0_DST_OFF__MASK 0x00003fff 513 #define CP_LOAD_STATE4_0_DST_OFF__SHIFT 0 514 static inline uint32_t CP_LOAD_STATE4_0_DST_OFF(uint32_t val) 515 { 516 return ((val) << CP_LOAD_STATE4_0_DST_OFF__SHIFT) & CP_LOAD_STATE4_0_DST_OFF__MASK; 517 } 518 #define CP_LOAD_STATE4_0_STATE_SRC__MASK 0x00030000 519 #define CP_LOAD_STATE4_0_STATE_SRC__SHIFT 16 520 static inline uint32_t CP_LOAD_STATE4_0_STATE_SRC(enum a4xx_state_src val) 521 { 522 return ((val) << CP_LOAD_STATE4_0_STATE_SRC__SHIFT) & CP_LOAD_STATE4_0_STATE_SRC__MASK; 523 } 524 #define CP_LOAD_STATE4_0_STATE_BLOCK__MASK 0x003c0000 525 #define CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT 18 526 static inline uint32_t CP_LOAD_STATE4_0_STATE_BLOCK(enum a4xx_state_block val) 527 { 528 return ((val) << CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE4_0_STATE_BLOCK__MASK; 529 } 530 #define CP_LOAD_STATE4_0_NUM_UNIT__MASK 0xffc00000 531 #define CP_LOAD_STATE4_0_NUM_UNIT__SHIFT 22 532 static inline uint32_t CP_LOAD_STATE4_0_NUM_UNIT(uint32_t val) 533 { 534 return ((val) << CP_LOAD_STATE4_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE4_0_NUM_UNIT__MASK; 535 } 536 537 #define REG_CP_LOAD_STATE4_1 0x00000001 538 #define CP_LOAD_STATE4_1_STATE_TYPE__MASK 0x00000003 539 #define CP_LOAD_STATE4_1_STATE_TYPE__SHIFT 0 540 static inline uint32_t CP_LOAD_STATE4_1_STATE_TYPE(enum a4xx_state_type val) 541 { 542 return ((val) << CP_LOAD_STATE4_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE4_1_STATE_TYPE__MASK; 543 } 544 #define CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK 0xfffffffc 545 #define CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT 2 546 static inline uint32_t CP_LOAD_STATE4_1_EXT_SRC_ADDR(uint32_t val) 547 { 548 return ((val >> 2) << CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK; 549 } 550 551 #define REG_CP_LOAD_STATE4_2 0x00000002 552 #define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK 0xffffffff 553 #define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT 0 554 static inline uint32_t CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(uint32_t val) 555 { 556 return ((val) << CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK; 557 } 558 559 #define REG_CP_LOAD_STATE6_0 0x00000000 560 #define CP_LOAD_STATE6_0_DST_OFF__MASK 0x00003fff 561 #define CP_LOAD_STATE6_0_DST_OFF__SHIFT 0 562 static inline uint32_t CP_LOAD_STATE6_0_DST_OFF(uint32_t val) 563 { 564 return ((val) << CP_LOAD_STATE6_0_DST_OFF__SHIFT) & CP_LOAD_STATE6_0_DST_OFF__MASK; 565 } 566 #define CP_LOAD_STATE6_0_STATE_TYPE__MASK 0x0000c000 567 #define CP_LOAD_STATE6_0_STATE_TYPE__SHIFT 14 568 static inline uint32_t CP_LOAD_STATE6_0_STATE_TYPE(enum a6xx_state_type val) 569 { 570 return ((val) << CP_LOAD_STATE6_0_STATE_TYPE__SHIFT) & CP_LOAD_STATE6_0_STATE_TYPE__MASK; 571 } 572 #define CP_LOAD_STATE6_0_STATE_SRC__MASK 0x00030000 573 #define CP_LOAD_STATE6_0_STATE_SRC__SHIFT 16 574 static inline uint32_t CP_LOAD_STATE6_0_STATE_SRC(enum a6xx_state_src val) 575 { 576 return ((val) << CP_LOAD_STATE6_0_STATE_SRC__SHIFT) & CP_LOAD_STATE6_0_STATE_SRC__MASK; 577 } 578 #define CP_LOAD_STATE6_0_STATE_BLOCK__MASK 0x003c0000 579 #define CP_LOAD_STATE6_0_STATE_BLOCK__SHIFT 18 580 static inline uint32_t CP_LOAD_STATE6_0_STATE_BLOCK(enum a6xx_state_block val) 581 { 582 return ((val) << CP_LOAD_STATE6_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE6_0_STATE_BLOCK__MASK; 583 } 584 #define CP_LOAD_STATE6_0_NUM_UNIT__MASK 0xffc00000 585 #define CP_LOAD_STATE6_0_NUM_UNIT__SHIFT 22 586 static inline uint32_t CP_LOAD_STATE6_0_NUM_UNIT(uint32_t val) 587 { 588 return ((val) << CP_LOAD_STATE6_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE6_0_NUM_UNIT__MASK; 589 } 590 591 #define REG_CP_LOAD_STATE6_1 0x00000001 592 #define CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK 0xfffffffc 593 #define CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT 2 594 static inline uint32_t CP_LOAD_STATE6_1_EXT_SRC_ADDR(uint32_t val) 595 { 596 return ((val >> 2) << CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK; 597 } 598 599 #define REG_CP_LOAD_STATE6_2 0x00000002 600 #define CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK 0xffffffff 601 #define CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT 0 602 static inline uint32_t CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(uint32_t val) 603 { 604 return ((val) << CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK; 605 } 606 607 #define REG_CP_LOAD_STATE6_EXT_SRC_ADDR 0x00000001 608 609 #define REG_CP_DRAW_INDX_0 0x00000000 610 #define CP_DRAW_INDX_0_VIZ_QUERY__MASK 0xffffffff 611 #define CP_DRAW_INDX_0_VIZ_QUERY__SHIFT 0 612 static inline uint32_t CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val) 613 { 614 return ((val) << CP_DRAW_INDX_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_0_VIZ_QUERY__MASK; 615 } 616 617 #define REG_CP_DRAW_INDX_1 0x00000001 618 #define CP_DRAW_INDX_1_PRIM_TYPE__MASK 0x0000003f 619 #define CP_DRAW_INDX_1_PRIM_TYPE__SHIFT 0 620 static inline uint32_t CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val) 621 { 622 return ((val) << CP_DRAW_INDX_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_1_PRIM_TYPE__MASK; 623 } 624 #define CP_DRAW_INDX_1_SOURCE_SELECT__MASK 0x000000c0 625 #define CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT 6 626 static inline uint32_t CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val) 627 { 628 return ((val) << CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_1_SOURCE_SELECT__MASK; 629 } 630 #define CP_DRAW_INDX_1_VIS_CULL__MASK 0x00000600 631 #define CP_DRAW_INDX_1_VIS_CULL__SHIFT 9 632 static inline uint32_t CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val) 633 { 634 return ((val) << CP_DRAW_INDX_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_1_VIS_CULL__MASK; 635 } 636 #define CP_DRAW_INDX_1_INDEX_SIZE__MASK 0x00000800 637 #define CP_DRAW_INDX_1_INDEX_SIZE__SHIFT 11 638 static inline uint32_t CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val) 639 { 640 return ((val) << CP_DRAW_INDX_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_1_INDEX_SIZE__MASK; 641 } 642 #define CP_DRAW_INDX_1_NOT_EOP 0x00001000 643 #define CP_DRAW_INDX_1_SMALL_INDEX 0x00002000 644 #define CP_DRAW_INDX_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000 645 #define CP_DRAW_INDX_1_NUM_INSTANCES__MASK 0xff000000 646 #define CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT 24 647 static inline uint32_t CP_DRAW_INDX_1_NUM_INSTANCES(uint32_t val) 648 { 649 return ((val) << CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_1_NUM_INSTANCES__MASK; 650 } 651 652 #define REG_CP_DRAW_INDX_2 0x00000002 653 #define CP_DRAW_INDX_2_NUM_INDICES__MASK 0xffffffff 654 #define CP_DRAW_INDX_2_NUM_INDICES__SHIFT 0 655 static inline uint32_t CP_DRAW_INDX_2_NUM_INDICES(uint32_t val) 656 { 657 return ((val) << CP_DRAW_INDX_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_NUM_INDICES__MASK; 658 } 659 660 #define REG_CP_DRAW_INDX_3 0x00000003 661 #define CP_DRAW_INDX_3_INDX_BASE__MASK 0xffffffff 662 #define CP_DRAW_INDX_3_INDX_BASE__SHIFT 0 663 static inline uint32_t CP_DRAW_INDX_3_INDX_BASE(uint32_t val) 664 { 665 return ((val) << CP_DRAW_INDX_3_INDX_BASE__SHIFT) & CP_DRAW_INDX_3_INDX_BASE__MASK; 666 } 667 668 #define REG_CP_DRAW_INDX_4 0x00000004 669 #define CP_DRAW_INDX_4_INDX_SIZE__MASK 0xffffffff 670 #define CP_DRAW_INDX_4_INDX_SIZE__SHIFT 0 671 static inline uint32_t CP_DRAW_INDX_4_INDX_SIZE(uint32_t val) 672 { 673 return ((val) << CP_DRAW_INDX_4_INDX_SIZE__SHIFT) & CP_DRAW_INDX_4_INDX_SIZE__MASK; 674 } 675 676 #define REG_CP_DRAW_INDX_2_0 0x00000000 677 #define CP_DRAW_INDX_2_0_VIZ_QUERY__MASK 0xffffffff 678 #define CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT 0 679 static inline uint32_t CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val) 680 { 681 return ((val) << CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_2_0_VIZ_QUERY__MASK; 682 } 683 684 #define REG_CP_DRAW_INDX_2_1 0x00000001 685 #define CP_DRAW_INDX_2_1_PRIM_TYPE__MASK 0x0000003f 686 #define CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT 0 687 static inline uint32_t CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val) 688 { 689 return ((val) << CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_2_1_PRIM_TYPE__MASK; 690 } 691 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK 0x000000c0 692 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT 6 693 static inline uint32_t CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val) 694 { 695 return ((val) << CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK; 696 } 697 #define CP_DRAW_INDX_2_1_VIS_CULL__MASK 0x00000600 698 #define CP_DRAW_INDX_2_1_VIS_CULL__SHIFT 9 699 static inline uint32_t CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val) 700 { 701 return ((val) << CP_DRAW_INDX_2_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_2_1_VIS_CULL__MASK; 702 } 703 #define CP_DRAW_INDX_2_1_INDEX_SIZE__MASK 0x00000800 704 #define CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT 11 705 static inline uint32_t CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val) 706 { 707 return ((val) << CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_2_1_INDEX_SIZE__MASK; 708 } 709 #define CP_DRAW_INDX_2_1_NOT_EOP 0x00001000 710 #define CP_DRAW_INDX_2_1_SMALL_INDEX 0x00002000 711 #define CP_DRAW_INDX_2_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000 712 #define CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK 0xff000000 713 #define CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT 24 714 static inline uint32_t CP_DRAW_INDX_2_1_NUM_INSTANCES(uint32_t val) 715 { 716 return ((val) << CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK; 717 } 718 719 #define REG_CP_DRAW_INDX_2_2 0x00000002 720 #define CP_DRAW_INDX_2_2_NUM_INDICES__MASK 0xffffffff 721 #define CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT 0 722 static inline uint32_t CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val) 723 { 724 return ((val) << CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_2_NUM_INDICES__MASK; 725 } 726 727 #define REG_CP_DRAW_INDX_OFFSET_0 0x00000000 728 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK 0x0000003f 729 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT 0 730 static inline uint32_t CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val) 731 { 732 return ((val) << CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK; 733 } 734 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK 0x000000c0 735 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT 6 736 static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val) 737 { 738 return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK; 739 } 740 #define CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK 0x00000300 741 #define CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT 8 742 static inline uint32_t CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val) 743 { 744 return ((val) << CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT) & CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK; 745 } 746 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK 0x00000c00 747 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT 10 748 static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val) 749 { 750 return ((val) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK; 751 } 752 #define CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__MASK 0x00003000 753 #define CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__SHIFT 12 754 static inline uint32_t CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(enum a6xx_patch_type val) 755 { 756 return ((val) << CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__MASK; 757 } 758 #define CP_DRAW_INDX_OFFSET_0_GS_ENABLE 0x00010000 759 #define CP_DRAW_INDX_OFFSET_0_TESS_ENABLE 0x00020000 760 761 #define REG_CP_DRAW_INDX_OFFSET_1 0x00000001 762 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK 0xffffffff 763 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT 0 764 static inline uint32_t CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES(uint32_t val) 765 { 766 return ((val) << CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK; 767 } 768 769 #define REG_CP_DRAW_INDX_OFFSET_2 0x00000002 770 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK 0xffffffff 771 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT 0 772 static inline uint32_t CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val) 773 { 774 return ((val) << CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK; 775 } 776 777 #define REG_CP_DRAW_INDX_OFFSET_3 0x00000003 778 #define CP_DRAW_INDX_OFFSET_3_FIRST_INDX__MASK 0xffffffff 779 #define CP_DRAW_INDX_OFFSET_3_FIRST_INDX__SHIFT 0 780 static inline uint32_t CP_DRAW_INDX_OFFSET_3_FIRST_INDX(uint32_t val) 781 { 782 return ((val) << CP_DRAW_INDX_OFFSET_3_FIRST_INDX__SHIFT) & CP_DRAW_INDX_OFFSET_3_FIRST_INDX__MASK; 783 } 784 785 786 #define REG_CP_DRAW_INDX_OFFSET_4 0x00000004 787 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__MASK 0xffffffff 788 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__SHIFT 0 789 static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO(uint32_t val) 790 { 791 return ((val) << CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__MASK; 792 } 793 794 #define REG_CP_DRAW_INDX_OFFSET_5 0x00000005 795 #define CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__MASK 0xffffffff 796 #define CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__SHIFT 0 797 static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI(uint32_t val) 798 { 799 return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__MASK; 800 } 801 802 #define REG_CP_DRAW_INDX_OFFSET_INDX_BASE 0x00000004 803 804 #define REG_CP_DRAW_INDX_OFFSET_6 0x00000006 805 #define CP_DRAW_INDX_OFFSET_6_MAX_INDICES__MASK 0xffffffff 806 #define CP_DRAW_INDX_OFFSET_6_MAX_INDICES__SHIFT 0 807 static inline uint32_t CP_DRAW_INDX_OFFSET_6_MAX_INDICES(uint32_t val) 808 { 809 return ((val) << CP_DRAW_INDX_OFFSET_6_MAX_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_6_MAX_INDICES__MASK; 810 } 811 812 #define REG_CP_DRAW_INDX_OFFSET_4 0x00000004 813 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK 0xffffffff 814 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT 0 815 static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE(uint32_t val) 816 { 817 return ((val) << CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK; 818 } 819 820 #define REG_CP_DRAW_INDX_OFFSET_5 0x00000005 821 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK 0xffffffff 822 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT 0 823 static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_SIZE(uint32_t val) 824 { 825 return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK; 826 } 827 828 #define REG_A4XX_CP_DRAW_INDIRECT_0 0x00000000 829 #define A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK 0x0000003f 830 #define A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT 0 831 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val) 832 { 833 return ((val) << A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK; 834 } 835 #define A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK 0x000000c0 836 #define A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT 6 837 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val) 838 { 839 return ((val) << A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK; 840 } 841 #define A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK 0x00000300 842 #define A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT 8 843 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val) 844 { 845 return ((val) << A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK; 846 } 847 #define A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK 0x00000c00 848 #define A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT 10 849 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val) 850 { 851 return ((val) << A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK; 852 } 853 #define A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__MASK 0x00003000 854 #define A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__SHIFT 12 855 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE(enum a6xx_patch_type val) 856 { 857 return ((val) << A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__MASK; 858 } 859 #define A4XX_CP_DRAW_INDIRECT_0_GS_ENABLE 0x00010000 860 #define A4XX_CP_DRAW_INDIRECT_0_TESS_ENABLE 0x00020000 861 862 863 #define REG_A4XX_CP_DRAW_INDIRECT_1 0x00000001 864 #define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK 0xffffffff 865 #define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT 0 866 static inline uint32_t A4XX_CP_DRAW_INDIRECT_1_INDIRECT(uint32_t val) 867 { 868 return ((val) << A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK; 869 } 870 871 872 #define REG_A5XX_CP_DRAW_INDIRECT_1 0x00000001 873 #define A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__MASK 0xffffffff 874 #define A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__SHIFT 0 875 static inline uint32_t A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO(uint32_t val) 876 { 877 return ((val) << A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__SHIFT) & A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__MASK; 878 } 879 880 #define REG_A5XX_CP_DRAW_INDIRECT_2 0x00000002 881 #define A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK 0xffffffff 882 #define A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT 0 883 static inline uint32_t A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI(uint32_t val) 884 { 885 return ((val) << A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK; 886 } 887 888 #define REG_A5XX_CP_DRAW_INDIRECT_INDIRECT 0x00000001 889 890 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_0 0x00000000 891 #define A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK 0x0000003f 892 #define A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT 0 893 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val) 894 { 895 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK; 896 } 897 #define A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK 0x000000c0 898 #define A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT 6 899 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val) 900 { 901 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK; 902 } 903 #define A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK 0x00000300 904 #define A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT 8 905 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val) 906 { 907 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK; 908 } 909 #define A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK 0x00000c00 910 #define A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT 10 911 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val) 912 { 913 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK; 914 } 915 #define A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__MASK 0x00003000 916 #define A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__SHIFT 12 917 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE(enum a6xx_patch_type val) 918 { 919 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__MASK; 920 } 921 #define A4XX_CP_DRAW_INDX_INDIRECT_0_GS_ENABLE 0x00010000 922 #define A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_ENABLE 0x00020000 923 924 925 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_1 0x00000001 926 #define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK 0xffffffff 927 #define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT 0 928 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE(uint32_t val) 929 { 930 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK; 931 } 932 933 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_2 0x00000002 934 #define A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK 0xffffffff 935 #define A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT 0 936 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE(uint32_t val) 937 { 938 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK; 939 } 940 941 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_3 0x00000003 942 #define A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK 0xffffffff 943 #define A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT 0 944 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT(uint32_t val) 945 { 946 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK; 947 } 948 949 950 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_1 0x00000001 951 #define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK 0xffffffff 952 #define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT 0 953 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO(uint32_t val) 954 { 955 return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK; 956 } 957 958 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_2 0x00000002 959 #define A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK 0xffffffff 960 #define A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT 0 961 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI(uint32_t val) 962 { 963 return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK; 964 } 965 966 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_INDX_BASE 0x00000001 967 968 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_3 0x00000003 969 #define A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK 0xffffffff 970 #define A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT 0 971 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(uint32_t val) 972 { 973 return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK; 974 } 975 976 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_4 0x00000004 977 #define A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK 0xffffffff 978 #define A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT 0 979 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO(uint32_t val) 980 { 981 return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK; 982 } 983 984 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_5 0x00000005 985 #define A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK 0xffffffff 986 #define A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT 0 987 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI(uint32_t val) 988 { 989 return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK; 990 } 991 992 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_INDIRECT 0x00000004 993 994 #define REG_A6XX_CP_DRAW_INDIRECT_MULTI_0 0x00000000 995 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__MASK 0x0000003f 996 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__SHIFT 0 997 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE(enum pc_di_primtype val) 998 { 999 return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__MASK; 1000 } 1001 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__MASK 0x000000c0 1002 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__SHIFT 6 1003 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT(enum pc_di_src_sel val) 1004 { 1005 return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__MASK; 1006 } 1007 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__MASK 0x00000300 1008 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__SHIFT 8 1009 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL(enum pc_di_vis_cull_mode val) 1010 { 1011 return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__MASK; 1012 } 1013 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__MASK 0x00000c00 1014 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__SHIFT 10 1015 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE(enum a4xx_index_size val) 1016 { 1017 return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__MASK; 1018 } 1019 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__MASK 0x00003000 1020 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__SHIFT 12 1021 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE(enum a6xx_patch_type val) 1022 { 1023 return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__MASK; 1024 } 1025 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_GS_ENABLE 0x00010000 1026 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_TESS_ENABLE 0x00020000 1027 1028 #define REG_A6XX_CP_DRAW_INDIRECT_MULTI_1 0x00000001 1029 #define A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__MASK 0x0000000f 1030 #define A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__SHIFT 0 1031 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(enum a6xx_draw_indirect_opcode val) 1032 { 1033 return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__MASK; 1034 } 1035 #define A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__MASK 0x003fff00 1036 #define A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__SHIFT 8 1037 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(uint32_t val) 1038 { 1039 return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__MASK; 1040 } 1041 1042 #define REG_A6XX_CP_DRAW_INDIRECT_MULTI_2 0x00000002 1043 #define A6XX_CP_DRAW_INDIRECT_MULTI_2_DRAW_COUNT__MASK 0xffffffff 1044 #define A6XX_CP_DRAW_INDIRECT_MULTI_2_DRAW_COUNT__SHIFT 0 1045 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_2_DRAW_COUNT(uint32_t val) 1046 { 1047 return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_2_DRAW_COUNT__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_2_DRAW_COUNT__MASK; 1048 } 1049 1050 #define REG_A6XX_CP_DRAW_INDIRECT_MULTI_ADDRESS_0 0x00000003 1051 1052 #define REG_A6XX_CP_DRAW_INDIRECT_MULTI_5 0x00000005 1053 #define A6XX_CP_DRAW_INDIRECT_MULTI_5_PARAM_0__MASK 0xffffffff 1054 #define A6XX_CP_DRAW_INDIRECT_MULTI_5_PARAM_0__SHIFT 0 1055 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_5_PARAM_0(uint32_t val) 1056 { 1057 return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_5_PARAM_0__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_5_PARAM_0__MASK; 1058 } 1059 1060 #define REG_A6XX_CP_DRAW_INDIRECT_MULTI_INDIRECT 0x00000006 1061 1062 #define REG_A6XX_CP_DRAW_INDIRECT_MULTI_8 0x00000008 1063 #define A6XX_CP_DRAW_INDIRECT_MULTI_8_STRIDE__MASK 0xffffffff 1064 #define A6XX_CP_DRAW_INDIRECT_MULTI_8_STRIDE__SHIFT 0 1065 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_8_STRIDE(uint32_t val) 1066 { 1067 return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_8_STRIDE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_8_STRIDE__MASK; 1068 } 1069 1070 static inline uint32_t REG_CP_SET_DRAW_STATE_(uint32_t i0) { return 0x00000000 + 0x3*i0; } 1071 1072 static inline uint32_t REG_CP_SET_DRAW_STATE__0(uint32_t i0) { return 0x00000000 + 0x3*i0; } 1073 #define CP_SET_DRAW_STATE__0_COUNT__MASK 0x0000ffff 1074 #define CP_SET_DRAW_STATE__0_COUNT__SHIFT 0 1075 static inline uint32_t CP_SET_DRAW_STATE__0_COUNT(uint32_t val) 1076 { 1077 return ((val) << CP_SET_DRAW_STATE__0_COUNT__SHIFT) & CP_SET_DRAW_STATE__0_COUNT__MASK; 1078 } 1079 #define CP_SET_DRAW_STATE__0_DIRTY 0x00010000 1080 #define CP_SET_DRAW_STATE__0_DISABLE 0x00020000 1081 #define CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS 0x00040000 1082 #define CP_SET_DRAW_STATE__0_LOAD_IMMED 0x00080000 1083 #define CP_SET_DRAW_STATE__0_BINNING 0x00100000 1084 #define CP_SET_DRAW_STATE__0_GMEM 0x00200000 1085 #define CP_SET_DRAW_STATE__0_SYSMEM 0x00400000 1086 #define CP_SET_DRAW_STATE__0_GROUP_ID__MASK 0x1f000000 1087 #define CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT 24 1088 static inline uint32_t CP_SET_DRAW_STATE__0_GROUP_ID(uint32_t val) 1089 { 1090 return ((val) << CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT) & CP_SET_DRAW_STATE__0_GROUP_ID__MASK; 1091 } 1092 1093 static inline uint32_t REG_CP_SET_DRAW_STATE__1(uint32_t i0) { return 0x00000001 + 0x3*i0; } 1094 #define CP_SET_DRAW_STATE__1_ADDR_LO__MASK 0xffffffff 1095 #define CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT 0 1096 static inline uint32_t CP_SET_DRAW_STATE__1_ADDR_LO(uint32_t val) 1097 { 1098 return ((val) << CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT) & CP_SET_DRAW_STATE__1_ADDR_LO__MASK; 1099 } 1100 1101 static inline uint32_t REG_CP_SET_DRAW_STATE__2(uint32_t i0) { return 0x00000002 + 0x3*i0; } 1102 #define CP_SET_DRAW_STATE__2_ADDR_HI__MASK 0xffffffff 1103 #define CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT 0 1104 static inline uint32_t CP_SET_DRAW_STATE__2_ADDR_HI(uint32_t val) 1105 { 1106 return ((val) << CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT) & CP_SET_DRAW_STATE__2_ADDR_HI__MASK; 1107 } 1108 1109 #define REG_CP_SET_BIN_0 0x00000000 1110 1111 #define REG_CP_SET_BIN_1 0x00000001 1112 #define CP_SET_BIN_1_X1__MASK 0x0000ffff 1113 #define CP_SET_BIN_1_X1__SHIFT 0 1114 static inline uint32_t CP_SET_BIN_1_X1(uint32_t val) 1115 { 1116 return ((val) << CP_SET_BIN_1_X1__SHIFT) & CP_SET_BIN_1_X1__MASK; 1117 } 1118 #define CP_SET_BIN_1_Y1__MASK 0xffff0000 1119 #define CP_SET_BIN_1_Y1__SHIFT 16 1120 static inline uint32_t CP_SET_BIN_1_Y1(uint32_t val) 1121 { 1122 return ((val) << CP_SET_BIN_1_Y1__SHIFT) & CP_SET_BIN_1_Y1__MASK; 1123 } 1124 1125 #define REG_CP_SET_BIN_2 0x00000002 1126 #define CP_SET_BIN_2_X2__MASK 0x0000ffff 1127 #define CP_SET_BIN_2_X2__SHIFT 0 1128 static inline uint32_t CP_SET_BIN_2_X2(uint32_t val) 1129 { 1130 return ((val) << CP_SET_BIN_2_X2__SHIFT) & CP_SET_BIN_2_X2__MASK; 1131 } 1132 #define CP_SET_BIN_2_Y2__MASK 0xffff0000 1133 #define CP_SET_BIN_2_Y2__SHIFT 16 1134 static inline uint32_t CP_SET_BIN_2_Y2(uint32_t val) 1135 { 1136 return ((val) << CP_SET_BIN_2_Y2__SHIFT) & CP_SET_BIN_2_Y2__MASK; 1137 } 1138 1139 #define REG_CP_SET_BIN_DATA_0 0x00000000 1140 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK 0xffffffff 1141 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT 0 1142 static inline uint32_t CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val) 1143 { 1144 return ((val) << CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT) & CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK; 1145 } 1146 1147 #define REG_CP_SET_BIN_DATA_1 0x00000001 1148 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK 0xffffffff 1149 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT 0 1150 static inline uint32_t CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val) 1151 { 1152 return ((val) << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK; 1153 } 1154 1155 #define REG_CP_SET_BIN_DATA5_0 0x00000000 1156 #define CP_SET_BIN_DATA5_0_VSC_SIZE__MASK 0x003f0000 1157 #define CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT 16 1158 static inline uint32_t CP_SET_BIN_DATA5_0_VSC_SIZE(uint32_t val) 1159 { 1160 return ((val) << CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT) & CP_SET_BIN_DATA5_0_VSC_SIZE__MASK; 1161 } 1162 #define CP_SET_BIN_DATA5_0_VSC_N__MASK 0x07c00000 1163 #define CP_SET_BIN_DATA5_0_VSC_N__SHIFT 22 1164 static inline uint32_t CP_SET_BIN_DATA5_0_VSC_N(uint32_t val) 1165 { 1166 return ((val) << CP_SET_BIN_DATA5_0_VSC_N__SHIFT) & CP_SET_BIN_DATA5_0_VSC_N__MASK; 1167 } 1168 1169 #define REG_CP_SET_BIN_DATA5_1 0x00000001 1170 #define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK 0xffffffff 1171 #define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT 0 1172 static inline uint32_t CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO(uint32_t val) 1173 { 1174 return ((val) << CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT) & CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK; 1175 } 1176 1177 #define REG_CP_SET_BIN_DATA5_2 0x00000002 1178 #define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK 0xffffffff 1179 #define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT 0 1180 static inline uint32_t CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI(uint32_t val) 1181 { 1182 return ((val) << CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT) & CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK; 1183 } 1184 1185 #define REG_CP_SET_BIN_DATA5_3 0x00000003 1186 #define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK 0xffffffff 1187 #define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT 0 1188 static inline uint32_t CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO(uint32_t val) 1189 { 1190 return ((val) << CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT) & CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK; 1191 } 1192 1193 #define REG_CP_SET_BIN_DATA5_4 0x00000004 1194 #define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK 0xffffffff 1195 #define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT 0 1196 static inline uint32_t CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI(uint32_t val) 1197 { 1198 return ((val) << CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT) & CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK; 1199 } 1200 1201 #define REG_CP_SET_BIN_DATA5_5 0x00000005 1202 #define CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__MASK 0xffffffff 1203 #define CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__SHIFT 0 1204 static inline uint32_t CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO(uint32_t val) 1205 { 1206 return ((val) << CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__SHIFT) & CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__MASK; 1207 } 1208 1209 #define REG_CP_SET_BIN_DATA5_6 0x00000006 1210 #define CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__MASK 0xffffffff 1211 #define CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__SHIFT 0 1212 static inline uint32_t CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI(uint32_t val) 1213 { 1214 return ((val) << CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__SHIFT) & CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__MASK; 1215 } 1216 1217 #define REG_CP_SET_BIN_DATA5_OFFSET_0 0x00000000 1218 #define CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__MASK 0x003f0000 1219 #define CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__SHIFT 16 1220 static inline uint32_t CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE(uint32_t val) 1221 { 1222 return ((val) << CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__SHIFT) & CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__MASK; 1223 } 1224 #define CP_SET_BIN_DATA5_OFFSET_0_VSC_N__MASK 0x07c00000 1225 #define CP_SET_BIN_DATA5_OFFSET_0_VSC_N__SHIFT 22 1226 static inline uint32_t CP_SET_BIN_DATA5_OFFSET_0_VSC_N(uint32_t val) 1227 { 1228 return ((val) << CP_SET_BIN_DATA5_OFFSET_0_VSC_N__SHIFT) & CP_SET_BIN_DATA5_OFFSET_0_VSC_N__MASK; 1229 } 1230 1231 #define REG_CP_SET_BIN_DATA5_OFFSET_1 0x00000001 1232 #define CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__MASK 0xffffffff 1233 #define CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__SHIFT 0 1234 static inline uint32_t CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET(uint32_t val) 1235 { 1236 return ((val) << CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__SHIFT) & CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__MASK; 1237 } 1238 1239 #define REG_CP_SET_BIN_DATA5_OFFSET_2 0x00000002 1240 #define CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__MASK 0xffffffff 1241 #define CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__SHIFT 0 1242 static inline uint32_t CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET(uint32_t val) 1243 { 1244 return ((val) << CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__SHIFT) & CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__MASK; 1245 } 1246 1247 #define REG_CP_SET_BIN_DATA5_OFFSET_3 0x00000003 1248 #define CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__MASK 0xffffffff 1249 #define CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__SHIFT 0 1250 static inline uint32_t CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET(uint32_t val) 1251 { 1252 return ((val) << CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__SHIFT) & CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__MASK; 1253 } 1254 1255 #define REG_CP_REG_RMW_0 0x00000000 1256 #define CP_REG_RMW_0_DST_REG__MASK 0x0003ffff 1257 #define CP_REG_RMW_0_DST_REG__SHIFT 0 1258 static inline uint32_t CP_REG_RMW_0_DST_REG(uint32_t val) 1259 { 1260 return ((val) << CP_REG_RMW_0_DST_REG__SHIFT) & CP_REG_RMW_0_DST_REG__MASK; 1261 } 1262 #define CP_REG_RMW_0_ROTATE__MASK 0x1f000000 1263 #define CP_REG_RMW_0_ROTATE__SHIFT 24 1264 static inline uint32_t CP_REG_RMW_0_ROTATE(uint32_t val) 1265 { 1266 return ((val) << CP_REG_RMW_0_ROTATE__SHIFT) & CP_REG_RMW_0_ROTATE__MASK; 1267 } 1268 #define CP_REG_RMW_0_SRC1_ADD 0x20000000 1269 #define CP_REG_RMW_0_SRC1_IS_REG 0x40000000 1270 #define CP_REG_RMW_0_SRC0_IS_REG 0x80000000 1271 1272 #define REG_CP_REG_RMW_1 0x00000001 1273 #define CP_REG_RMW_1_SRC0__MASK 0xffffffff 1274 #define CP_REG_RMW_1_SRC0__SHIFT 0 1275 static inline uint32_t CP_REG_RMW_1_SRC0(uint32_t val) 1276 { 1277 return ((val) << CP_REG_RMW_1_SRC0__SHIFT) & CP_REG_RMW_1_SRC0__MASK; 1278 } 1279 1280 #define REG_CP_REG_RMW_2 0x00000002 1281 #define CP_REG_RMW_2_SRC1__MASK 0xffffffff 1282 #define CP_REG_RMW_2_SRC1__SHIFT 0 1283 static inline uint32_t CP_REG_RMW_2_SRC1(uint32_t val) 1284 { 1285 return ((val) << CP_REG_RMW_2_SRC1__SHIFT) & CP_REG_RMW_2_SRC1__MASK; 1286 } 1287 1288 #define REG_CP_REG_TO_MEM_0 0x00000000 1289 #define CP_REG_TO_MEM_0_REG__MASK 0x0003ffff 1290 #define CP_REG_TO_MEM_0_REG__SHIFT 0 1291 static inline uint32_t CP_REG_TO_MEM_0_REG(uint32_t val) 1292 { 1293 return ((val) << CP_REG_TO_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_0_REG__MASK; 1294 } 1295 #define CP_REG_TO_MEM_0_CNT__MASK 0x3ffc0000 1296 #define CP_REG_TO_MEM_0_CNT__SHIFT 18 1297 static inline uint32_t CP_REG_TO_MEM_0_CNT(uint32_t val) 1298 { 1299 return ((val) << CP_REG_TO_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_0_CNT__MASK; 1300 } 1301 #define CP_REG_TO_MEM_0_64B 0x40000000 1302 #define CP_REG_TO_MEM_0_ACCUMULATE 0x80000000 1303 1304 #define REG_CP_REG_TO_MEM_1 0x00000001 1305 #define CP_REG_TO_MEM_1_DEST__MASK 0xffffffff 1306 #define CP_REG_TO_MEM_1_DEST__SHIFT 0 1307 static inline uint32_t CP_REG_TO_MEM_1_DEST(uint32_t val) 1308 { 1309 return ((val) << CP_REG_TO_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_1_DEST__MASK; 1310 } 1311 1312 #define REG_CP_REG_TO_MEM_2 0x00000002 1313 #define CP_REG_TO_MEM_2_DEST_HI__MASK 0xffffffff 1314 #define CP_REG_TO_MEM_2_DEST_HI__SHIFT 0 1315 static inline uint32_t CP_REG_TO_MEM_2_DEST_HI(uint32_t val) 1316 { 1317 return ((val) << CP_REG_TO_MEM_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_2_DEST_HI__MASK; 1318 } 1319 1320 #define REG_CP_REG_TO_MEM_OFFSET_REG_0 0x00000000 1321 #define CP_REG_TO_MEM_OFFSET_REG_0_REG__MASK 0x0003ffff 1322 #define CP_REG_TO_MEM_OFFSET_REG_0_REG__SHIFT 0 1323 static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_0_REG(uint32_t val) 1324 { 1325 return ((val) << CP_REG_TO_MEM_OFFSET_REG_0_REG__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_0_REG__MASK; 1326 } 1327 #define CP_REG_TO_MEM_OFFSET_REG_0_CNT__MASK 0x3ffc0000 1328 #define CP_REG_TO_MEM_OFFSET_REG_0_CNT__SHIFT 18 1329 static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_0_CNT(uint32_t val) 1330 { 1331 return ((val) << CP_REG_TO_MEM_OFFSET_REG_0_CNT__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_0_CNT__MASK; 1332 } 1333 #define CP_REG_TO_MEM_OFFSET_REG_0_64B 0x40000000 1334 #define CP_REG_TO_MEM_OFFSET_REG_0_ACCUMULATE 0x80000000 1335 1336 #define REG_CP_REG_TO_MEM_OFFSET_REG_1 0x00000001 1337 #define CP_REG_TO_MEM_OFFSET_REG_1_DEST__MASK 0xffffffff 1338 #define CP_REG_TO_MEM_OFFSET_REG_1_DEST__SHIFT 0 1339 static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_1_DEST(uint32_t val) 1340 { 1341 return ((val) << CP_REG_TO_MEM_OFFSET_REG_1_DEST__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_1_DEST__MASK; 1342 } 1343 1344 #define REG_CP_REG_TO_MEM_OFFSET_REG_2 0x00000002 1345 #define CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__MASK 0xffffffff 1346 #define CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__SHIFT 0 1347 static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI(uint32_t val) 1348 { 1349 return ((val) << CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__MASK; 1350 } 1351 1352 #define REG_CP_REG_TO_MEM_OFFSET_REG_3 0x00000003 1353 #define CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__MASK 0x0003ffff 1354 #define CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__SHIFT 0 1355 static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0(uint32_t val) 1356 { 1357 return ((val) << CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__MASK; 1358 } 1359 #define CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0_SCRATCH 0x00080000 1360 1361 #define REG_CP_REG_TO_MEM_OFFSET_MEM_0 0x00000000 1362 #define CP_REG_TO_MEM_OFFSET_MEM_0_REG__MASK 0x0003ffff 1363 #define CP_REG_TO_MEM_OFFSET_MEM_0_REG__SHIFT 0 1364 static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_0_REG(uint32_t val) 1365 { 1366 return ((val) << CP_REG_TO_MEM_OFFSET_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_0_REG__MASK; 1367 } 1368 #define CP_REG_TO_MEM_OFFSET_MEM_0_CNT__MASK 0x3ffc0000 1369 #define CP_REG_TO_MEM_OFFSET_MEM_0_CNT__SHIFT 18 1370 static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_0_CNT(uint32_t val) 1371 { 1372 return ((val) << CP_REG_TO_MEM_OFFSET_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_0_CNT__MASK; 1373 } 1374 #define CP_REG_TO_MEM_OFFSET_MEM_0_64B 0x40000000 1375 #define CP_REG_TO_MEM_OFFSET_MEM_0_ACCUMULATE 0x80000000 1376 1377 #define REG_CP_REG_TO_MEM_OFFSET_MEM_1 0x00000001 1378 #define CP_REG_TO_MEM_OFFSET_MEM_1_DEST__MASK 0xffffffff 1379 #define CP_REG_TO_MEM_OFFSET_MEM_1_DEST__SHIFT 0 1380 static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_1_DEST(uint32_t val) 1381 { 1382 return ((val) << CP_REG_TO_MEM_OFFSET_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_1_DEST__MASK; 1383 } 1384 1385 #define REG_CP_REG_TO_MEM_OFFSET_MEM_2 0x00000002 1386 #define CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__MASK 0xffffffff 1387 #define CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__SHIFT 0 1388 static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI(uint32_t val) 1389 { 1390 return ((val) << CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__MASK; 1391 } 1392 1393 #define REG_CP_REG_TO_MEM_OFFSET_MEM_3 0x00000003 1394 #define CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__MASK 0xffffffff 1395 #define CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__SHIFT 0 1396 static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO(uint32_t val) 1397 { 1398 return ((val) << CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__MASK; 1399 } 1400 1401 #define REG_CP_REG_TO_MEM_OFFSET_MEM_4 0x00000004 1402 #define CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__MASK 0xffffffff 1403 #define CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__SHIFT 0 1404 static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI(uint32_t val) 1405 { 1406 return ((val) << CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__MASK; 1407 } 1408 1409 #define REG_CP_MEM_TO_REG_0 0x00000000 1410 #define CP_MEM_TO_REG_0_REG__MASK 0x0003ffff 1411 #define CP_MEM_TO_REG_0_REG__SHIFT 0 1412 static inline uint32_t CP_MEM_TO_REG_0_REG(uint32_t val) 1413 { 1414 return ((val) << CP_MEM_TO_REG_0_REG__SHIFT) & CP_MEM_TO_REG_0_REG__MASK; 1415 } 1416 #define CP_MEM_TO_REG_0_CNT__MASK 0x3ff80000 1417 #define CP_MEM_TO_REG_0_CNT__SHIFT 19 1418 static inline uint32_t CP_MEM_TO_REG_0_CNT(uint32_t val) 1419 { 1420 return ((val) << CP_MEM_TO_REG_0_CNT__SHIFT) & CP_MEM_TO_REG_0_CNT__MASK; 1421 } 1422 #define CP_MEM_TO_REG_0_SHIFT_BY_2 0x40000000 1423 #define CP_MEM_TO_REG_0_UNK31 0x80000000 1424 1425 #define REG_CP_MEM_TO_REG_1 0x00000001 1426 #define CP_MEM_TO_REG_1_SRC__MASK 0xffffffff 1427 #define CP_MEM_TO_REG_1_SRC__SHIFT 0 1428 static inline uint32_t CP_MEM_TO_REG_1_SRC(uint32_t val) 1429 { 1430 return ((val) << CP_MEM_TO_REG_1_SRC__SHIFT) & CP_MEM_TO_REG_1_SRC__MASK; 1431 } 1432 1433 #define REG_CP_MEM_TO_REG_2 0x00000002 1434 #define CP_MEM_TO_REG_2_SRC_HI__MASK 0xffffffff 1435 #define CP_MEM_TO_REG_2_SRC_HI__SHIFT 0 1436 static inline uint32_t CP_MEM_TO_REG_2_SRC_HI(uint32_t val) 1437 { 1438 return ((val) << CP_MEM_TO_REG_2_SRC_HI__SHIFT) & CP_MEM_TO_REG_2_SRC_HI__MASK; 1439 } 1440 1441 #define REG_CP_MEM_TO_MEM_0 0x00000000 1442 #define CP_MEM_TO_MEM_0_NEG_A 0x00000001 1443 #define CP_MEM_TO_MEM_0_NEG_B 0x00000002 1444 #define CP_MEM_TO_MEM_0_NEG_C 0x00000004 1445 #define CP_MEM_TO_MEM_0_DOUBLE 0x20000000 1446 #define CP_MEM_TO_MEM_0_WAIT_FOR_MEM_WRITES 0x40000000 1447 #define CP_MEM_TO_MEM_0_UNK31 0x80000000 1448 1449 #define REG_CP_MEMCPY_0 0x00000000 1450 #define CP_MEMCPY_0_DWORDS__MASK 0xffffffff 1451 #define CP_MEMCPY_0_DWORDS__SHIFT 0 1452 static inline uint32_t CP_MEMCPY_0_DWORDS(uint32_t val) 1453 { 1454 return ((val) << CP_MEMCPY_0_DWORDS__SHIFT) & CP_MEMCPY_0_DWORDS__MASK; 1455 } 1456 1457 #define REG_CP_MEMCPY_1 0x00000001 1458 #define CP_MEMCPY_1_SRC_LO__MASK 0xffffffff 1459 #define CP_MEMCPY_1_SRC_LO__SHIFT 0 1460 static inline uint32_t CP_MEMCPY_1_SRC_LO(uint32_t val) 1461 { 1462 return ((val) << CP_MEMCPY_1_SRC_LO__SHIFT) & CP_MEMCPY_1_SRC_LO__MASK; 1463 } 1464 1465 #define REG_CP_MEMCPY_2 0x00000002 1466 #define CP_MEMCPY_2_SRC_HI__MASK 0xffffffff 1467 #define CP_MEMCPY_2_SRC_HI__SHIFT 0 1468 static inline uint32_t CP_MEMCPY_2_SRC_HI(uint32_t val) 1469 { 1470 return ((val) << CP_MEMCPY_2_SRC_HI__SHIFT) & CP_MEMCPY_2_SRC_HI__MASK; 1471 } 1472 1473 #define REG_CP_MEMCPY_3 0x00000003 1474 #define CP_MEMCPY_3_DST_LO__MASK 0xffffffff 1475 #define CP_MEMCPY_3_DST_LO__SHIFT 0 1476 static inline uint32_t CP_MEMCPY_3_DST_LO(uint32_t val) 1477 { 1478 return ((val) << CP_MEMCPY_3_DST_LO__SHIFT) & CP_MEMCPY_3_DST_LO__MASK; 1479 } 1480 1481 #define REG_CP_MEMCPY_4 0x00000004 1482 #define CP_MEMCPY_4_DST_HI__MASK 0xffffffff 1483 #define CP_MEMCPY_4_DST_HI__SHIFT 0 1484 static inline uint32_t CP_MEMCPY_4_DST_HI(uint32_t val) 1485 { 1486 return ((val) << CP_MEMCPY_4_DST_HI__SHIFT) & CP_MEMCPY_4_DST_HI__MASK; 1487 } 1488 1489 #define REG_CP_REG_TO_SCRATCH_0 0x00000000 1490 #define CP_REG_TO_SCRATCH_0_REG__MASK 0x0003ffff 1491 #define CP_REG_TO_SCRATCH_0_REG__SHIFT 0 1492 static inline uint32_t CP_REG_TO_SCRATCH_0_REG(uint32_t val) 1493 { 1494 return ((val) << CP_REG_TO_SCRATCH_0_REG__SHIFT) & CP_REG_TO_SCRATCH_0_REG__MASK; 1495 } 1496 #define CP_REG_TO_SCRATCH_0_SCRATCH__MASK 0x00700000 1497 #define CP_REG_TO_SCRATCH_0_SCRATCH__SHIFT 20 1498 static inline uint32_t CP_REG_TO_SCRATCH_0_SCRATCH(uint32_t val) 1499 { 1500 return ((val) << CP_REG_TO_SCRATCH_0_SCRATCH__SHIFT) & CP_REG_TO_SCRATCH_0_SCRATCH__MASK; 1501 } 1502 #define CP_REG_TO_SCRATCH_0_CNT__MASK 0x07000000 1503 #define CP_REG_TO_SCRATCH_0_CNT__SHIFT 24 1504 static inline uint32_t CP_REG_TO_SCRATCH_0_CNT(uint32_t val) 1505 { 1506 return ((val) << CP_REG_TO_SCRATCH_0_CNT__SHIFT) & CP_REG_TO_SCRATCH_0_CNT__MASK; 1507 } 1508 1509 #define REG_CP_SCRATCH_TO_REG_0 0x00000000 1510 #define CP_SCRATCH_TO_REG_0_REG__MASK 0x0003ffff 1511 #define CP_SCRATCH_TO_REG_0_REG__SHIFT 0 1512 static inline uint32_t CP_SCRATCH_TO_REG_0_REG(uint32_t val) 1513 { 1514 return ((val) << CP_SCRATCH_TO_REG_0_REG__SHIFT) & CP_SCRATCH_TO_REG_0_REG__MASK; 1515 } 1516 #define CP_SCRATCH_TO_REG_0_UNK18 0x00040000 1517 #define CP_SCRATCH_TO_REG_0_SCRATCH__MASK 0x00700000 1518 #define CP_SCRATCH_TO_REG_0_SCRATCH__SHIFT 20 1519 static inline uint32_t CP_SCRATCH_TO_REG_0_SCRATCH(uint32_t val) 1520 { 1521 return ((val) << CP_SCRATCH_TO_REG_0_SCRATCH__SHIFT) & CP_SCRATCH_TO_REG_0_SCRATCH__MASK; 1522 } 1523 #define CP_SCRATCH_TO_REG_0_CNT__MASK 0x07000000 1524 #define CP_SCRATCH_TO_REG_0_CNT__SHIFT 24 1525 static inline uint32_t CP_SCRATCH_TO_REG_0_CNT(uint32_t val) 1526 { 1527 return ((val) << CP_SCRATCH_TO_REG_0_CNT__SHIFT) & CP_SCRATCH_TO_REG_0_CNT__MASK; 1528 } 1529 1530 #define REG_CP_SCRATCH_WRITE_0 0x00000000 1531 #define CP_SCRATCH_WRITE_0_SCRATCH__MASK 0x00700000 1532 #define CP_SCRATCH_WRITE_0_SCRATCH__SHIFT 20 1533 static inline uint32_t CP_SCRATCH_WRITE_0_SCRATCH(uint32_t val) 1534 { 1535 return ((val) << CP_SCRATCH_WRITE_0_SCRATCH__SHIFT) & CP_SCRATCH_WRITE_0_SCRATCH__MASK; 1536 } 1537 1538 #define REG_CP_MEM_WRITE_0 0x00000000 1539 #define CP_MEM_WRITE_0_ADDR_LO__MASK 0xffffffff 1540 #define CP_MEM_WRITE_0_ADDR_LO__SHIFT 0 1541 static inline uint32_t CP_MEM_WRITE_0_ADDR_LO(uint32_t val) 1542 { 1543 return ((val) << CP_MEM_WRITE_0_ADDR_LO__SHIFT) & CP_MEM_WRITE_0_ADDR_LO__MASK; 1544 } 1545 1546 #define REG_CP_MEM_WRITE_1 0x00000001 1547 #define CP_MEM_WRITE_1_ADDR_HI__MASK 0xffffffff 1548 #define CP_MEM_WRITE_1_ADDR_HI__SHIFT 0 1549 static inline uint32_t CP_MEM_WRITE_1_ADDR_HI(uint32_t val) 1550 { 1551 return ((val) << CP_MEM_WRITE_1_ADDR_HI__SHIFT) & CP_MEM_WRITE_1_ADDR_HI__MASK; 1552 } 1553 1554 #define REG_CP_COND_WRITE_0 0x00000000 1555 #define CP_COND_WRITE_0_FUNCTION__MASK 0x00000007 1556 #define CP_COND_WRITE_0_FUNCTION__SHIFT 0 1557 static inline uint32_t CP_COND_WRITE_0_FUNCTION(enum cp_cond_function val) 1558 { 1559 return ((val) << CP_COND_WRITE_0_FUNCTION__SHIFT) & CP_COND_WRITE_0_FUNCTION__MASK; 1560 } 1561 #define CP_COND_WRITE_0_POLL_MEMORY 0x00000010 1562 #define CP_COND_WRITE_0_WRITE_MEMORY 0x00000100 1563 1564 #define REG_CP_COND_WRITE_1 0x00000001 1565 #define CP_COND_WRITE_1_POLL_ADDR__MASK 0xffffffff 1566 #define CP_COND_WRITE_1_POLL_ADDR__SHIFT 0 1567 static inline uint32_t CP_COND_WRITE_1_POLL_ADDR(uint32_t val) 1568 { 1569 return ((val) << CP_COND_WRITE_1_POLL_ADDR__SHIFT) & CP_COND_WRITE_1_POLL_ADDR__MASK; 1570 } 1571 1572 #define REG_CP_COND_WRITE_2 0x00000002 1573 #define CP_COND_WRITE_2_REF__MASK 0xffffffff 1574 #define CP_COND_WRITE_2_REF__SHIFT 0 1575 static inline uint32_t CP_COND_WRITE_2_REF(uint32_t val) 1576 { 1577 return ((val) << CP_COND_WRITE_2_REF__SHIFT) & CP_COND_WRITE_2_REF__MASK; 1578 } 1579 1580 #define REG_CP_COND_WRITE_3 0x00000003 1581 #define CP_COND_WRITE_3_MASK__MASK 0xffffffff 1582 #define CP_COND_WRITE_3_MASK__SHIFT 0 1583 static inline uint32_t CP_COND_WRITE_3_MASK(uint32_t val) 1584 { 1585 return ((val) << CP_COND_WRITE_3_MASK__SHIFT) & CP_COND_WRITE_3_MASK__MASK; 1586 } 1587 1588 #define REG_CP_COND_WRITE_4 0x00000004 1589 #define CP_COND_WRITE_4_WRITE_ADDR__MASK 0xffffffff 1590 #define CP_COND_WRITE_4_WRITE_ADDR__SHIFT 0 1591 static inline uint32_t CP_COND_WRITE_4_WRITE_ADDR(uint32_t val) 1592 { 1593 return ((val) << CP_COND_WRITE_4_WRITE_ADDR__SHIFT) & CP_COND_WRITE_4_WRITE_ADDR__MASK; 1594 } 1595 1596 #define REG_CP_COND_WRITE_5 0x00000005 1597 #define CP_COND_WRITE_5_WRITE_DATA__MASK 0xffffffff 1598 #define CP_COND_WRITE_5_WRITE_DATA__SHIFT 0 1599 static inline uint32_t CP_COND_WRITE_5_WRITE_DATA(uint32_t val) 1600 { 1601 return ((val) << CP_COND_WRITE_5_WRITE_DATA__SHIFT) & CP_COND_WRITE_5_WRITE_DATA__MASK; 1602 } 1603 1604 #define REG_CP_COND_WRITE5_0 0x00000000 1605 #define CP_COND_WRITE5_0_FUNCTION__MASK 0x00000007 1606 #define CP_COND_WRITE5_0_FUNCTION__SHIFT 0 1607 static inline uint32_t CP_COND_WRITE5_0_FUNCTION(enum cp_cond_function val) 1608 { 1609 return ((val) << CP_COND_WRITE5_0_FUNCTION__SHIFT) & CP_COND_WRITE5_0_FUNCTION__MASK; 1610 } 1611 #define CP_COND_WRITE5_0_SIGNED_COMPARE 0x00000008 1612 #define CP_COND_WRITE5_0_POLL_MEMORY 0x00000010 1613 #define CP_COND_WRITE5_0_POLL_SCRATCH 0x00000020 1614 #define CP_COND_WRITE5_0_WRITE_MEMORY 0x00000100 1615 1616 #define REG_CP_COND_WRITE5_1 0x00000001 1617 #define CP_COND_WRITE5_1_POLL_ADDR_LO__MASK 0xffffffff 1618 #define CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT 0 1619 static inline uint32_t CP_COND_WRITE5_1_POLL_ADDR_LO(uint32_t val) 1620 { 1621 return ((val) << CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT) & CP_COND_WRITE5_1_POLL_ADDR_LO__MASK; 1622 } 1623 1624 #define REG_CP_COND_WRITE5_2 0x00000002 1625 #define CP_COND_WRITE5_2_POLL_ADDR_HI__MASK 0xffffffff 1626 #define CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT 0 1627 static inline uint32_t CP_COND_WRITE5_2_POLL_ADDR_HI(uint32_t val) 1628 { 1629 return ((val) << CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT) & CP_COND_WRITE5_2_POLL_ADDR_HI__MASK; 1630 } 1631 1632 #define REG_CP_COND_WRITE5_3 0x00000003 1633 #define CP_COND_WRITE5_3_REF__MASK 0xffffffff 1634 #define CP_COND_WRITE5_3_REF__SHIFT 0 1635 static inline uint32_t CP_COND_WRITE5_3_REF(uint32_t val) 1636 { 1637 return ((val) << CP_COND_WRITE5_3_REF__SHIFT) & CP_COND_WRITE5_3_REF__MASK; 1638 } 1639 1640 #define REG_CP_COND_WRITE5_4 0x00000004 1641 #define CP_COND_WRITE5_4_MASK__MASK 0xffffffff 1642 #define CP_COND_WRITE5_4_MASK__SHIFT 0 1643 static inline uint32_t CP_COND_WRITE5_4_MASK(uint32_t val) 1644 { 1645 return ((val) << CP_COND_WRITE5_4_MASK__SHIFT) & CP_COND_WRITE5_4_MASK__MASK; 1646 } 1647 1648 #define REG_CP_COND_WRITE5_5 0x00000005 1649 #define CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK 0xffffffff 1650 #define CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT 0 1651 static inline uint32_t CP_COND_WRITE5_5_WRITE_ADDR_LO(uint32_t val) 1652 { 1653 return ((val) << CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT) & CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK; 1654 } 1655 1656 #define REG_CP_COND_WRITE5_6 0x00000006 1657 #define CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK 0xffffffff 1658 #define CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT 0 1659 static inline uint32_t CP_COND_WRITE5_6_WRITE_ADDR_HI(uint32_t val) 1660 { 1661 return ((val) << CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT) & CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK; 1662 } 1663 1664 #define REG_CP_COND_WRITE5_7 0x00000007 1665 #define CP_COND_WRITE5_7_WRITE_DATA__MASK 0xffffffff 1666 #define CP_COND_WRITE5_7_WRITE_DATA__SHIFT 0 1667 static inline uint32_t CP_COND_WRITE5_7_WRITE_DATA(uint32_t val) 1668 { 1669 return ((val) << CP_COND_WRITE5_7_WRITE_DATA__SHIFT) & CP_COND_WRITE5_7_WRITE_DATA__MASK; 1670 } 1671 1672 #define REG_CP_WAIT_MEM_GTE_0 0x00000000 1673 #define CP_WAIT_MEM_GTE_0_RESERVED__MASK 0xffffffff 1674 #define CP_WAIT_MEM_GTE_0_RESERVED__SHIFT 0 1675 static inline uint32_t CP_WAIT_MEM_GTE_0_RESERVED(uint32_t val) 1676 { 1677 return ((val) << CP_WAIT_MEM_GTE_0_RESERVED__SHIFT) & CP_WAIT_MEM_GTE_0_RESERVED__MASK; 1678 } 1679 1680 #define REG_CP_WAIT_MEM_GTE_1 0x00000001 1681 #define CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__MASK 0xffffffff 1682 #define CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__SHIFT 0 1683 static inline uint32_t CP_WAIT_MEM_GTE_1_POLL_ADDR_LO(uint32_t val) 1684 { 1685 return ((val) << CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__SHIFT) & CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__MASK; 1686 } 1687 1688 #define REG_CP_WAIT_MEM_GTE_2 0x00000002 1689 #define CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__MASK 0xffffffff 1690 #define CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__SHIFT 0 1691 static inline uint32_t CP_WAIT_MEM_GTE_2_POLL_ADDR_HI(uint32_t val) 1692 { 1693 return ((val) << CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__SHIFT) & CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__MASK; 1694 } 1695 1696 #define REG_CP_WAIT_MEM_GTE_3 0x00000003 1697 #define CP_WAIT_MEM_GTE_3_REF__MASK 0xffffffff 1698 #define CP_WAIT_MEM_GTE_3_REF__SHIFT 0 1699 static inline uint32_t CP_WAIT_MEM_GTE_3_REF(uint32_t val) 1700 { 1701 return ((val) << CP_WAIT_MEM_GTE_3_REF__SHIFT) & CP_WAIT_MEM_GTE_3_REF__MASK; 1702 } 1703 1704 #define REG_CP_WAIT_REG_MEM_0 0x00000000 1705 #define CP_WAIT_REG_MEM_0_FUNCTION__MASK 0x00000007 1706 #define CP_WAIT_REG_MEM_0_FUNCTION__SHIFT 0 1707 static inline uint32_t CP_WAIT_REG_MEM_0_FUNCTION(enum cp_cond_function val) 1708 { 1709 return ((val) << CP_WAIT_REG_MEM_0_FUNCTION__SHIFT) & CP_WAIT_REG_MEM_0_FUNCTION__MASK; 1710 } 1711 #define CP_WAIT_REG_MEM_0_SIGNED_COMPARE 0x00000008 1712 #define CP_WAIT_REG_MEM_0_POLL_MEMORY 0x00000010 1713 #define CP_WAIT_REG_MEM_0_POLL_SCRATCH 0x00000020 1714 #define CP_WAIT_REG_MEM_0_WRITE_MEMORY 0x00000100 1715 1716 #define REG_CP_WAIT_REG_MEM_1 0x00000001 1717 #define CP_WAIT_REG_MEM_1_POLL_ADDR_LO__MASK 0xffffffff 1718 #define CP_WAIT_REG_MEM_1_POLL_ADDR_LO__SHIFT 0 1719 static inline uint32_t CP_WAIT_REG_MEM_1_POLL_ADDR_LO(uint32_t val) 1720 { 1721 return ((val) << CP_WAIT_REG_MEM_1_POLL_ADDR_LO__SHIFT) & CP_WAIT_REG_MEM_1_POLL_ADDR_LO__MASK; 1722 } 1723 1724 #define REG_CP_WAIT_REG_MEM_2 0x00000002 1725 #define CP_WAIT_REG_MEM_2_POLL_ADDR_HI__MASK 0xffffffff 1726 #define CP_WAIT_REG_MEM_2_POLL_ADDR_HI__SHIFT 0 1727 static inline uint32_t CP_WAIT_REG_MEM_2_POLL_ADDR_HI(uint32_t val) 1728 { 1729 return ((val) << CP_WAIT_REG_MEM_2_POLL_ADDR_HI__SHIFT) & CP_WAIT_REG_MEM_2_POLL_ADDR_HI__MASK; 1730 } 1731 1732 #define REG_CP_WAIT_REG_MEM_3 0x00000003 1733 #define CP_WAIT_REG_MEM_3_REF__MASK 0xffffffff 1734 #define CP_WAIT_REG_MEM_3_REF__SHIFT 0 1735 static inline uint32_t CP_WAIT_REG_MEM_3_REF(uint32_t val) 1736 { 1737 return ((val) << CP_WAIT_REG_MEM_3_REF__SHIFT) & CP_WAIT_REG_MEM_3_REF__MASK; 1738 } 1739 1740 #define REG_CP_WAIT_REG_MEM_4 0x00000004 1741 #define CP_WAIT_REG_MEM_4_MASK__MASK 0xffffffff 1742 #define CP_WAIT_REG_MEM_4_MASK__SHIFT 0 1743 static inline uint32_t CP_WAIT_REG_MEM_4_MASK(uint32_t val) 1744 { 1745 return ((val) << CP_WAIT_REG_MEM_4_MASK__SHIFT) & CP_WAIT_REG_MEM_4_MASK__MASK; 1746 } 1747 1748 #define REG_CP_WAIT_REG_MEM_5 0x00000005 1749 #define CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__MASK 0xffffffff 1750 #define CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__SHIFT 0 1751 static inline uint32_t CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(uint32_t val) 1752 { 1753 return ((val) << CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__SHIFT) & CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__MASK; 1754 } 1755 1756 #define REG_CP_WAIT_TWO_REGS_0 0x00000000 1757 #define CP_WAIT_TWO_REGS_0_REG0__MASK 0x0003ffff 1758 #define CP_WAIT_TWO_REGS_0_REG0__SHIFT 0 1759 static inline uint32_t CP_WAIT_TWO_REGS_0_REG0(uint32_t val) 1760 { 1761 return ((val) << CP_WAIT_TWO_REGS_0_REG0__SHIFT) & CP_WAIT_TWO_REGS_0_REG0__MASK; 1762 } 1763 1764 #define REG_CP_WAIT_TWO_REGS_1 0x00000001 1765 #define CP_WAIT_TWO_REGS_1_REG1__MASK 0x0003ffff 1766 #define CP_WAIT_TWO_REGS_1_REG1__SHIFT 0 1767 static inline uint32_t CP_WAIT_TWO_REGS_1_REG1(uint32_t val) 1768 { 1769 return ((val) << CP_WAIT_TWO_REGS_1_REG1__SHIFT) & CP_WAIT_TWO_REGS_1_REG1__MASK; 1770 } 1771 1772 #define REG_CP_WAIT_TWO_REGS_2 0x00000002 1773 #define CP_WAIT_TWO_REGS_2_REF__MASK 0xffffffff 1774 #define CP_WAIT_TWO_REGS_2_REF__SHIFT 0 1775 static inline uint32_t CP_WAIT_TWO_REGS_2_REF(uint32_t val) 1776 { 1777 return ((val) << CP_WAIT_TWO_REGS_2_REF__SHIFT) & CP_WAIT_TWO_REGS_2_REF__MASK; 1778 } 1779 1780 #define REG_CP_DISPATCH_COMPUTE_0 0x00000000 1781 1782 #define REG_CP_DISPATCH_COMPUTE_1 0x00000001 1783 #define CP_DISPATCH_COMPUTE_1_X__MASK 0xffffffff 1784 #define CP_DISPATCH_COMPUTE_1_X__SHIFT 0 1785 static inline uint32_t CP_DISPATCH_COMPUTE_1_X(uint32_t val) 1786 { 1787 return ((val) << CP_DISPATCH_COMPUTE_1_X__SHIFT) & CP_DISPATCH_COMPUTE_1_X__MASK; 1788 } 1789 1790 #define REG_CP_DISPATCH_COMPUTE_2 0x00000002 1791 #define CP_DISPATCH_COMPUTE_2_Y__MASK 0xffffffff 1792 #define CP_DISPATCH_COMPUTE_2_Y__SHIFT 0 1793 static inline uint32_t CP_DISPATCH_COMPUTE_2_Y(uint32_t val) 1794 { 1795 return ((val) << CP_DISPATCH_COMPUTE_2_Y__SHIFT) & CP_DISPATCH_COMPUTE_2_Y__MASK; 1796 } 1797 1798 #define REG_CP_DISPATCH_COMPUTE_3 0x00000003 1799 #define CP_DISPATCH_COMPUTE_3_Z__MASK 0xffffffff 1800 #define CP_DISPATCH_COMPUTE_3_Z__SHIFT 0 1801 static inline uint32_t CP_DISPATCH_COMPUTE_3_Z(uint32_t val) 1802 { 1803 return ((val) << CP_DISPATCH_COMPUTE_3_Z__SHIFT) & CP_DISPATCH_COMPUTE_3_Z__MASK; 1804 } 1805 1806 #define REG_CP_SET_RENDER_MODE_0 0x00000000 1807 #define CP_SET_RENDER_MODE_0_MODE__MASK 0x000001ff 1808 #define CP_SET_RENDER_MODE_0_MODE__SHIFT 0 1809 static inline uint32_t CP_SET_RENDER_MODE_0_MODE(enum render_mode_cmd val) 1810 { 1811 return ((val) << CP_SET_RENDER_MODE_0_MODE__SHIFT) & CP_SET_RENDER_MODE_0_MODE__MASK; 1812 } 1813 1814 #define REG_CP_SET_RENDER_MODE_1 0x00000001 1815 #define CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK 0xffffffff 1816 #define CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT 0 1817 static inline uint32_t CP_SET_RENDER_MODE_1_ADDR_0_LO(uint32_t val) 1818 { 1819 return ((val) << CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT) & CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK; 1820 } 1821 1822 #define REG_CP_SET_RENDER_MODE_2 0x00000002 1823 #define CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK 0xffffffff 1824 #define CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT 0 1825 static inline uint32_t CP_SET_RENDER_MODE_2_ADDR_0_HI(uint32_t val) 1826 { 1827 return ((val) << CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT) & CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK; 1828 } 1829 1830 #define REG_CP_SET_RENDER_MODE_3 0x00000003 1831 #define CP_SET_RENDER_MODE_3_VSC_ENABLE 0x00000008 1832 #define CP_SET_RENDER_MODE_3_GMEM_ENABLE 0x00000010 1833 1834 #define REG_CP_SET_RENDER_MODE_4 0x00000004 1835 1836 #define REG_CP_SET_RENDER_MODE_5 0x00000005 1837 #define CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK 0xffffffff 1838 #define CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT 0 1839 static inline uint32_t CP_SET_RENDER_MODE_5_ADDR_1_LEN(uint32_t val) 1840 { 1841 return ((val) << CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT) & CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK; 1842 } 1843 1844 #define REG_CP_SET_RENDER_MODE_6 0x00000006 1845 #define CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK 0xffffffff 1846 #define CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT 0 1847 static inline uint32_t CP_SET_RENDER_MODE_6_ADDR_1_LO(uint32_t val) 1848 { 1849 return ((val) << CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT) & CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK; 1850 } 1851 1852 #define REG_CP_SET_RENDER_MODE_7 0x00000007 1853 #define CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK 0xffffffff 1854 #define CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT 0 1855 static inline uint32_t CP_SET_RENDER_MODE_7_ADDR_1_HI(uint32_t val) 1856 { 1857 return ((val) << CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT) & CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK; 1858 } 1859 1860 #define REG_CP_COMPUTE_CHECKPOINT_0 0x00000000 1861 #define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK 0xffffffff 1862 #define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT 0 1863 static inline uint32_t CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO(uint32_t val) 1864 { 1865 return ((val) << CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK; 1866 } 1867 1868 #define REG_CP_COMPUTE_CHECKPOINT_1 0x00000001 1869 #define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK 0xffffffff 1870 #define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT 0 1871 static inline uint32_t CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI(uint32_t val) 1872 { 1873 return ((val) << CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK; 1874 } 1875 1876 #define REG_CP_COMPUTE_CHECKPOINT_2 0x00000002 1877 1878 #define REG_CP_COMPUTE_CHECKPOINT_3 0x00000003 1879 #define CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__MASK 0xffffffff 1880 #define CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__SHIFT 0 1881 static inline uint32_t CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN(uint32_t val) 1882 { 1883 return ((val) << CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__SHIFT) & CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__MASK; 1884 } 1885 1886 #define REG_CP_COMPUTE_CHECKPOINT_4 0x00000004 1887 1888 #define REG_CP_COMPUTE_CHECKPOINT_5 0x00000005 1889 #define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK 0xffffffff 1890 #define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT 0 1891 static inline uint32_t CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO(uint32_t val) 1892 { 1893 return ((val) << CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK; 1894 } 1895 1896 #define REG_CP_COMPUTE_CHECKPOINT_6 0x00000006 1897 #define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK 0xffffffff 1898 #define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT 0 1899 static inline uint32_t CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI(uint32_t val) 1900 { 1901 return ((val) << CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK; 1902 } 1903 1904 #define REG_CP_COMPUTE_CHECKPOINT_7 0x00000007 1905 1906 #define REG_CP_PERFCOUNTER_ACTION_0 0x00000000 1907 1908 #define REG_CP_PERFCOUNTER_ACTION_1 0x00000001 1909 #define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK 0xffffffff 1910 #define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT 0 1911 static inline uint32_t CP_PERFCOUNTER_ACTION_1_ADDR_0_LO(uint32_t val) 1912 { 1913 return ((val) << CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT) & CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK; 1914 } 1915 1916 #define REG_CP_PERFCOUNTER_ACTION_2 0x00000002 1917 #define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK 0xffffffff 1918 #define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT 0 1919 static inline uint32_t CP_PERFCOUNTER_ACTION_2_ADDR_0_HI(uint32_t val) 1920 { 1921 return ((val) << CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT) & CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK; 1922 } 1923 1924 #define REG_CP_EVENT_WRITE_0 0x00000000 1925 #define CP_EVENT_WRITE_0_EVENT__MASK 0x000000ff 1926 #define CP_EVENT_WRITE_0_EVENT__SHIFT 0 1927 static inline uint32_t CP_EVENT_WRITE_0_EVENT(enum vgt_event_type val) 1928 { 1929 return ((val) << CP_EVENT_WRITE_0_EVENT__SHIFT) & CP_EVENT_WRITE_0_EVENT__MASK; 1930 } 1931 #define CP_EVENT_WRITE_0_TIMESTAMP 0x40000000 1932 #define CP_EVENT_WRITE_0_IRQ 0x80000000 1933 1934 #define REG_CP_EVENT_WRITE_1 0x00000001 1935 #define CP_EVENT_WRITE_1_ADDR_0_LO__MASK 0xffffffff 1936 #define CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT 0 1937 static inline uint32_t CP_EVENT_WRITE_1_ADDR_0_LO(uint32_t val) 1938 { 1939 return ((val) << CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT) & CP_EVENT_WRITE_1_ADDR_0_LO__MASK; 1940 } 1941 1942 #define REG_CP_EVENT_WRITE_2 0x00000002 1943 #define CP_EVENT_WRITE_2_ADDR_0_HI__MASK 0xffffffff 1944 #define CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT 0 1945 static inline uint32_t CP_EVENT_WRITE_2_ADDR_0_HI(uint32_t val) 1946 { 1947 return ((val) << CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT) & CP_EVENT_WRITE_2_ADDR_0_HI__MASK; 1948 } 1949 1950 #define REG_CP_EVENT_WRITE_3 0x00000003 1951 1952 #define REG_CP_BLIT_0 0x00000000 1953 #define CP_BLIT_0_OP__MASK 0x0000000f 1954 #define CP_BLIT_0_OP__SHIFT 0 1955 static inline uint32_t CP_BLIT_0_OP(enum cp_blit_cmd val) 1956 { 1957 return ((val) << CP_BLIT_0_OP__SHIFT) & CP_BLIT_0_OP__MASK; 1958 } 1959 1960 #define REG_CP_BLIT_1 0x00000001 1961 #define CP_BLIT_1_SRC_X1__MASK 0x00003fff 1962 #define CP_BLIT_1_SRC_X1__SHIFT 0 1963 static inline uint32_t CP_BLIT_1_SRC_X1(uint32_t val) 1964 { 1965 return ((val) << CP_BLIT_1_SRC_X1__SHIFT) & CP_BLIT_1_SRC_X1__MASK; 1966 } 1967 #define CP_BLIT_1_SRC_Y1__MASK 0x3fff0000 1968 #define CP_BLIT_1_SRC_Y1__SHIFT 16 1969 static inline uint32_t CP_BLIT_1_SRC_Y1(uint32_t val) 1970 { 1971 return ((val) << CP_BLIT_1_SRC_Y1__SHIFT) & CP_BLIT_1_SRC_Y1__MASK; 1972 } 1973 1974 #define REG_CP_BLIT_2 0x00000002 1975 #define CP_BLIT_2_SRC_X2__MASK 0x00003fff 1976 #define CP_BLIT_2_SRC_X2__SHIFT 0 1977 static inline uint32_t CP_BLIT_2_SRC_X2(uint32_t val) 1978 { 1979 return ((val) << CP_BLIT_2_SRC_X2__SHIFT) & CP_BLIT_2_SRC_X2__MASK; 1980 } 1981 #define CP_BLIT_2_SRC_Y2__MASK 0x3fff0000 1982 #define CP_BLIT_2_SRC_Y2__SHIFT 16 1983 static inline uint32_t CP_BLIT_2_SRC_Y2(uint32_t val) 1984 { 1985 return ((val) << CP_BLIT_2_SRC_Y2__SHIFT) & CP_BLIT_2_SRC_Y2__MASK; 1986 } 1987 1988 #define REG_CP_BLIT_3 0x00000003 1989 #define CP_BLIT_3_DST_X1__MASK 0x00003fff 1990 #define CP_BLIT_3_DST_X1__SHIFT 0 1991 static inline uint32_t CP_BLIT_3_DST_X1(uint32_t val) 1992 { 1993 return ((val) << CP_BLIT_3_DST_X1__SHIFT) & CP_BLIT_3_DST_X1__MASK; 1994 } 1995 #define CP_BLIT_3_DST_Y1__MASK 0x3fff0000 1996 #define CP_BLIT_3_DST_Y1__SHIFT 16 1997 static inline uint32_t CP_BLIT_3_DST_Y1(uint32_t val) 1998 { 1999 return ((val) << CP_BLIT_3_DST_Y1__SHIFT) & CP_BLIT_3_DST_Y1__MASK; 2000 } 2001 2002 #define REG_CP_BLIT_4 0x00000004 2003 #define CP_BLIT_4_DST_X2__MASK 0x00003fff 2004 #define CP_BLIT_4_DST_X2__SHIFT 0 2005 static inline uint32_t CP_BLIT_4_DST_X2(uint32_t val) 2006 { 2007 return ((val) << CP_BLIT_4_DST_X2__SHIFT) & CP_BLIT_4_DST_X2__MASK; 2008 } 2009 #define CP_BLIT_4_DST_Y2__MASK 0x3fff0000 2010 #define CP_BLIT_4_DST_Y2__SHIFT 16 2011 static inline uint32_t CP_BLIT_4_DST_Y2(uint32_t val) 2012 { 2013 return ((val) << CP_BLIT_4_DST_Y2__SHIFT) & CP_BLIT_4_DST_Y2__MASK; 2014 } 2015 2016 #define REG_CP_EXEC_CS_0 0x00000000 2017 2018 #define REG_CP_EXEC_CS_1 0x00000001 2019 #define CP_EXEC_CS_1_NGROUPS_X__MASK 0xffffffff 2020 #define CP_EXEC_CS_1_NGROUPS_X__SHIFT 0 2021 static inline uint32_t CP_EXEC_CS_1_NGROUPS_X(uint32_t val) 2022 { 2023 return ((val) << CP_EXEC_CS_1_NGROUPS_X__SHIFT) & CP_EXEC_CS_1_NGROUPS_X__MASK; 2024 } 2025 2026 #define REG_CP_EXEC_CS_2 0x00000002 2027 #define CP_EXEC_CS_2_NGROUPS_Y__MASK 0xffffffff 2028 #define CP_EXEC_CS_2_NGROUPS_Y__SHIFT 0 2029 static inline uint32_t CP_EXEC_CS_2_NGROUPS_Y(uint32_t val) 2030 { 2031 return ((val) << CP_EXEC_CS_2_NGROUPS_Y__SHIFT) & CP_EXEC_CS_2_NGROUPS_Y__MASK; 2032 } 2033 2034 #define REG_CP_EXEC_CS_3 0x00000003 2035 #define CP_EXEC_CS_3_NGROUPS_Z__MASK 0xffffffff 2036 #define CP_EXEC_CS_3_NGROUPS_Z__SHIFT 0 2037 static inline uint32_t CP_EXEC_CS_3_NGROUPS_Z(uint32_t val) 2038 { 2039 return ((val) << CP_EXEC_CS_3_NGROUPS_Z__SHIFT) & CP_EXEC_CS_3_NGROUPS_Z__MASK; 2040 } 2041 2042 #define REG_A4XX_CP_EXEC_CS_INDIRECT_0 0x00000000 2043 2044 2045 #define REG_A4XX_CP_EXEC_CS_INDIRECT_1 0x00000001 2046 #define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK 0xffffffff 2047 #define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT 0 2048 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_1_ADDR(uint32_t val) 2049 { 2050 return ((val) << A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK; 2051 } 2052 2053 #define REG_A4XX_CP_EXEC_CS_INDIRECT_2 0x00000002 2054 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK 0x00000ffc 2055 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT 2 2056 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX(uint32_t val) 2057 { 2058 return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK; 2059 } 2060 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK 0x003ff000 2061 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT 12 2062 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY(uint32_t val) 2063 { 2064 return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK; 2065 } 2066 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK 0xffc00000 2067 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT 22 2068 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ(uint32_t val) 2069 { 2070 return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK; 2071 } 2072 2073 2074 #define REG_A5XX_CP_EXEC_CS_INDIRECT_1 0x00000001 2075 #define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK 0xffffffff 2076 #define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT 0 2077 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO(uint32_t val) 2078 { 2079 return ((val) << A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK; 2080 } 2081 2082 #define REG_A5XX_CP_EXEC_CS_INDIRECT_2 0x00000002 2083 #define A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK 0xffffffff 2084 #define A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT 0 2085 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI(uint32_t val) 2086 { 2087 return ((val) << A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK; 2088 } 2089 2090 #define REG_A5XX_CP_EXEC_CS_INDIRECT_3 0x00000003 2091 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK 0x00000ffc 2092 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT 2 2093 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(uint32_t val) 2094 { 2095 return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK; 2096 } 2097 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK 0x003ff000 2098 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT 12 2099 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(uint32_t val) 2100 { 2101 return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK; 2102 } 2103 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK 0xffc00000 2104 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT 22 2105 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(uint32_t val) 2106 { 2107 return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK; 2108 } 2109 2110 #define REG_A6XX_CP_SET_MARKER_0 0x00000000 2111 #define A6XX_CP_SET_MARKER_0_MODE__MASK 0x000001ff 2112 #define A6XX_CP_SET_MARKER_0_MODE__SHIFT 0 2113 static inline uint32_t A6XX_CP_SET_MARKER_0_MODE(enum a6xx_render_mode val) 2114 { 2115 return ((val) << A6XX_CP_SET_MARKER_0_MODE__SHIFT) & A6XX_CP_SET_MARKER_0_MODE__MASK; 2116 } 2117 #define A6XX_CP_SET_MARKER_0_MARKER__MASK 0x0000000f 2118 #define A6XX_CP_SET_MARKER_0_MARKER__SHIFT 0 2119 static inline uint32_t A6XX_CP_SET_MARKER_0_MARKER(enum a6xx_render_mode val) 2120 { 2121 return ((val) << A6XX_CP_SET_MARKER_0_MARKER__SHIFT) & A6XX_CP_SET_MARKER_0_MARKER__MASK; 2122 } 2123 2124 static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG_(uint32_t i0) { return 0x00000000 + 0x3*i0; } 2125 2126 static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG__0(uint32_t i0) { return 0x00000000 + 0x3*i0; } 2127 #define A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK 0x00000007 2128 #define A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT 0 2129 static inline uint32_t A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG(enum pseudo_reg val) 2130 { 2131 return ((val) << A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT) & A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK; 2132 } 2133 2134 static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG__1(uint32_t i0) { return 0x00000001 + 0x3*i0; } 2135 #define A6XX_CP_SET_PSEUDO_REG__1_LO__MASK 0xffffffff 2136 #define A6XX_CP_SET_PSEUDO_REG__1_LO__SHIFT 0 2137 static inline uint32_t A6XX_CP_SET_PSEUDO_REG__1_LO(uint32_t val) 2138 { 2139 return ((val) << A6XX_CP_SET_PSEUDO_REG__1_LO__SHIFT) & A6XX_CP_SET_PSEUDO_REG__1_LO__MASK; 2140 } 2141 2142 static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG__2(uint32_t i0) { return 0x00000002 + 0x3*i0; } 2143 #define A6XX_CP_SET_PSEUDO_REG__2_HI__MASK 0xffffffff 2144 #define A6XX_CP_SET_PSEUDO_REG__2_HI__SHIFT 0 2145 static inline uint32_t A6XX_CP_SET_PSEUDO_REG__2_HI(uint32_t val) 2146 { 2147 return ((val) << A6XX_CP_SET_PSEUDO_REG__2_HI__SHIFT) & A6XX_CP_SET_PSEUDO_REG__2_HI__MASK; 2148 } 2149 2150 #define REG_A6XX_CP_REG_TEST_0 0x00000000 2151 #define A6XX_CP_REG_TEST_0_REG__MASK 0x0003ffff 2152 #define A6XX_CP_REG_TEST_0_REG__SHIFT 0 2153 static inline uint32_t A6XX_CP_REG_TEST_0_REG(uint32_t val) 2154 { 2155 return ((val) << A6XX_CP_REG_TEST_0_REG__SHIFT) & A6XX_CP_REG_TEST_0_REG__MASK; 2156 } 2157 #define A6XX_CP_REG_TEST_0_BIT__MASK 0x01f00000 2158 #define A6XX_CP_REG_TEST_0_BIT__SHIFT 20 2159 static inline uint32_t A6XX_CP_REG_TEST_0_BIT(uint32_t val) 2160 { 2161 return ((val) << A6XX_CP_REG_TEST_0_BIT__SHIFT) & A6XX_CP_REG_TEST_0_BIT__MASK; 2162 } 2163 #define A6XX_CP_REG_TEST_0_WAIT_FOR_ME 0x02000000 2164 2165 #define REG_CP_COND_REG_EXEC_0 0x00000000 2166 #define CP_COND_REG_EXEC_0_REG0__MASK 0x0003ffff 2167 #define CP_COND_REG_EXEC_0_REG0__SHIFT 0 2168 static inline uint32_t CP_COND_REG_EXEC_0_REG0(uint32_t val) 2169 { 2170 return ((val) << CP_COND_REG_EXEC_0_REG0__SHIFT) & CP_COND_REG_EXEC_0_REG0__MASK; 2171 } 2172 #define CP_COND_REG_EXEC_0_BINNING 0x02000000 2173 #define CP_COND_REG_EXEC_0_GMEM 0x04000000 2174 #define CP_COND_REG_EXEC_0_SYSMEM 0x08000000 2175 #define CP_COND_REG_EXEC_0_MODE__MASK 0xf0000000 2176 #define CP_COND_REG_EXEC_0_MODE__SHIFT 28 2177 static inline uint32_t CP_COND_REG_EXEC_0_MODE(enum compare_mode val) 2178 { 2179 return ((val) << CP_COND_REG_EXEC_0_MODE__SHIFT) & CP_COND_REG_EXEC_0_MODE__MASK; 2180 } 2181 2182 #define REG_CP_COND_REG_EXEC_1 0x00000001 2183 #define CP_COND_REG_EXEC_1_DWORDS__MASK 0xffffffff 2184 #define CP_COND_REG_EXEC_1_DWORDS__SHIFT 0 2185 static inline uint32_t CP_COND_REG_EXEC_1_DWORDS(uint32_t val) 2186 { 2187 return ((val) << CP_COND_REG_EXEC_1_DWORDS__SHIFT) & CP_COND_REG_EXEC_1_DWORDS__MASK; 2188 } 2189 2190 #define REG_CP_COND_EXEC_0 0x00000000 2191 #define CP_COND_EXEC_0_ADDR0_LO__MASK 0xffffffff 2192 #define CP_COND_EXEC_0_ADDR0_LO__SHIFT 0 2193 static inline uint32_t CP_COND_EXEC_0_ADDR0_LO(uint32_t val) 2194 { 2195 return ((val) << CP_COND_EXEC_0_ADDR0_LO__SHIFT) & CP_COND_EXEC_0_ADDR0_LO__MASK; 2196 } 2197 2198 #define REG_CP_COND_EXEC_1 0x00000001 2199 #define CP_COND_EXEC_1_ADDR0_HI__MASK 0xffffffff 2200 #define CP_COND_EXEC_1_ADDR0_HI__SHIFT 0 2201 static inline uint32_t CP_COND_EXEC_1_ADDR0_HI(uint32_t val) 2202 { 2203 return ((val) << CP_COND_EXEC_1_ADDR0_HI__SHIFT) & CP_COND_EXEC_1_ADDR0_HI__MASK; 2204 } 2205 2206 #define REG_CP_COND_EXEC_2 0x00000002 2207 #define CP_COND_EXEC_2_ADDR1_LO__MASK 0xffffffff 2208 #define CP_COND_EXEC_2_ADDR1_LO__SHIFT 0 2209 static inline uint32_t CP_COND_EXEC_2_ADDR1_LO(uint32_t val) 2210 { 2211 return ((val) << CP_COND_EXEC_2_ADDR1_LO__SHIFT) & CP_COND_EXEC_2_ADDR1_LO__MASK; 2212 } 2213 2214 #define REG_CP_COND_EXEC_3 0x00000003 2215 #define CP_COND_EXEC_3_ADDR1_HI__MASK 0xffffffff 2216 #define CP_COND_EXEC_3_ADDR1_HI__SHIFT 0 2217 static inline uint32_t CP_COND_EXEC_3_ADDR1_HI(uint32_t val) 2218 { 2219 return ((val) << CP_COND_EXEC_3_ADDR1_HI__SHIFT) & CP_COND_EXEC_3_ADDR1_HI__MASK; 2220 } 2221 2222 #define REG_CP_COND_EXEC_4 0x00000004 2223 #define CP_COND_EXEC_4_REF__MASK 0xffffffff 2224 #define CP_COND_EXEC_4_REF__SHIFT 0 2225 static inline uint32_t CP_COND_EXEC_4_REF(uint32_t val) 2226 { 2227 return ((val) << CP_COND_EXEC_4_REF__SHIFT) & CP_COND_EXEC_4_REF__MASK; 2228 } 2229 2230 #define REG_CP_COND_EXEC_5 0x00000005 2231 #define CP_COND_EXEC_5_DWORDS__MASK 0xffffffff 2232 #define CP_COND_EXEC_5_DWORDS__SHIFT 0 2233 static inline uint32_t CP_COND_EXEC_5_DWORDS(uint32_t val) 2234 { 2235 return ((val) << CP_COND_EXEC_5_DWORDS__SHIFT) & CP_COND_EXEC_5_DWORDS__MASK; 2236 } 2237 2238 #define REG_CP_SET_CTXSWITCH_IB_0 0x00000000 2239 #define CP_SET_CTXSWITCH_IB_0_ADDR_LO__MASK 0xffffffff 2240 #define CP_SET_CTXSWITCH_IB_0_ADDR_LO__SHIFT 0 2241 static inline uint32_t CP_SET_CTXSWITCH_IB_0_ADDR_LO(uint32_t val) 2242 { 2243 return ((val) << CP_SET_CTXSWITCH_IB_0_ADDR_LO__SHIFT) & CP_SET_CTXSWITCH_IB_0_ADDR_LO__MASK; 2244 } 2245 2246 #define REG_CP_SET_CTXSWITCH_IB_1 0x00000001 2247 #define CP_SET_CTXSWITCH_IB_1_ADDR_HI__MASK 0xffffffff 2248 #define CP_SET_CTXSWITCH_IB_1_ADDR_HI__SHIFT 0 2249 static inline uint32_t CP_SET_CTXSWITCH_IB_1_ADDR_HI(uint32_t val) 2250 { 2251 return ((val) << CP_SET_CTXSWITCH_IB_1_ADDR_HI__SHIFT) & CP_SET_CTXSWITCH_IB_1_ADDR_HI__MASK; 2252 } 2253 2254 #define REG_CP_SET_CTXSWITCH_IB_2 0x00000002 2255 #define CP_SET_CTXSWITCH_IB_2_DWORDS__MASK 0x000fffff 2256 #define CP_SET_CTXSWITCH_IB_2_DWORDS__SHIFT 0 2257 static inline uint32_t CP_SET_CTXSWITCH_IB_2_DWORDS(uint32_t val) 2258 { 2259 return ((val) << CP_SET_CTXSWITCH_IB_2_DWORDS__SHIFT) & CP_SET_CTXSWITCH_IB_2_DWORDS__MASK; 2260 } 2261 #define CP_SET_CTXSWITCH_IB_2_TYPE__MASK 0x00300000 2262 #define CP_SET_CTXSWITCH_IB_2_TYPE__SHIFT 20 2263 static inline uint32_t CP_SET_CTXSWITCH_IB_2_TYPE(enum ctxswitch_ib val) 2264 { 2265 return ((val) << CP_SET_CTXSWITCH_IB_2_TYPE__SHIFT) & CP_SET_CTXSWITCH_IB_2_TYPE__MASK; 2266 } 2267 2268 #define REG_CP_REG_WRITE_0 0x00000000 2269 #define CP_REG_WRITE_0_TRACKER__MASK 0x00000007 2270 #define CP_REG_WRITE_0_TRACKER__SHIFT 0 2271 static inline uint32_t CP_REG_WRITE_0_TRACKER(enum reg_tracker val) 2272 { 2273 return ((val) << CP_REG_WRITE_0_TRACKER__SHIFT) & CP_REG_WRITE_0_TRACKER__MASK; 2274 } 2275 2276 #define REG_CP_SMMU_TABLE_UPDATE_0 0x00000000 2277 #define CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__MASK 0xffffffff 2278 #define CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__SHIFT 0 2279 static inline uint32_t CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(uint32_t val) 2280 { 2281 return ((val) << CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__SHIFT) & CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__MASK; 2282 } 2283 2284 #define REG_CP_SMMU_TABLE_UPDATE_1 0x00000001 2285 #define CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__MASK 0x0000ffff 2286 #define CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__SHIFT 0 2287 static inline uint32_t CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(uint32_t val) 2288 { 2289 return ((val) << CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__SHIFT) & CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__MASK; 2290 } 2291 #define CP_SMMU_TABLE_UPDATE_1_ASID__MASK 0xffff0000 2292 #define CP_SMMU_TABLE_UPDATE_1_ASID__SHIFT 16 2293 static inline uint32_t CP_SMMU_TABLE_UPDATE_1_ASID(uint32_t val) 2294 { 2295 return ((val) << CP_SMMU_TABLE_UPDATE_1_ASID__SHIFT) & CP_SMMU_TABLE_UPDATE_1_ASID__MASK; 2296 } 2297 2298 #define REG_CP_SMMU_TABLE_UPDATE_2 0x00000002 2299 #define CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__MASK 0xffffffff 2300 #define CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__SHIFT 0 2301 static inline uint32_t CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(uint32_t val) 2302 { 2303 return ((val) << CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__SHIFT) & CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__MASK; 2304 } 2305 2306 #define REG_CP_SMMU_TABLE_UPDATE_3 0x00000003 2307 #define CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__MASK 0xffffffff 2308 #define CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__SHIFT 0 2309 static inline uint32_t CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(uint32_t val) 2310 { 2311 return ((val) << CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__SHIFT) & CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__MASK; 2312 } 2313 2314 2315 #endif /* ADRENO_PM4_XML */ 2316