1 #ifndef ADRENO_PM4_XML 2 #define ADRENO_PM4_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2013-11-30 14:47:15) 12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2014-06-02 15:21:30) 14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2014-11-13 22:44:30) 15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 15053 bytes, from 2014-11-09 15:45:47) 16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 63169 bytes, from 2014-11-13 22:44:18) 17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 49097 bytes, from 2014-11-14 15:38:00) 18 19 Copyright (C) 2013-2014 by the following authors: 20 - Rob Clark <robdclark@gmail.com> (robclark) 21 22 Permission is hereby granted, free of charge, to any person obtaining 23 a copy of this software and associated documentation files (the 24 "Software"), to deal in the Software without restriction, including 25 without limitation the rights to use, copy, modify, merge, publish, 26 distribute, sublicense, and/or sell copies of the Software, and to 27 permit persons to whom the Software is furnished to do so, subject to 28 the following conditions: 29 30 The above copyright notice and this permission notice (including the 31 next paragraph) shall be included in all copies or substantial 32 portions of the Software. 33 34 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 35 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 36 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 37 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 38 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 39 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 40 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43 44 enum vgt_event_type { 45 VS_DEALLOC = 0, 46 PS_DEALLOC = 1, 47 VS_DONE_TS = 2, 48 PS_DONE_TS = 3, 49 CACHE_FLUSH_TS = 4, 50 CONTEXT_DONE = 5, 51 CACHE_FLUSH = 6, 52 HLSQ_FLUSH = 7, 53 VIZQUERY_START = 7, 54 VIZQUERY_END = 8, 55 SC_WAIT_WC = 9, 56 RST_PIX_CNT = 13, 57 RST_VTX_CNT = 14, 58 TILE_FLUSH = 15, 59 CACHE_FLUSH_AND_INV_TS_EVENT = 20, 60 ZPASS_DONE = 21, 61 CACHE_FLUSH_AND_INV_EVENT = 22, 62 PERFCOUNTER_START = 23, 63 PERFCOUNTER_STOP = 24, 64 VS_FETCH_DONE = 27, 65 FACENESS_FLUSH = 28, 66 }; 67 68 enum pc_di_primtype { 69 DI_PT_NONE = 0, 70 DI_PT_POINTLIST_A2XX = 1, 71 DI_PT_LINELIST = 2, 72 DI_PT_LINESTRIP = 3, 73 DI_PT_TRILIST = 4, 74 DI_PT_TRIFAN = 5, 75 DI_PT_TRISTRIP = 6, 76 DI_PT_LINELOOP = 7, 77 DI_PT_RECTLIST = 8, 78 DI_PT_POINTLIST_A3XX = 9, 79 DI_PT_QUADLIST = 13, 80 DI_PT_QUADSTRIP = 14, 81 DI_PT_POLYGON = 15, 82 DI_PT_2D_COPY_RECT_LIST_V0 = 16, 83 DI_PT_2D_COPY_RECT_LIST_V1 = 17, 84 DI_PT_2D_COPY_RECT_LIST_V2 = 18, 85 DI_PT_2D_COPY_RECT_LIST_V3 = 19, 86 DI_PT_2D_FILL_RECT_LIST = 20, 87 DI_PT_2D_LINE_STRIP = 21, 88 DI_PT_2D_TRI_STRIP = 22, 89 }; 90 91 enum pc_di_src_sel { 92 DI_SRC_SEL_DMA = 0, 93 DI_SRC_SEL_IMMEDIATE = 1, 94 DI_SRC_SEL_AUTO_INDEX = 2, 95 DI_SRC_SEL_RESERVED = 3, 96 }; 97 98 enum pc_di_index_size { 99 INDEX_SIZE_IGN = 0, 100 INDEX_SIZE_16_BIT = 0, 101 INDEX_SIZE_32_BIT = 1, 102 INDEX_SIZE_8_BIT = 2, 103 INDEX_SIZE_INVALID = 0, 104 }; 105 106 enum pc_di_vis_cull_mode { 107 IGNORE_VISIBILITY = 0, 108 USE_VISIBILITY = 1, 109 }; 110 111 enum adreno_pm4_packet_type { 112 CP_TYPE0_PKT = 0, 113 CP_TYPE1_PKT = 0x40000000, 114 CP_TYPE2_PKT = 0x80000000, 115 CP_TYPE3_PKT = 0xc0000000, 116 }; 117 118 enum adreno_pm4_type3_packets { 119 CP_ME_INIT = 72, 120 CP_NOP = 16, 121 CP_INDIRECT_BUFFER = 63, 122 CP_INDIRECT_BUFFER_PFD = 55, 123 CP_WAIT_FOR_IDLE = 38, 124 CP_WAIT_REG_MEM = 60, 125 CP_WAIT_REG_EQ = 82, 126 CP_WAIT_REG_GTE = 83, 127 CP_WAIT_UNTIL_READ = 92, 128 CP_WAIT_IB_PFD_COMPLETE = 93, 129 CP_REG_RMW = 33, 130 CP_SET_BIN_DATA = 47, 131 CP_REG_TO_MEM = 62, 132 CP_MEM_WRITE = 61, 133 CP_MEM_WRITE_CNTR = 79, 134 CP_COND_EXEC = 68, 135 CP_COND_WRITE = 69, 136 CP_EVENT_WRITE = 70, 137 CP_EVENT_WRITE_SHD = 88, 138 CP_EVENT_WRITE_CFL = 89, 139 CP_EVENT_WRITE_ZPD = 91, 140 CP_RUN_OPENCL = 49, 141 CP_DRAW_INDX = 34, 142 CP_DRAW_INDX_2 = 54, 143 CP_DRAW_INDX_BIN = 52, 144 CP_DRAW_INDX_2_BIN = 53, 145 CP_VIZ_QUERY = 35, 146 CP_SET_STATE = 37, 147 CP_SET_CONSTANT = 45, 148 CP_IM_LOAD = 39, 149 CP_IM_LOAD_IMMEDIATE = 43, 150 CP_LOAD_CONSTANT_CONTEXT = 46, 151 CP_INVALIDATE_STATE = 59, 152 CP_SET_SHADER_BASES = 74, 153 CP_SET_BIN_MASK = 80, 154 CP_SET_BIN_SELECT = 81, 155 CP_CONTEXT_UPDATE = 94, 156 CP_INTERRUPT = 64, 157 CP_IM_STORE = 44, 158 CP_SET_DRAW_INIT_FLAGS = 75, 159 CP_SET_PROTECTED_MODE = 95, 160 CP_BOOTSTRAP_UCODE = 111, 161 CP_LOAD_STATE = 48, 162 CP_COND_INDIRECT_BUFFER_PFE = 58, 163 CP_COND_INDIRECT_BUFFER_PFD = 50, 164 CP_INDIRECT_BUFFER_PFE = 63, 165 CP_SET_BIN = 76, 166 CP_TEST_TWO_MEMS = 113, 167 CP_REG_WR_NO_CTXT = 120, 168 CP_RECORD_PFP_TIMESTAMP = 17, 169 CP_WAIT_FOR_ME = 19, 170 CP_SET_DRAW_STATE = 67, 171 CP_DRAW_INDX_OFFSET = 56, 172 CP_DRAW_INDIRECT = 40, 173 CP_DRAW_INDX_INDIRECT = 41, 174 CP_DRAW_AUTO = 36, 175 CP_UNKNOWN_1A = 26, 176 CP_WIDE_REG_WRITE = 116, 177 IN_IB_PREFETCH_END = 23, 178 IN_SUBBLK_PREFETCH = 31, 179 IN_INSTR_PREFETCH = 32, 180 IN_INSTR_MATCH = 71, 181 IN_CONST_PREFETCH = 73, 182 IN_INCR_UPDT_STATE = 85, 183 IN_INCR_UPDT_CONST = 86, 184 IN_INCR_UPDT_INSTR = 87, 185 }; 186 187 enum adreno_state_block { 188 SB_VERT_TEX = 0, 189 SB_VERT_MIPADDR = 1, 190 SB_FRAG_TEX = 2, 191 SB_FRAG_MIPADDR = 3, 192 SB_VERT_SHADER = 4, 193 SB_FRAG_SHADER = 6, 194 }; 195 196 enum adreno_state_type { 197 ST_SHADER = 0, 198 ST_CONSTANTS = 1, 199 }; 200 201 enum adreno_state_src { 202 SS_DIRECT = 0, 203 SS_INDIRECT = 4, 204 }; 205 206 #define REG_CP_LOAD_STATE_0 0x00000000 207 #define CP_LOAD_STATE_0_DST_OFF__MASK 0x0000ffff 208 #define CP_LOAD_STATE_0_DST_OFF__SHIFT 0 209 static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val) 210 { 211 return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK; 212 } 213 #define CP_LOAD_STATE_0_STATE_SRC__MASK 0x00070000 214 #define CP_LOAD_STATE_0_STATE_SRC__SHIFT 16 215 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val) 216 { 217 return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK; 218 } 219 #define CP_LOAD_STATE_0_STATE_BLOCK__MASK 0x00380000 220 #define CP_LOAD_STATE_0_STATE_BLOCK__SHIFT 19 221 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val) 222 { 223 return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK; 224 } 225 #define CP_LOAD_STATE_0_NUM_UNIT__MASK 0x7fc00000 226 #define CP_LOAD_STATE_0_NUM_UNIT__SHIFT 22 227 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val) 228 { 229 return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK; 230 } 231 232 #define REG_CP_LOAD_STATE_1 0x00000001 233 #define CP_LOAD_STATE_1_STATE_TYPE__MASK 0x00000003 234 #define CP_LOAD_STATE_1_STATE_TYPE__SHIFT 0 235 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val) 236 { 237 return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK; 238 } 239 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK 0xfffffffc 240 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT 2 241 static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val) 242 { 243 return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK; 244 } 245 246 #define REG_CP_DRAW_INDX_0 0x00000000 247 #define CP_DRAW_INDX_0_VIZ_QUERY__MASK 0xffffffff 248 #define CP_DRAW_INDX_0_VIZ_QUERY__SHIFT 0 249 static inline uint32_t CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val) 250 { 251 return ((val) << CP_DRAW_INDX_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_0_VIZ_QUERY__MASK; 252 } 253 254 #define REG_CP_DRAW_INDX_1 0x00000001 255 #define CP_DRAW_INDX_1_PRIM_TYPE__MASK 0x0000003f 256 #define CP_DRAW_INDX_1_PRIM_TYPE__SHIFT 0 257 static inline uint32_t CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val) 258 { 259 return ((val) << CP_DRAW_INDX_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_1_PRIM_TYPE__MASK; 260 } 261 #define CP_DRAW_INDX_1_SOURCE_SELECT__MASK 0x000000c0 262 #define CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT 6 263 static inline uint32_t CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val) 264 { 265 return ((val) << CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_1_SOURCE_SELECT__MASK; 266 } 267 #define CP_DRAW_INDX_1_VIS_CULL__MASK 0x00000600 268 #define CP_DRAW_INDX_1_VIS_CULL__SHIFT 9 269 static inline uint32_t CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val) 270 { 271 return ((val) << CP_DRAW_INDX_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_1_VIS_CULL__MASK; 272 } 273 #define CP_DRAW_INDX_1_INDEX_SIZE__MASK 0x00000800 274 #define CP_DRAW_INDX_1_INDEX_SIZE__SHIFT 11 275 static inline uint32_t CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val) 276 { 277 return ((val) << CP_DRAW_INDX_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_1_INDEX_SIZE__MASK; 278 } 279 #define CP_DRAW_INDX_1_NOT_EOP 0x00001000 280 #define CP_DRAW_INDX_1_SMALL_INDEX 0x00002000 281 #define CP_DRAW_INDX_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000 282 #define CP_DRAW_INDX_1_NUM_INSTANCES__MASK 0xff000000 283 #define CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT 24 284 static inline uint32_t CP_DRAW_INDX_1_NUM_INSTANCES(uint32_t val) 285 { 286 return ((val) << CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_1_NUM_INSTANCES__MASK; 287 } 288 289 #define REG_CP_DRAW_INDX_2 0x00000002 290 #define CP_DRAW_INDX_2_NUM_INDICES__MASK 0xffffffff 291 #define CP_DRAW_INDX_2_NUM_INDICES__SHIFT 0 292 static inline uint32_t CP_DRAW_INDX_2_NUM_INDICES(uint32_t val) 293 { 294 return ((val) << CP_DRAW_INDX_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_NUM_INDICES__MASK; 295 } 296 297 #define REG_CP_DRAW_INDX_3 0x00000003 298 #define CP_DRAW_INDX_3_INDX_BASE__MASK 0xffffffff 299 #define CP_DRAW_INDX_3_INDX_BASE__SHIFT 0 300 static inline uint32_t CP_DRAW_INDX_3_INDX_BASE(uint32_t val) 301 { 302 return ((val) << CP_DRAW_INDX_3_INDX_BASE__SHIFT) & CP_DRAW_INDX_3_INDX_BASE__MASK; 303 } 304 305 #define REG_CP_DRAW_INDX_4 0x00000004 306 #define CP_DRAW_INDX_4_INDX_SIZE__MASK 0xffffffff 307 #define CP_DRAW_INDX_4_INDX_SIZE__SHIFT 0 308 static inline uint32_t CP_DRAW_INDX_4_INDX_SIZE(uint32_t val) 309 { 310 return ((val) << CP_DRAW_INDX_4_INDX_SIZE__SHIFT) & CP_DRAW_INDX_4_INDX_SIZE__MASK; 311 } 312 313 #define REG_CP_DRAW_INDX_2_0 0x00000000 314 #define CP_DRAW_INDX_2_0_VIZ_QUERY__MASK 0xffffffff 315 #define CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT 0 316 static inline uint32_t CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val) 317 { 318 return ((val) << CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_2_0_VIZ_QUERY__MASK; 319 } 320 321 #define REG_CP_DRAW_INDX_2_1 0x00000001 322 #define CP_DRAW_INDX_2_1_PRIM_TYPE__MASK 0x0000003f 323 #define CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT 0 324 static inline uint32_t CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val) 325 { 326 return ((val) << CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_2_1_PRIM_TYPE__MASK; 327 } 328 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK 0x000000c0 329 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT 6 330 static inline uint32_t CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val) 331 { 332 return ((val) << CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK; 333 } 334 #define CP_DRAW_INDX_2_1_VIS_CULL__MASK 0x00000600 335 #define CP_DRAW_INDX_2_1_VIS_CULL__SHIFT 9 336 static inline uint32_t CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val) 337 { 338 return ((val) << CP_DRAW_INDX_2_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_2_1_VIS_CULL__MASK; 339 } 340 #define CP_DRAW_INDX_2_1_INDEX_SIZE__MASK 0x00000800 341 #define CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT 11 342 static inline uint32_t CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val) 343 { 344 return ((val) << CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_2_1_INDEX_SIZE__MASK; 345 } 346 #define CP_DRAW_INDX_2_1_NOT_EOP 0x00001000 347 #define CP_DRAW_INDX_2_1_SMALL_INDEX 0x00002000 348 #define CP_DRAW_INDX_2_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000 349 #define CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK 0xff000000 350 #define CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT 24 351 static inline uint32_t CP_DRAW_INDX_2_1_NUM_INSTANCES(uint32_t val) 352 { 353 return ((val) << CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK; 354 } 355 356 #define REG_CP_DRAW_INDX_2_2 0x00000002 357 #define CP_DRAW_INDX_2_2_NUM_INDICES__MASK 0xffffffff 358 #define CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT 0 359 static inline uint32_t CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val) 360 { 361 return ((val) << CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_2_NUM_INDICES__MASK; 362 } 363 364 #define REG_CP_DRAW_INDX_OFFSET_0 0x00000000 365 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK 0x0000003f 366 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT 0 367 static inline uint32_t CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val) 368 { 369 return ((val) << CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK; 370 } 371 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK 0x000000c0 372 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT 6 373 static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val) 374 { 375 return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK; 376 } 377 #define CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK 0x00000700 378 #define CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT 8 379 static inline uint32_t CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val) 380 { 381 return ((val) << CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT) & CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK; 382 } 383 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK 0x00000800 384 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT 11 385 static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum pc_di_index_size val) 386 { 387 return ((val) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK; 388 } 389 #define CP_DRAW_INDX_OFFSET_0_NOT_EOP 0x00001000 390 #define CP_DRAW_INDX_OFFSET_0_SMALL_INDEX 0x00002000 391 #define CP_DRAW_INDX_OFFSET_0_PRE_DRAW_INITIATOR_ENABLE 0x00004000 392 #define CP_DRAW_INDX_OFFSET_0_NUM_INSTANCES__MASK 0xffff0000 393 #define CP_DRAW_INDX_OFFSET_0_NUM_INSTANCES__SHIFT 16 394 static inline uint32_t CP_DRAW_INDX_OFFSET_0_NUM_INSTANCES(uint32_t val) 395 { 396 return ((val) << CP_DRAW_INDX_OFFSET_0_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_OFFSET_0_NUM_INSTANCES__MASK; 397 } 398 399 #define REG_CP_DRAW_INDX_OFFSET_1 0x00000001 400 401 #define REG_CP_DRAW_INDX_OFFSET_2 0x00000002 402 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK 0xffffffff 403 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT 0 404 static inline uint32_t CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val) 405 { 406 return ((val) << CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK; 407 } 408 409 #define REG_CP_DRAW_INDX_OFFSET_3 0x00000003 410 411 #define REG_CP_DRAW_INDX_OFFSET_4 0x00000004 412 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK 0xffffffff 413 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT 0 414 static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE(uint32_t val) 415 { 416 return ((val) << CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK; 417 } 418 419 #define REG_CP_DRAW_INDX_OFFSET_5 0x00000005 420 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK 0xffffffff 421 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT 0 422 static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_SIZE(uint32_t val) 423 { 424 return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK; 425 } 426 427 #define REG_CP_SET_DRAW_STATE_0 0x00000000 428 #define CP_SET_DRAW_STATE_0_COUNT__MASK 0x0000ffff 429 #define CP_SET_DRAW_STATE_0_COUNT__SHIFT 0 430 static inline uint32_t CP_SET_DRAW_STATE_0_COUNT(uint32_t val) 431 { 432 return ((val) << CP_SET_DRAW_STATE_0_COUNT__SHIFT) & CP_SET_DRAW_STATE_0_COUNT__MASK; 433 } 434 #define CP_SET_DRAW_STATE_0_DIRTY 0x00010000 435 #define CP_SET_DRAW_STATE_0_DISABLE 0x00020000 436 #define CP_SET_DRAW_STATE_0_DISABLE_ALL_GROUPS 0x00040000 437 #define CP_SET_DRAW_STATE_0_LOAD_IMMED 0x00080000 438 #define CP_SET_DRAW_STATE_0_GROUP_ID__MASK 0x1f000000 439 #define CP_SET_DRAW_STATE_0_GROUP_ID__SHIFT 24 440 static inline uint32_t CP_SET_DRAW_STATE_0_GROUP_ID(uint32_t val) 441 { 442 return ((val) << CP_SET_DRAW_STATE_0_GROUP_ID__SHIFT) & CP_SET_DRAW_STATE_0_GROUP_ID__MASK; 443 } 444 445 #define REG_CP_SET_DRAW_STATE_1 0x00000001 446 #define CP_SET_DRAW_STATE_1_ADDR__MASK 0xffffffff 447 #define CP_SET_DRAW_STATE_1_ADDR__SHIFT 0 448 static inline uint32_t CP_SET_DRAW_STATE_1_ADDR(uint32_t val) 449 { 450 return ((val) << CP_SET_DRAW_STATE_1_ADDR__SHIFT) & CP_SET_DRAW_STATE_1_ADDR__MASK; 451 } 452 453 #define REG_CP_SET_BIN_0 0x00000000 454 455 #define REG_CP_SET_BIN_1 0x00000001 456 #define CP_SET_BIN_1_X1__MASK 0x0000ffff 457 #define CP_SET_BIN_1_X1__SHIFT 0 458 static inline uint32_t CP_SET_BIN_1_X1(uint32_t val) 459 { 460 return ((val) << CP_SET_BIN_1_X1__SHIFT) & CP_SET_BIN_1_X1__MASK; 461 } 462 #define CP_SET_BIN_1_Y1__MASK 0xffff0000 463 #define CP_SET_BIN_1_Y1__SHIFT 16 464 static inline uint32_t CP_SET_BIN_1_Y1(uint32_t val) 465 { 466 return ((val) << CP_SET_BIN_1_Y1__SHIFT) & CP_SET_BIN_1_Y1__MASK; 467 } 468 469 #define REG_CP_SET_BIN_2 0x00000002 470 #define CP_SET_BIN_2_X2__MASK 0x0000ffff 471 #define CP_SET_BIN_2_X2__SHIFT 0 472 static inline uint32_t CP_SET_BIN_2_X2(uint32_t val) 473 { 474 return ((val) << CP_SET_BIN_2_X2__SHIFT) & CP_SET_BIN_2_X2__MASK; 475 } 476 #define CP_SET_BIN_2_Y2__MASK 0xffff0000 477 #define CP_SET_BIN_2_Y2__SHIFT 16 478 static inline uint32_t CP_SET_BIN_2_Y2(uint32_t val) 479 { 480 return ((val) << CP_SET_BIN_2_Y2__SHIFT) & CP_SET_BIN_2_Y2__MASK; 481 } 482 483 #define REG_CP_SET_BIN_DATA_0 0x00000000 484 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK 0xffffffff 485 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT 0 486 static inline uint32_t CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val) 487 { 488 return ((val) << CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT) & CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK; 489 } 490 491 #define REG_CP_SET_BIN_DATA_1 0x00000001 492 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK 0xffffffff 493 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT 0 494 static inline uint32_t CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val) 495 { 496 return ((val) << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK; 497 } 498 499 500 #endif /* ADRENO_PM4_XML */ 501