1 #ifndef ADRENO_PM4_XML
2 #define ADRENO_PM4_XML
3 
4 /* Autogenerated file, DO NOT EDIT manually!
5 
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
9 
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    364 bytes, from 2015-05-20 20:03:07)
12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2015-05-20 20:03:07)
13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2015-05-20 20:03:14)
14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  10551 bytes, from 2015-05-20 20:03:14)
15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  14968 bytes, from 2015-05-20 20:12:27)
16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  67120 bytes, from 2015-08-14 23:22:03)
17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  63785 bytes, from 2015-08-14 18:27:06)
18 
19 Copyright (C) 2013-2015 by the following authors:
20 - Rob Clark <robdclark@gmail.com> (robclark)
21 
22 Permission is hereby granted, free of charge, to any person obtaining
23 a copy of this software and associated documentation files (the
24 "Software"), to deal in the Software without restriction, including
25 without limitation the rights to use, copy, modify, merge, publish,
26 distribute, sublicense, and/or sell copies of the Software, and to
27 permit persons to whom the Software is furnished to do so, subject to
28 the following conditions:
29 
30 The above copyright notice and this permission notice (including the
31 next paragraph) shall be included in all copies or substantial
32 portions of the Software.
33 
34 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
36 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
37 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
38 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
39 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
40 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
41 */
42 
43 
44 enum vgt_event_type {
45 	VS_DEALLOC = 0,
46 	PS_DEALLOC = 1,
47 	VS_DONE_TS = 2,
48 	PS_DONE_TS = 3,
49 	CACHE_FLUSH_TS = 4,
50 	CONTEXT_DONE = 5,
51 	CACHE_FLUSH = 6,
52 	HLSQ_FLUSH = 7,
53 	VIZQUERY_START = 7,
54 	VIZQUERY_END = 8,
55 	SC_WAIT_WC = 9,
56 	RST_PIX_CNT = 13,
57 	RST_VTX_CNT = 14,
58 	TILE_FLUSH = 15,
59 	CACHE_FLUSH_AND_INV_TS_EVENT = 20,
60 	ZPASS_DONE = 21,
61 	CACHE_FLUSH_AND_INV_EVENT = 22,
62 	PERFCOUNTER_START = 23,
63 	PERFCOUNTER_STOP = 24,
64 	VS_FETCH_DONE = 27,
65 	FACENESS_FLUSH = 28,
66 };
67 
68 enum pc_di_primtype {
69 	DI_PT_NONE = 0,
70 	DI_PT_POINTLIST_PSIZE = 1,
71 	DI_PT_LINELIST = 2,
72 	DI_PT_LINESTRIP = 3,
73 	DI_PT_TRILIST = 4,
74 	DI_PT_TRIFAN = 5,
75 	DI_PT_TRISTRIP = 6,
76 	DI_PT_LINELOOP = 7,
77 	DI_PT_RECTLIST = 8,
78 	DI_PT_POINTLIST = 9,
79 	DI_PT_LINE_ADJ = 10,
80 	DI_PT_LINESTRIP_ADJ = 11,
81 	DI_PT_TRI_ADJ = 12,
82 	DI_PT_TRISTRIP_ADJ = 13,
83 	DI_PT_PATCHES = 34,
84 };
85 
86 enum pc_di_src_sel {
87 	DI_SRC_SEL_DMA = 0,
88 	DI_SRC_SEL_IMMEDIATE = 1,
89 	DI_SRC_SEL_AUTO_INDEX = 2,
90 	DI_SRC_SEL_RESERVED = 3,
91 };
92 
93 enum pc_di_index_size {
94 	INDEX_SIZE_IGN = 0,
95 	INDEX_SIZE_16_BIT = 0,
96 	INDEX_SIZE_32_BIT = 1,
97 	INDEX_SIZE_8_BIT = 2,
98 	INDEX_SIZE_INVALID = 0,
99 };
100 
101 enum pc_di_vis_cull_mode {
102 	IGNORE_VISIBILITY = 0,
103 	USE_VISIBILITY = 1,
104 };
105 
106 enum adreno_pm4_packet_type {
107 	CP_TYPE0_PKT = 0,
108 	CP_TYPE1_PKT = 0x40000000,
109 	CP_TYPE2_PKT = 0x80000000,
110 	CP_TYPE3_PKT = 0xc0000000,
111 };
112 
113 enum adreno_pm4_type3_packets {
114 	CP_ME_INIT = 72,
115 	CP_NOP = 16,
116 	CP_INDIRECT_BUFFER = 63,
117 	CP_INDIRECT_BUFFER_PFD = 55,
118 	CP_WAIT_FOR_IDLE = 38,
119 	CP_WAIT_REG_MEM = 60,
120 	CP_WAIT_REG_EQ = 82,
121 	CP_WAIT_REG_GTE = 83,
122 	CP_WAIT_UNTIL_READ = 92,
123 	CP_WAIT_IB_PFD_COMPLETE = 93,
124 	CP_REG_RMW = 33,
125 	CP_SET_BIN_DATA = 47,
126 	CP_REG_TO_MEM = 62,
127 	CP_MEM_WRITE = 61,
128 	CP_MEM_WRITE_CNTR = 79,
129 	CP_COND_EXEC = 68,
130 	CP_COND_WRITE = 69,
131 	CP_EVENT_WRITE = 70,
132 	CP_EVENT_WRITE_SHD = 88,
133 	CP_EVENT_WRITE_CFL = 89,
134 	CP_EVENT_WRITE_ZPD = 91,
135 	CP_RUN_OPENCL = 49,
136 	CP_DRAW_INDX = 34,
137 	CP_DRAW_INDX_2 = 54,
138 	CP_DRAW_INDX_BIN = 52,
139 	CP_DRAW_INDX_2_BIN = 53,
140 	CP_VIZ_QUERY = 35,
141 	CP_SET_STATE = 37,
142 	CP_SET_CONSTANT = 45,
143 	CP_IM_LOAD = 39,
144 	CP_IM_LOAD_IMMEDIATE = 43,
145 	CP_LOAD_CONSTANT_CONTEXT = 46,
146 	CP_INVALIDATE_STATE = 59,
147 	CP_SET_SHADER_BASES = 74,
148 	CP_SET_BIN_MASK = 80,
149 	CP_SET_BIN_SELECT = 81,
150 	CP_CONTEXT_UPDATE = 94,
151 	CP_INTERRUPT = 64,
152 	CP_IM_STORE = 44,
153 	CP_SET_DRAW_INIT_FLAGS = 75,
154 	CP_SET_PROTECTED_MODE = 95,
155 	CP_BOOTSTRAP_UCODE = 111,
156 	CP_LOAD_STATE = 48,
157 	CP_COND_INDIRECT_BUFFER_PFE = 58,
158 	CP_COND_INDIRECT_BUFFER_PFD = 50,
159 	CP_INDIRECT_BUFFER_PFE = 63,
160 	CP_SET_BIN = 76,
161 	CP_TEST_TWO_MEMS = 113,
162 	CP_REG_WR_NO_CTXT = 120,
163 	CP_RECORD_PFP_TIMESTAMP = 17,
164 	CP_WAIT_FOR_ME = 19,
165 	CP_SET_DRAW_STATE = 67,
166 	CP_DRAW_INDX_OFFSET = 56,
167 	CP_DRAW_INDIRECT = 40,
168 	CP_DRAW_INDX_INDIRECT = 41,
169 	CP_DRAW_AUTO = 36,
170 	CP_UNKNOWN_19 = 25,
171 	CP_UNKNOWN_1A = 26,
172 	CP_UNKNOWN_4E = 78,
173 	CP_WIDE_REG_WRITE = 116,
174 	IN_IB_PREFETCH_END = 23,
175 	IN_SUBBLK_PREFETCH = 31,
176 	IN_INSTR_PREFETCH = 32,
177 	IN_INSTR_MATCH = 71,
178 	IN_CONST_PREFETCH = 73,
179 	IN_INCR_UPDT_STATE = 85,
180 	IN_INCR_UPDT_CONST = 86,
181 	IN_INCR_UPDT_INSTR = 87,
182 };
183 
184 enum adreno_state_block {
185 	SB_VERT_TEX = 0,
186 	SB_VERT_MIPADDR = 1,
187 	SB_FRAG_TEX = 2,
188 	SB_FRAG_MIPADDR = 3,
189 	SB_VERT_SHADER = 4,
190 	SB_GEOM_SHADER = 5,
191 	SB_FRAG_SHADER = 6,
192 };
193 
194 enum adreno_state_type {
195 	ST_SHADER = 0,
196 	ST_CONSTANTS = 1,
197 };
198 
199 enum adreno_state_src {
200 	SS_DIRECT = 0,
201 	SS_INDIRECT = 4,
202 };
203 
204 enum a4xx_index_size {
205 	INDEX4_SIZE_8_BIT = 0,
206 	INDEX4_SIZE_16_BIT = 1,
207 	INDEX4_SIZE_32_BIT = 2,
208 };
209 
210 #define REG_CP_LOAD_STATE_0					0x00000000
211 #define CP_LOAD_STATE_0_DST_OFF__MASK				0x0000ffff
212 #define CP_LOAD_STATE_0_DST_OFF__SHIFT				0
213 static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val)
214 {
215 	return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK;
216 }
217 #define CP_LOAD_STATE_0_STATE_SRC__MASK				0x00070000
218 #define CP_LOAD_STATE_0_STATE_SRC__SHIFT			16
219 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val)
220 {
221 	return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK;
222 }
223 #define CP_LOAD_STATE_0_STATE_BLOCK__MASK			0x00380000
224 #define CP_LOAD_STATE_0_STATE_BLOCK__SHIFT			19
225 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val)
226 {
227 	return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK;
228 }
229 #define CP_LOAD_STATE_0_NUM_UNIT__MASK				0x7fc00000
230 #define CP_LOAD_STATE_0_NUM_UNIT__SHIFT				22
231 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val)
232 {
233 	return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK;
234 }
235 
236 #define REG_CP_LOAD_STATE_1					0x00000001
237 #define CP_LOAD_STATE_1_STATE_TYPE__MASK			0x00000003
238 #define CP_LOAD_STATE_1_STATE_TYPE__SHIFT			0
239 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val)
240 {
241 	return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK;
242 }
243 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK			0xfffffffc
244 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT			2
245 static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val)
246 {
247 	return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK;
248 }
249 
250 #define REG_CP_DRAW_INDX_0					0x00000000
251 #define CP_DRAW_INDX_0_VIZ_QUERY__MASK				0xffffffff
252 #define CP_DRAW_INDX_0_VIZ_QUERY__SHIFT				0
253 static inline uint32_t CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val)
254 {
255 	return ((val) << CP_DRAW_INDX_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_0_VIZ_QUERY__MASK;
256 }
257 
258 #define REG_CP_DRAW_INDX_1					0x00000001
259 #define CP_DRAW_INDX_1_PRIM_TYPE__MASK				0x0000003f
260 #define CP_DRAW_INDX_1_PRIM_TYPE__SHIFT				0
261 static inline uint32_t CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val)
262 {
263 	return ((val) << CP_DRAW_INDX_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_1_PRIM_TYPE__MASK;
264 }
265 #define CP_DRAW_INDX_1_SOURCE_SELECT__MASK			0x000000c0
266 #define CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT			6
267 static inline uint32_t CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val)
268 {
269 	return ((val) << CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_1_SOURCE_SELECT__MASK;
270 }
271 #define CP_DRAW_INDX_1_VIS_CULL__MASK				0x00000600
272 #define CP_DRAW_INDX_1_VIS_CULL__SHIFT				9
273 static inline uint32_t CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val)
274 {
275 	return ((val) << CP_DRAW_INDX_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_1_VIS_CULL__MASK;
276 }
277 #define CP_DRAW_INDX_1_INDEX_SIZE__MASK				0x00000800
278 #define CP_DRAW_INDX_1_INDEX_SIZE__SHIFT			11
279 static inline uint32_t CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val)
280 {
281 	return ((val) << CP_DRAW_INDX_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_1_INDEX_SIZE__MASK;
282 }
283 #define CP_DRAW_INDX_1_NOT_EOP					0x00001000
284 #define CP_DRAW_INDX_1_SMALL_INDEX				0x00002000
285 #define CP_DRAW_INDX_1_PRE_DRAW_INITIATOR_ENABLE		0x00004000
286 #define CP_DRAW_INDX_1_NUM_INSTANCES__MASK			0xff000000
287 #define CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT			24
288 static inline uint32_t CP_DRAW_INDX_1_NUM_INSTANCES(uint32_t val)
289 {
290 	return ((val) << CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_1_NUM_INSTANCES__MASK;
291 }
292 
293 #define REG_CP_DRAW_INDX_2					0x00000002
294 #define CP_DRAW_INDX_2_NUM_INDICES__MASK			0xffffffff
295 #define CP_DRAW_INDX_2_NUM_INDICES__SHIFT			0
296 static inline uint32_t CP_DRAW_INDX_2_NUM_INDICES(uint32_t val)
297 {
298 	return ((val) << CP_DRAW_INDX_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_NUM_INDICES__MASK;
299 }
300 
301 #define REG_CP_DRAW_INDX_3					0x00000003
302 #define CP_DRAW_INDX_3_INDX_BASE__MASK				0xffffffff
303 #define CP_DRAW_INDX_3_INDX_BASE__SHIFT				0
304 static inline uint32_t CP_DRAW_INDX_3_INDX_BASE(uint32_t val)
305 {
306 	return ((val) << CP_DRAW_INDX_3_INDX_BASE__SHIFT) & CP_DRAW_INDX_3_INDX_BASE__MASK;
307 }
308 
309 #define REG_CP_DRAW_INDX_4					0x00000004
310 #define CP_DRAW_INDX_4_INDX_SIZE__MASK				0xffffffff
311 #define CP_DRAW_INDX_4_INDX_SIZE__SHIFT				0
312 static inline uint32_t CP_DRAW_INDX_4_INDX_SIZE(uint32_t val)
313 {
314 	return ((val) << CP_DRAW_INDX_4_INDX_SIZE__SHIFT) & CP_DRAW_INDX_4_INDX_SIZE__MASK;
315 }
316 
317 #define REG_CP_DRAW_INDX_2_0					0x00000000
318 #define CP_DRAW_INDX_2_0_VIZ_QUERY__MASK			0xffffffff
319 #define CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT			0
320 static inline uint32_t CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val)
321 {
322 	return ((val) << CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_2_0_VIZ_QUERY__MASK;
323 }
324 
325 #define REG_CP_DRAW_INDX_2_1					0x00000001
326 #define CP_DRAW_INDX_2_1_PRIM_TYPE__MASK			0x0000003f
327 #define CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT			0
328 static inline uint32_t CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val)
329 {
330 	return ((val) << CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_2_1_PRIM_TYPE__MASK;
331 }
332 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK			0x000000c0
333 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT			6
334 static inline uint32_t CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val)
335 {
336 	return ((val) << CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK;
337 }
338 #define CP_DRAW_INDX_2_1_VIS_CULL__MASK				0x00000600
339 #define CP_DRAW_INDX_2_1_VIS_CULL__SHIFT			9
340 static inline uint32_t CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val)
341 {
342 	return ((val) << CP_DRAW_INDX_2_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_2_1_VIS_CULL__MASK;
343 }
344 #define CP_DRAW_INDX_2_1_INDEX_SIZE__MASK			0x00000800
345 #define CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT			11
346 static inline uint32_t CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val)
347 {
348 	return ((val) << CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_2_1_INDEX_SIZE__MASK;
349 }
350 #define CP_DRAW_INDX_2_1_NOT_EOP				0x00001000
351 #define CP_DRAW_INDX_2_1_SMALL_INDEX				0x00002000
352 #define CP_DRAW_INDX_2_1_PRE_DRAW_INITIATOR_ENABLE		0x00004000
353 #define CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK			0xff000000
354 #define CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT			24
355 static inline uint32_t CP_DRAW_INDX_2_1_NUM_INSTANCES(uint32_t val)
356 {
357 	return ((val) << CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK;
358 }
359 
360 #define REG_CP_DRAW_INDX_2_2					0x00000002
361 #define CP_DRAW_INDX_2_2_NUM_INDICES__MASK			0xffffffff
362 #define CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT			0
363 static inline uint32_t CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val)
364 {
365 	return ((val) << CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_2_NUM_INDICES__MASK;
366 }
367 
368 #define REG_CP_DRAW_INDX_OFFSET_0				0x00000000
369 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK			0x0000003f
370 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT			0
371 static inline uint32_t CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val)
372 {
373 	return ((val) << CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK;
374 }
375 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK		0x000000c0
376 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT		6
377 static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val)
378 {
379 	return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK;
380 }
381 #define CP_DRAW_INDX_OFFSET_0_TESSELLATE			0x00000100
382 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK			0x00000c00
383 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT			10
384 static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val)
385 {
386 	return ((val) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK;
387 }
388 #define CP_DRAW_INDX_OFFSET_0_TESS_MODE__MASK			0x01f00000
389 #define CP_DRAW_INDX_OFFSET_0_TESS_MODE__SHIFT			20
390 static inline uint32_t CP_DRAW_INDX_OFFSET_0_TESS_MODE(uint32_t val)
391 {
392 	return ((val) << CP_DRAW_INDX_OFFSET_0_TESS_MODE__SHIFT) & CP_DRAW_INDX_OFFSET_0_TESS_MODE__MASK;
393 }
394 
395 #define REG_CP_DRAW_INDX_OFFSET_1				0x00000001
396 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK		0xffffffff
397 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT		0
398 static inline uint32_t CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES(uint32_t val)
399 {
400 	return ((val) << CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK;
401 }
402 
403 #define REG_CP_DRAW_INDX_OFFSET_2				0x00000002
404 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK			0xffffffff
405 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT		0
406 static inline uint32_t CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val)
407 {
408 	return ((val) << CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK;
409 }
410 
411 #define REG_CP_DRAW_INDX_OFFSET_3				0x00000003
412 
413 #define REG_CP_DRAW_INDX_OFFSET_4				0x00000004
414 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK			0xffffffff
415 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT			0
416 static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE(uint32_t val)
417 {
418 	return ((val) << CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK;
419 }
420 
421 #define REG_CP_DRAW_INDX_OFFSET_5				0x00000005
422 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK			0xffffffff
423 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT			0
424 static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_SIZE(uint32_t val)
425 {
426 	return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK;
427 }
428 
429 #define REG_CP_SET_DRAW_STATE_0					0x00000000
430 #define CP_SET_DRAW_STATE_0_COUNT__MASK				0x0000ffff
431 #define CP_SET_DRAW_STATE_0_COUNT__SHIFT			0
432 static inline uint32_t CP_SET_DRAW_STATE_0_COUNT(uint32_t val)
433 {
434 	return ((val) << CP_SET_DRAW_STATE_0_COUNT__SHIFT) & CP_SET_DRAW_STATE_0_COUNT__MASK;
435 }
436 #define CP_SET_DRAW_STATE_0_DIRTY				0x00010000
437 #define CP_SET_DRAW_STATE_0_DISABLE				0x00020000
438 #define CP_SET_DRAW_STATE_0_DISABLE_ALL_GROUPS			0x00040000
439 #define CP_SET_DRAW_STATE_0_LOAD_IMMED				0x00080000
440 #define CP_SET_DRAW_STATE_0_GROUP_ID__MASK			0x1f000000
441 #define CP_SET_DRAW_STATE_0_GROUP_ID__SHIFT			24
442 static inline uint32_t CP_SET_DRAW_STATE_0_GROUP_ID(uint32_t val)
443 {
444 	return ((val) << CP_SET_DRAW_STATE_0_GROUP_ID__SHIFT) & CP_SET_DRAW_STATE_0_GROUP_ID__MASK;
445 }
446 
447 #define REG_CP_SET_DRAW_STATE_1					0x00000001
448 #define CP_SET_DRAW_STATE_1_ADDR__MASK				0xffffffff
449 #define CP_SET_DRAW_STATE_1_ADDR__SHIFT				0
450 static inline uint32_t CP_SET_DRAW_STATE_1_ADDR(uint32_t val)
451 {
452 	return ((val) << CP_SET_DRAW_STATE_1_ADDR__SHIFT) & CP_SET_DRAW_STATE_1_ADDR__MASK;
453 }
454 
455 #define REG_CP_SET_BIN_0					0x00000000
456 
457 #define REG_CP_SET_BIN_1					0x00000001
458 #define CP_SET_BIN_1_X1__MASK					0x0000ffff
459 #define CP_SET_BIN_1_X1__SHIFT					0
460 static inline uint32_t CP_SET_BIN_1_X1(uint32_t val)
461 {
462 	return ((val) << CP_SET_BIN_1_X1__SHIFT) & CP_SET_BIN_1_X1__MASK;
463 }
464 #define CP_SET_BIN_1_Y1__MASK					0xffff0000
465 #define CP_SET_BIN_1_Y1__SHIFT					16
466 static inline uint32_t CP_SET_BIN_1_Y1(uint32_t val)
467 {
468 	return ((val) << CP_SET_BIN_1_Y1__SHIFT) & CP_SET_BIN_1_Y1__MASK;
469 }
470 
471 #define REG_CP_SET_BIN_2					0x00000002
472 #define CP_SET_BIN_2_X2__MASK					0x0000ffff
473 #define CP_SET_BIN_2_X2__SHIFT					0
474 static inline uint32_t CP_SET_BIN_2_X2(uint32_t val)
475 {
476 	return ((val) << CP_SET_BIN_2_X2__SHIFT) & CP_SET_BIN_2_X2__MASK;
477 }
478 #define CP_SET_BIN_2_Y2__MASK					0xffff0000
479 #define CP_SET_BIN_2_Y2__SHIFT					16
480 static inline uint32_t CP_SET_BIN_2_Y2(uint32_t val)
481 {
482 	return ((val) << CP_SET_BIN_2_Y2__SHIFT) & CP_SET_BIN_2_Y2__MASK;
483 }
484 
485 #define REG_CP_SET_BIN_DATA_0					0x00000000
486 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK			0xffffffff
487 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT			0
488 static inline uint32_t CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val)
489 {
490 	return ((val) << CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT) & CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK;
491 }
492 
493 #define REG_CP_SET_BIN_DATA_1					0x00000001
494 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK		0xffffffff
495 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT		0
496 static inline uint32_t CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val)
497 {
498 	return ((val) << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK;
499 }
500 
501 
502 #endif /* ADRENO_PM4_XML */
503