1 #ifndef ADRENO_PM4_XML 2 #define ADRENO_PM4_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44) 12 - /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44) 13 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44) 14 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44) 15 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57) 16 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44) 17 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44) 18 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02) 19 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19) 20 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08) 21 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44) 22 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36) 23 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13) 24 25 Copyright (C) 2013-2021 by the following authors: 26 - Rob Clark <robdclark@gmail.com> (robclark) 27 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) 28 29 Permission is hereby granted, free of charge, to any person obtaining 30 a copy of this software and associated documentation files (the 31 "Software"), to deal in the Software without restriction, including 32 without limitation the rights to use, copy, modify, merge, publish, 33 distribute, sublicense, and/or sell copies of the Software, and to 34 permit persons to whom the Software is furnished to do so, subject to 35 the following conditions: 36 37 The above copyright notice and this permission notice (including the 38 next paragraph) shall be included in all copies or substantial 39 portions of the Software. 40 41 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 42 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 43 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 44 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 45 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 46 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 47 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 48 */ 49 50 51 enum vgt_event_type { 52 VS_DEALLOC = 0, 53 PS_DEALLOC = 1, 54 VS_DONE_TS = 2, 55 PS_DONE_TS = 3, 56 CACHE_FLUSH_TS = 4, 57 CONTEXT_DONE = 5, 58 CACHE_FLUSH = 6, 59 VIZQUERY_START = 7, 60 HLSQ_FLUSH = 7, 61 VIZQUERY_END = 8, 62 SC_WAIT_WC = 9, 63 WRITE_PRIMITIVE_COUNTS = 9, 64 START_PRIMITIVE_CTRS = 11, 65 STOP_PRIMITIVE_CTRS = 12, 66 RST_PIX_CNT = 13, 67 RST_VTX_CNT = 14, 68 TILE_FLUSH = 15, 69 STAT_EVENT = 16, 70 CACHE_FLUSH_AND_INV_TS_EVENT = 20, 71 ZPASS_DONE = 21, 72 CACHE_FLUSH_AND_INV_EVENT = 22, 73 RB_DONE_TS = 22, 74 PERFCOUNTER_START = 23, 75 PERFCOUNTER_STOP = 24, 76 VS_FETCH_DONE = 27, 77 FACENESS_FLUSH = 28, 78 WT_DONE_TS = 8, 79 FLUSH_SO_0 = 17, 80 FLUSH_SO_1 = 18, 81 FLUSH_SO_2 = 19, 82 FLUSH_SO_3 = 20, 83 PC_CCU_INVALIDATE_DEPTH = 24, 84 PC_CCU_INVALIDATE_COLOR = 25, 85 PC_CCU_RESOLVE_TS = 26, 86 PC_CCU_FLUSH_DEPTH_TS = 28, 87 PC_CCU_FLUSH_COLOR_TS = 29, 88 BLIT = 30, 89 UNK_25 = 37, 90 LRZ_FLUSH = 38, 91 BLIT_OP_FILL_2D = 39, 92 BLIT_OP_COPY_2D = 40, 93 BLIT_OP_SCALE_2D = 42, 94 CONTEXT_DONE_2D = 43, 95 UNK_2C = 44, 96 UNK_2D = 45, 97 CACHE_INVALIDATE = 49, 98 }; 99 100 enum pc_di_primtype { 101 DI_PT_NONE = 0, 102 DI_PT_POINTLIST_PSIZE = 1, 103 DI_PT_LINELIST = 2, 104 DI_PT_LINESTRIP = 3, 105 DI_PT_TRILIST = 4, 106 DI_PT_TRIFAN = 5, 107 DI_PT_TRISTRIP = 6, 108 DI_PT_LINELOOP = 7, 109 DI_PT_RECTLIST = 8, 110 DI_PT_POINTLIST = 9, 111 DI_PT_LINE_ADJ = 10, 112 DI_PT_LINESTRIP_ADJ = 11, 113 DI_PT_TRI_ADJ = 12, 114 DI_PT_TRISTRIP_ADJ = 13, 115 DI_PT_PATCHES0 = 31, 116 DI_PT_PATCHES1 = 32, 117 DI_PT_PATCHES2 = 33, 118 DI_PT_PATCHES3 = 34, 119 DI_PT_PATCHES4 = 35, 120 DI_PT_PATCHES5 = 36, 121 DI_PT_PATCHES6 = 37, 122 DI_PT_PATCHES7 = 38, 123 DI_PT_PATCHES8 = 39, 124 DI_PT_PATCHES9 = 40, 125 DI_PT_PATCHES10 = 41, 126 DI_PT_PATCHES11 = 42, 127 DI_PT_PATCHES12 = 43, 128 DI_PT_PATCHES13 = 44, 129 DI_PT_PATCHES14 = 45, 130 DI_PT_PATCHES15 = 46, 131 DI_PT_PATCHES16 = 47, 132 DI_PT_PATCHES17 = 48, 133 DI_PT_PATCHES18 = 49, 134 DI_PT_PATCHES19 = 50, 135 DI_PT_PATCHES20 = 51, 136 DI_PT_PATCHES21 = 52, 137 DI_PT_PATCHES22 = 53, 138 DI_PT_PATCHES23 = 54, 139 DI_PT_PATCHES24 = 55, 140 DI_PT_PATCHES25 = 56, 141 DI_PT_PATCHES26 = 57, 142 DI_PT_PATCHES27 = 58, 143 DI_PT_PATCHES28 = 59, 144 DI_PT_PATCHES29 = 60, 145 DI_PT_PATCHES30 = 61, 146 DI_PT_PATCHES31 = 62, 147 }; 148 149 enum pc_di_src_sel { 150 DI_SRC_SEL_DMA = 0, 151 DI_SRC_SEL_IMMEDIATE = 1, 152 DI_SRC_SEL_AUTO_INDEX = 2, 153 DI_SRC_SEL_AUTO_XFB = 3, 154 }; 155 156 enum pc_di_face_cull_sel { 157 DI_FACE_CULL_NONE = 0, 158 DI_FACE_CULL_FETCH = 1, 159 DI_FACE_BACKFACE_CULL = 2, 160 DI_FACE_FRONTFACE_CULL = 3, 161 }; 162 163 enum pc_di_index_size { 164 INDEX_SIZE_IGN = 0, 165 INDEX_SIZE_16_BIT = 0, 166 INDEX_SIZE_32_BIT = 1, 167 INDEX_SIZE_8_BIT = 2, 168 INDEX_SIZE_INVALID = 0, 169 }; 170 171 enum pc_di_vis_cull_mode { 172 IGNORE_VISIBILITY = 0, 173 USE_VISIBILITY = 1, 174 }; 175 176 enum adreno_pm4_packet_type { 177 CP_TYPE0_PKT = 0, 178 CP_TYPE1_PKT = 0x40000000, 179 CP_TYPE2_PKT = 0x80000000, 180 CP_TYPE3_PKT = 0xc0000000, 181 CP_TYPE4_PKT = 0x40000000, 182 CP_TYPE7_PKT = 0x70000000, 183 }; 184 185 enum adreno_pm4_type3_packets { 186 CP_ME_INIT = 72, 187 CP_NOP = 16, 188 CP_PREEMPT_ENABLE = 28, 189 CP_PREEMPT_TOKEN = 30, 190 CP_INDIRECT_BUFFER = 63, 191 CP_INDIRECT_BUFFER_CHAIN = 87, 192 CP_INDIRECT_BUFFER_PFD = 55, 193 CP_WAIT_FOR_IDLE = 38, 194 CP_WAIT_REG_MEM = 60, 195 CP_WAIT_REG_EQ = 82, 196 CP_WAIT_REG_GTE = 83, 197 CP_WAIT_UNTIL_READ = 92, 198 CP_WAIT_IB_PFD_COMPLETE = 93, 199 CP_REG_RMW = 33, 200 CP_SET_BIN_DATA = 47, 201 CP_SET_BIN_DATA5 = 47, 202 CP_REG_TO_MEM = 62, 203 CP_MEM_WRITE = 61, 204 CP_MEM_WRITE_CNTR = 79, 205 CP_COND_EXEC = 68, 206 CP_COND_WRITE = 69, 207 CP_COND_WRITE5 = 69, 208 CP_EVENT_WRITE = 70, 209 CP_EVENT_WRITE_SHD = 88, 210 CP_EVENT_WRITE_CFL = 89, 211 CP_EVENT_WRITE_ZPD = 91, 212 CP_RUN_OPENCL = 49, 213 CP_DRAW_INDX = 34, 214 CP_DRAW_INDX_2 = 54, 215 CP_DRAW_INDX_BIN = 52, 216 CP_DRAW_INDX_2_BIN = 53, 217 CP_VIZ_QUERY = 35, 218 CP_SET_STATE = 37, 219 CP_SET_CONSTANT = 45, 220 CP_IM_LOAD = 39, 221 CP_IM_LOAD_IMMEDIATE = 43, 222 CP_LOAD_CONSTANT_CONTEXT = 46, 223 CP_INVALIDATE_STATE = 59, 224 CP_SET_SHADER_BASES = 74, 225 CP_SET_BIN_MASK = 80, 226 CP_SET_BIN_SELECT = 81, 227 CP_CONTEXT_UPDATE = 94, 228 CP_INTERRUPT = 64, 229 CP_IM_STORE = 44, 230 CP_SET_DRAW_INIT_FLAGS = 75, 231 CP_SET_PROTECTED_MODE = 95, 232 CP_BOOTSTRAP_UCODE = 111, 233 CP_LOAD_STATE = 48, 234 CP_LOAD_STATE4 = 48, 235 CP_COND_INDIRECT_BUFFER_PFE = 58, 236 CP_COND_INDIRECT_BUFFER_PFD = 50, 237 CP_INDIRECT_BUFFER_PFE = 63, 238 CP_SET_BIN = 76, 239 CP_TEST_TWO_MEMS = 113, 240 CP_REG_WR_NO_CTXT = 120, 241 CP_RECORD_PFP_TIMESTAMP = 17, 242 CP_SET_SECURE_MODE = 102, 243 CP_WAIT_FOR_ME = 19, 244 CP_SET_DRAW_STATE = 67, 245 CP_DRAW_INDX_OFFSET = 56, 246 CP_DRAW_INDIRECT = 40, 247 CP_DRAW_INDX_INDIRECT = 41, 248 CP_DRAW_INDIRECT_MULTI = 42, 249 CP_DRAW_AUTO = 36, 250 CP_DRAW_PRED_ENABLE_GLOBAL = 25, 251 CP_DRAW_PRED_ENABLE_LOCAL = 26, 252 CP_DRAW_PRED_SET = 78, 253 CP_WIDE_REG_WRITE = 116, 254 CP_SCRATCH_TO_REG = 77, 255 CP_REG_TO_SCRATCH = 74, 256 CP_WAIT_MEM_WRITES = 18, 257 CP_COND_REG_EXEC = 71, 258 CP_MEM_TO_REG = 66, 259 CP_EXEC_CS_INDIRECT = 65, 260 CP_EXEC_CS = 51, 261 CP_PERFCOUNTER_ACTION = 80, 262 CP_SMMU_TABLE_UPDATE = 83, 263 CP_SET_MARKER = 101, 264 CP_SET_PSEUDO_REG = 86, 265 CP_CONTEXT_REG_BUNCH = 92, 266 CP_YIELD_ENABLE = 28, 267 CP_SKIP_IB2_ENABLE_GLOBAL = 29, 268 CP_SKIP_IB2_ENABLE_LOCAL = 35, 269 CP_SET_SUBDRAW_SIZE = 53, 270 CP_WHERE_AM_I = 98, 271 CP_SET_VISIBILITY_OVERRIDE = 100, 272 CP_PREEMPT_ENABLE_GLOBAL = 105, 273 CP_PREEMPT_ENABLE_LOCAL = 106, 274 CP_CONTEXT_SWITCH_YIELD = 107, 275 CP_SET_RENDER_MODE = 108, 276 CP_COMPUTE_CHECKPOINT = 110, 277 CP_MEM_TO_MEM = 115, 278 CP_BLIT = 44, 279 CP_REG_TEST = 57, 280 CP_SET_MODE = 99, 281 CP_LOAD_STATE6_GEOM = 50, 282 CP_LOAD_STATE6_FRAG = 52, 283 CP_LOAD_STATE6 = 54, 284 IN_IB_PREFETCH_END = 23, 285 IN_SUBBLK_PREFETCH = 31, 286 IN_INSTR_PREFETCH = 32, 287 IN_INSTR_MATCH = 71, 288 IN_CONST_PREFETCH = 73, 289 IN_INCR_UPDT_STATE = 85, 290 IN_INCR_UPDT_CONST = 86, 291 IN_INCR_UPDT_INSTR = 87, 292 PKT4 = 4, 293 CP_SCRATCH_WRITE = 76, 294 CP_REG_TO_MEM_OFFSET_MEM = 116, 295 CP_REG_TO_MEM_OFFSET_REG = 114, 296 CP_WAIT_MEM_GTE = 20, 297 CP_WAIT_TWO_REGS = 112, 298 CP_MEMCPY = 117, 299 CP_SET_BIN_DATA5_OFFSET = 46, 300 CP_SET_CTXSWITCH_IB = 85, 301 CP_REG_WRITE = 109, 302 }; 303 304 enum adreno_state_block { 305 SB_VERT_TEX = 0, 306 SB_VERT_MIPADDR = 1, 307 SB_FRAG_TEX = 2, 308 SB_FRAG_MIPADDR = 3, 309 SB_VERT_SHADER = 4, 310 SB_GEOM_SHADER = 5, 311 SB_FRAG_SHADER = 6, 312 SB_COMPUTE_SHADER = 7, 313 }; 314 315 enum adreno_state_type { 316 ST_SHADER = 0, 317 ST_CONSTANTS = 1, 318 }; 319 320 enum adreno_state_src { 321 SS_DIRECT = 0, 322 SS_INVALID_ALL_IC = 2, 323 SS_INVALID_PART_IC = 3, 324 SS_INDIRECT = 4, 325 SS_INDIRECT_TCM = 5, 326 SS_INDIRECT_STM = 6, 327 }; 328 329 enum a4xx_state_block { 330 SB4_VS_TEX = 0, 331 SB4_HS_TEX = 1, 332 SB4_DS_TEX = 2, 333 SB4_GS_TEX = 3, 334 SB4_FS_TEX = 4, 335 SB4_CS_TEX = 5, 336 SB4_VS_SHADER = 8, 337 SB4_HS_SHADER = 9, 338 SB4_DS_SHADER = 10, 339 SB4_GS_SHADER = 11, 340 SB4_FS_SHADER = 12, 341 SB4_CS_SHADER = 13, 342 SB4_SSBO = 14, 343 SB4_CS_SSBO = 15, 344 }; 345 346 enum a4xx_state_type { 347 ST4_SHADER = 0, 348 ST4_CONSTANTS = 1, 349 ST4_UBO = 2, 350 }; 351 352 enum a4xx_state_src { 353 SS4_DIRECT = 0, 354 SS4_INDIRECT = 2, 355 }; 356 357 enum a6xx_state_block { 358 SB6_VS_TEX = 0, 359 SB6_HS_TEX = 1, 360 SB6_DS_TEX = 2, 361 SB6_GS_TEX = 3, 362 SB6_FS_TEX = 4, 363 SB6_CS_TEX = 5, 364 SB6_VS_SHADER = 8, 365 SB6_HS_SHADER = 9, 366 SB6_DS_SHADER = 10, 367 SB6_GS_SHADER = 11, 368 SB6_FS_SHADER = 12, 369 SB6_CS_SHADER = 13, 370 SB6_IBO = 14, 371 SB6_CS_IBO = 15, 372 }; 373 374 enum a6xx_state_type { 375 ST6_SHADER = 0, 376 ST6_CONSTANTS = 1, 377 ST6_UBO = 2, 378 ST6_IBO = 3, 379 }; 380 381 enum a6xx_state_src { 382 SS6_DIRECT = 0, 383 SS6_BINDLESS = 1, 384 SS6_INDIRECT = 2, 385 SS6_UBO = 3, 386 }; 387 388 enum a4xx_index_size { 389 INDEX4_SIZE_8_BIT = 0, 390 INDEX4_SIZE_16_BIT = 1, 391 INDEX4_SIZE_32_BIT = 2, 392 }; 393 394 enum a6xx_patch_type { 395 TESS_QUADS = 0, 396 TESS_TRIANGLES = 1, 397 TESS_ISOLINES = 2, 398 }; 399 400 enum a6xx_draw_indirect_opcode { 401 INDIRECT_OP_NORMAL = 2, 402 INDIRECT_OP_INDEXED = 4, 403 INDIRECT_OP_INDIRECT_COUNT = 6, 404 INDIRECT_OP_INDIRECT_COUNT_INDEXED = 7, 405 }; 406 407 enum cp_draw_pred_src { 408 PRED_SRC_MEM = 5, 409 }; 410 411 enum cp_draw_pred_test { 412 NE_0_PASS = 0, 413 EQ_0_PASS = 1, 414 }; 415 416 enum cp_cond_function { 417 WRITE_ALWAYS = 0, 418 WRITE_LT = 1, 419 WRITE_LE = 2, 420 WRITE_EQ = 3, 421 WRITE_NE = 4, 422 WRITE_GE = 5, 423 WRITE_GT = 6, 424 }; 425 426 enum render_mode_cmd { 427 BYPASS = 1, 428 BINNING = 2, 429 GMEM = 3, 430 BLIT2D = 5, 431 BLIT2DSCALE = 7, 432 END2D = 8, 433 }; 434 435 enum cp_blit_cmd { 436 BLIT_OP_FILL = 0, 437 BLIT_OP_COPY = 1, 438 BLIT_OP_SCALE = 3, 439 }; 440 441 enum a6xx_render_mode { 442 RM6_BYPASS = 1, 443 RM6_BINNING = 2, 444 RM6_GMEM = 4, 445 RM6_ENDVIS = 5, 446 RM6_RESOLVE = 6, 447 RM6_YIELD = 7, 448 RM6_COMPUTE = 8, 449 RM6_BLIT2DSCALE = 12, 450 RM6_IB1LIST_START = 13, 451 RM6_IB1LIST_END = 14, 452 RM6_IFPC_ENABLE = 256, 453 RM6_IFPC_DISABLE = 257, 454 }; 455 456 enum pseudo_reg { 457 SMMU_INFO = 0, 458 NON_SECURE_SAVE_ADDR = 1, 459 SECURE_SAVE_ADDR = 2, 460 NON_PRIV_SAVE_ADDR = 3, 461 COUNTER = 4, 462 }; 463 464 enum compare_mode { 465 PRED_TEST = 1, 466 REG_COMPARE = 2, 467 RENDER_MODE = 3, 468 }; 469 470 enum ctxswitch_ib { 471 RESTORE_IB = 0, 472 YIELD_RESTORE_IB = 1, 473 SAVE_IB = 2, 474 RB_SAVE_IB = 3, 475 }; 476 477 enum reg_tracker { 478 TRACK_CNTL_REG = 1, 479 TRACK_RENDER_CNTL = 2, 480 UNK_EVENT_WRITE = 4, 481 }; 482 483 #define REG_CP_LOAD_STATE_0 0x00000000 484 #define CP_LOAD_STATE_0_DST_OFF__MASK 0x0000ffff 485 #define CP_LOAD_STATE_0_DST_OFF__SHIFT 0 486 static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val) 487 { 488 return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK; 489 } 490 #define CP_LOAD_STATE_0_STATE_SRC__MASK 0x00070000 491 #define CP_LOAD_STATE_0_STATE_SRC__SHIFT 16 492 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val) 493 { 494 return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK; 495 } 496 #define CP_LOAD_STATE_0_STATE_BLOCK__MASK 0x00380000 497 #define CP_LOAD_STATE_0_STATE_BLOCK__SHIFT 19 498 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val) 499 { 500 return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK; 501 } 502 #define CP_LOAD_STATE_0_NUM_UNIT__MASK 0xffc00000 503 #define CP_LOAD_STATE_0_NUM_UNIT__SHIFT 22 504 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val) 505 { 506 return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK; 507 } 508 509 #define REG_CP_LOAD_STATE_1 0x00000001 510 #define CP_LOAD_STATE_1_STATE_TYPE__MASK 0x00000003 511 #define CP_LOAD_STATE_1_STATE_TYPE__SHIFT 0 512 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val) 513 { 514 return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK; 515 } 516 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK 0xfffffffc 517 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT 2 518 static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val) 519 { 520 return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK; 521 } 522 523 #define REG_CP_LOAD_STATE4_0 0x00000000 524 #define CP_LOAD_STATE4_0_DST_OFF__MASK 0x00003fff 525 #define CP_LOAD_STATE4_0_DST_OFF__SHIFT 0 526 static inline uint32_t CP_LOAD_STATE4_0_DST_OFF(uint32_t val) 527 { 528 return ((val) << CP_LOAD_STATE4_0_DST_OFF__SHIFT) & CP_LOAD_STATE4_0_DST_OFF__MASK; 529 } 530 #define CP_LOAD_STATE4_0_STATE_SRC__MASK 0x00030000 531 #define CP_LOAD_STATE4_0_STATE_SRC__SHIFT 16 532 static inline uint32_t CP_LOAD_STATE4_0_STATE_SRC(enum a4xx_state_src val) 533 { 534 return ((val) << CP_LOAD_STATE4_0_STATE_SRC__SHIFT) & CP_LOAD_STATE4_0_STATE_SRC__MASK; 535 } 536 #define CP_LOAD_STATE4_0_STATE_BLOCK__MASK 0x003c0000 537 #define CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT 18 538 static inline uint32_t CP_LOAD_STATE4_0_STATE_BLOCK(enum a4xx_state_block val) 539 { 540 return ((val) << CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE4_0_STATE_BLOCK__MASK; 541 } 542 #define CP_LOAD_STATE4_0_NUM_UNIT__MASK 0xffc00000 543 #define CP_LOAD_STATE4_0_NUM_UNIT__SHIFT 22 544 static inline uint32_t CP_LOAD_STATE4_0_NUM_UNIT(uint32_t val) 545 { 546 return ((val) << CP_LOAD_STATE4_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE4_0_NUM_UNIT__MASK; 547 } 548 549 #define REG_CP_LOAD_STATE4_1 0x00000001 550 #define CP_LOAD_STATE4_1_STATE_TYPE__MASK 0x00000003 551 #define CP_LOAD_STATE4_1_STATE_TYPE__SHIFT 0 552 static inline uint32_t CP_LOAD_STATE4_1_STATE_TYPE(enum a4xx_state_type val) 553 { 554 return ((val) << CP_LOAD_STATE4_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE4_1_STATE_TYPE__MASK; 555 } 556 #define CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK 0xfffffffc 557 #define CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT 2 558 static inline uint32_t CP_LOAD_STATE4_1_EXT_SRC_ADDR(uint32_t val) 559 { 560 return ((val >> 2) << CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK; 561 } 562 563 #define REG_CP_LOAD_STATE4_2 0x00000002 564 #define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK 0xffffffff 565 #define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT 0 566 static inline uint32_t CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(uint32_t val) 567 { 568 return ((val) << CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK; 569 } 570 571 #define REG_CP_LOAD_STATE6_0 0x00000000 572 #define CP_LOAD_STATE6_0_DST_OFF__MASK 0x00003fff 573 #define CP_LOAD_STATE6_0_DST_OFF__SHIFT 0 574 static inline uint32_t CP_LOAD_STATE6_0_DST_OFF(uint32_t val) 575 { 576 return ((val) << CP_LOAD_STATE6_0_DST_OFF__SHIFT) & CP_LOAD_STATE6_0_DST_OFF__MASK; 577 } 578 #define CP_LOAD_STATE6_0_STATE_TYPE__MASK 0x0000c000 579 #define CP_LOAD_STATE6_0_STATE_TYPE__SHIFT 14 580 static inline uint32_t CP_LOAD_STATE6_0_STATE_TYPE(enum a6xx_state_type val) 581 { 582 return ((val) << CP_LOAD_STATE6_0_STATE_TYPE__SHIFT) & CP_LOAD_STATE6_0_STATE_TYPE__MASK; 583 } 584 #define CP_LOAD_STATE6_0_STATE_SRC__MASK 0x00030000 585 #define CP_LOAD_STATE6_0_STATE_SRC__SHIFT 16 586 static inline uint32_t CP_LOAD_STATE6_0_STATE_SRC(enum a6xx_state_src val) 587 { 588 return ((val) << CP_LOAD_STATE6_0_STATE_SRC__SHIFT) & CP_LOAD_STATE6_0_STATE_SRC__MASK; 589 } 590 #define CP_LOAD_STATE6_0_STATE_BLOCK__MASK 0x003c0000 591 #define CP_LOAD_STATE6_0_STATE_BLOCK__SHIFT 18 592 static inline uint32_t CP_LOAD_STATE6_0_STATE_BLOCK(enum a6xx_state_block val) 593 { 594 return ((val) << CP_LOAD_STATE6_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE6_0_STATE_BLOCK__MASK; 595 } 596 #define CP_LOAD_STATE6_0_NUM_UNIT__MASK 0xffc00000 597 #define CP_LOAD_STATE6_0_NUM_UNIT__SHIFT 22 598 static inline uint32_t CP_LOAD_STATE6_0_NUM_UNIT(uint32_t val) 599 { 600 return ((val) << CP_LOAD_STATE6_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE6_0_NUM_UNIT__MASK; 601 } 602 603 #define REG_CP_LOAD_STATE6_1 0x00000001 604 #define CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK 0xfffffffc 605 #define CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT 2 606 static inline uint32_t CP_LOAD_STATE6_1_EXT_SRC_ADDR(uint32_t val) 607 { 608 return ((val >> 2) << CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK; 609 } 610 611 #define REG_CP_LOAD_STATE6_2 0x00000002 612 #define CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK 0xffffffff 613 #define CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT 0 614 static inline uint32_t CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(uint32_t val) 615 { 616 return ((val) << CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK; 617 } 618 619 #define REG_CP_LOAD_STATE6_EXT_SRC_ADDR 0x00000001 620 621 #define REG_CP_DRAW_INDX_0 0x00000000 622 #define CP_DRAW_INDX_0_VIZ_QUERY__MASK 0xffffffff 623 #define CP_DRAW_INDX_0_VIZ_QUERY__SHIFT 0 624 static inline uint32_t CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val) 625 { 626 return ((val) << CP_DRAW_INDX_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_0_VIZ_QUERY__MASK; 627 } 628 629 #define REG_CP_DRAW_INDX_1 0x00000001 630 #define CP_DRAW_INDX_1_PRIM_TYPE__MASK 0x0000003f 631 #define CP_DRAW_INDX_1_PRIM_TYPE__SHIFT 0 632 static inline uint32_t CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val) 633 { 634 return ((val) << CP_DRAW_INDX_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_1_PRIM_TYPE__MASK; 635 } 636 #define CP_DRAW_INDX_1_SOURCE_SELECT__MASK 0x000000c0 637 #define CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT 6 638 static inline uint32_t CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val) 639 { 640 return ((val) << CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_1_SOURCE_SELECT__MASK; 641 } 642 #define CP_DRAW_INDX_1_VIS_CULL__MASK 0x00000600 643 #define CP_DRAW_INDX_1_VIS_CULL__SHIFT 9 644 static inline uint32_t CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val) 645 { 646 return ((val) << CP_DRAW_INDX_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_1_VIS_CULL__MASK; 647 } 648 #define CP_DRAW_INDX_1_INDEX_SIZE__MASK 0x00000800 649 #define CP_DRAW_INDX_1_INDEX_SIZE__SHIFT 11 650 static inline uint32_t CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val) 651 { 652 return ((val) << CP_DRAW_INDX_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_1_INDEX_SIZE__MASK; 653 } 654 #define CP_DRAW_INDX_1_NOT_EOP 0x00001000 655 #define CP_DRAW_INDX_1_SMALL_INDEX 0x00002000 656 #define CP_DRAW_INDX_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000 657 #define CP_DRAW_INDX_1_NUM_INSTANCES__MASK 0xff000000 658 #define CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT 24 659 static inline uint32_t CP_DRAW_INDX_1_NUM_INSTANCES(uint32_t val) 660 { 661 return ((val) << CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_1_NUM_INSTANCES__MASK; 662 } 663 664 #define REG_CP_DRAW_INDX_2 0x00000002 665 #define CP_DRAW_INDX_2_NUM_INDICES__MASK 0xffffffff 666 #define CP_DRAW_INDX_2_NUM_INDICES__SHIFT 0 667 static inline uint32_t CP_DRAW_INDX_2_NUM_INDICES(uint32_t val) 668 { 669 return ((val) << CP_DRAW_INDX_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_NUM_INDICES__MASK; 670 } 671 672 #define REG_CP_DRAW_INDX_3 0x00000003 673 #define CP_DRAW_INDX_3_INDX_BASE__MASK 0xffffffff 674 #define CP_DRAW_INDX_3_INDX_BASE__SHIFT 0 675 static inline uint32_t CP_DRAW_INDX_3_INDX_BASE(uint32_t val) 676 { 677 return ((val) << CP_DRAW_INDX_3_INDX_BASE__SHIFT) & CP_DRAW_INDX_3_INDX_BASE__MASK; 678 } 679 680 #define REG_CP_DRAW_INDX_4 0x00000004 681 #define CP_DRAW_INDX_4_INDX_SIZE__MASK 0xffffffff 682 #define CP_DRAW_INDX_4_INDX_SIZE__SHIFT 0 683 static inline uint32_t CP_DRAW_INDX_4_INDX_SIZE(uint32_t val) 684 { 685 return ((val) << CP_DRAW_INDX_4_INDX_SIZE__SHIFT) & CP_DRAW_INDX_4_INDX_SIZE__MASK; 686 } 687 688 #define REG_CP_DRAW_INDX_2_0 0x00000000 689 #define CP_DRAW_INDX_2_0_VIZ_QUERY__MASK 0xffffffff 690 #define CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT 0 691 static inline uint32_t CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val) 692 { 693 return ((val) << CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_2_0_VIZ_QUERY__MASK; 694 } 695 696 #define REG_CP_DRAW_INDX_2_1 0x00000001 697 #define CP_DRAW_INDX_2_1_PRIM_TYPE__MASK 0x0000003f 698 #define CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT 0 699 static inline uint32_t CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val) 700 { 701 return ((val) << CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_2_1_PRIM_TYPE__MASK; 702 } 703 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK 0x000000c0 704 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT 6 705 static inline uint32_t CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val) 706 { 707 return ((val) << CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK; 708 } 709 #define CP_DRAW_INDX_2_1_VIS_CULL__MASK 0x00000600 710 #define CP_DRAW_INDX_2_1_VIS_CULL__SHIFT 9 711 static inline uint32_t CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val) 712 { 713 return ((val) << CP_DRAW_INDX_2_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_2_1_VIS_CULL__MASK; 714 } 715 #define CP_DRAW_INDX_2_1_INDEX_SIZE__MASK 0x00000800 716 #define CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT 11 717 static inline uint32_t CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val) 718 { 719 return ((val) << CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_2_1_INDEX_SIZE__MASK; 720 } 721 #define CP_DRAW_INDX_2_1_NOT_EOP 0x00001000 722 #define CP_DRAW_INDX_2_1_SMALL_INDEX 0x00002000 723 #define CP_DRAW_INDX_2_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000 724 #define CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK 0xff000000 725 #define CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT 24 726 static inline uint32_t CP_DRAW_INDX_2_1_NUM_INSTANCES(uint32_t val) 727 { 728 return ((val) << CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK; 729 } 730 731 #define REG_CP_DRAW_INDX_2_2 0x00000002 732 #define CP_DRAW_INDX_2_2_NUM_INDICES__MASK 0xffffffff 733 #define CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT 0 734 static inline uint32_t CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val) 735 { 736 return ((val) << CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_2_NUM_INDICES__MASK; 737 } 738 739 #define REG_CP_DRAW_INDX_OFFSET_0 0x00000000 740 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK 0x0000003f 741 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT 0 742 static inline uint32_t CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val) 743 { 744 return ((val) << CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK; 745 } 746 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK 0x000000c0 747 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT 6 748 static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val) 749 { 750 return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK; 751 } 752 #define CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK 0x00000300 753 #define CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT 8 754 static inline uint32_t CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val) 755 { 756 return ((val) << CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT) & CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK; 757 } 758 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK 0x00000c00 759 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT 10 760 static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val) 761 { 762 return ((val) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK; 763 } 764 #define CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__MASK 0x00003000 765 #define CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__SHIFT 12 766 static inline uint32_t CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(enum a6xx_patch_type val) 767 { 768 return ((val) << CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__MASK; 769 } 770 #define CP_DRAW_INDX_OFFSET_0_GS_ENABLE 0x00010000 771 #define CP_DRAW_INDX_OFFSET_0_TESS_ENABLE 0x00020000 772 773 #define REG_CP_DRAW_INDX_OFFSET_1 0x00000001 774 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK 0xffffffff 775 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT 0 776 static inline uint32_t CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES(uint32_t val) 777 { 778 return ((val) << CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK; 779 } 780 781 #define REG_CP_DRAW_INDX_OFFSET_2 0x00000002 782 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK 0xffffffff 783 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT 0 784 static inline uint32_t CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val) 785 { 786 return ((val) << CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK; 787 } 788 789 #define REG_CP_DRAW_INDX_OFFSET_3 0x00000003 790 #define CP_DRAW_INDX_OFFSET_3_FIRST_INDX__MASK 0xffffffff 791 #define CP_DRAW_INDX_OFFSET_3_FIRST_INDX__SHIFT 0 792 static inline uint32_t CP_DRAW_INDX_OFFSET_3_FIRST_INDX(uint32_t val) 793 { 794 return ((val) << CP_DRAW_INDX_OFFSET_3_FIRST_INDX__SHIFT) & CP_DRAW_INDX_OFFSET_3_FIRST_INDX__MASK; 795 } 796 797 798 #define REG_CP_DRAW_INDX_OFFSET_4 0x00000004 799 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__MASK 0xffffffff 800 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__SHIFT 0 801 static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO(uint32_t val) 802 { 803 return ((val) << CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__MASK; 804 } 805 806 #define REG_CP_DRAW_INDX_OFFSET_5 0x00000005 807 #define CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__MASK 0xffffffff 808 #define CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__SHIFT 0 809 static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI(uint32_t val) 810 { 811 return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__MASK; 812 } 813 814 #define REG_CP_DRAW_INDX_OFFSET_INDX_BASE 0x00000004 815 816 #define REG_CP_DRAW_INDX_OFFSET_6 0x00000006 817 #define CP_DRAW_INDX_OFFSET_6_MAX_INDICES__MASK 0xffffffff 818 #define CP_DRAW_INDX_OFFSET_6_MAX_INDICES__SHIFT 0 819 static inline uint32_t CP_DRAW_INDX_OFFSET_6_MAX_INDICES(uint32_t val) 820 { 821 return ((val) << CP_DRAW_INDX_OFFSET_6_MAX_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_6_MAX_INDICES__MASK; 822 } 823 824 #define REG_CP_DRAW_INDX_OFFSET_4 0x00000004 825 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK 0xffffffff 826 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT 0 827 static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE(uint32_t val) 828 { 829 return ((val) << CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK; 830 } 831 832 #define REG_CP_DRAW_INDX_OFFSET_5 0x00000005 833 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK 0xffffffff 834 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT 0 835 static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_SIZE(uint32_t val) 836 { 837 return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK; 838 } 839 840 #define REG_A4XX_CP_DRAW_INDIRECT_0 0x00000000 841 #define A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK 0x0000003f 842 #define A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT 0 843 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val) 844 { 845 return ((val) << A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK; 846 } 847 #define A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK 0x000000c0 848 #define A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT 6 849 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val) 850 { 851 return ((val) << A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK; 852 } 853 #define A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK 0x00000300 854 #define A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT 8 855 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val) 856 { 857 return ((val) << A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK; 858 } 859 #define A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK 0x00000c00 860 #define A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT 10 861 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val) 862 { 863 return ((val) << A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK; 864 } 865 #define A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__MASK 0x00003000 866 #define A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__SHIFT 12 867 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE(enum a6xx_patch_type val) 868 { 869 return ((val) << A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__MASK; 870 } 871 #define A4XX_CP_DRAW_INDIRECT_0_GS_ENABLE 0x00010000 872 #define A4XX_CP_DRAW_INDIRECT_0_TESS_ENABLE 0x00020000 873 874 875 #define REG_A4XX_CP_DRAW_INDIRECT_1 0x00000001 876 #define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK 0xffffffff 877 #define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT 0 878 static inline uint32_t A4XX_CP_DRAW_INDIRECT_1_INDIRECT(uint32_t val) 879 { 880 return ((val) << A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK; 881 } 882 883 884 #define REG_A5XX_CP_DRAW_INDIRECT_1 0x00000001 885 #define A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__MASK 0xffffffff 886 #define A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__SHIFT 0 887 static inline uint32_t A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO(uint32_t val) 888 { 889 return ((val) << A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__SHIFT) & A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__MASK; 890 } 891 892 #define REG_A5XX_CP_DRAW_INDIRECT_2 0x00000002 893 #define A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK 0xffffffff 894 #define A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT 0 895 static inline uint32_t A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI(uint32_t val) 896 { 897 return ((val) << A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK; 898 } 899 900 #define REG_A5XX_CP_DRAW_INDIRECT_INDIRECT 0x00000001 901 902 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_0 0x00000000 903 #define A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK 0x0000003f 904 #define A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT 0 905 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val) 906 { 907 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK; 908 } 909 #define A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK 0x000000c0 910 #define A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT 6 911 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val) 912 { 913 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK; 914 } 915 #define A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK 0x00000300 916 #define A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT 8 917 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val) 918 { 919 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK; 920 } 921 #define A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK 0x00000c00 922 #define A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT 10 923 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val) 924 { 925 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK; 926 } 927 #define A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__MASK 0x00003000 928 #define A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__SHIFT 12 929 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE(enum a6xx_patch_type val) 930 { 931 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__MASK; 932 } 933 #define A4XX_CP_DRAW_INDX_INDIRECT_0_GS_ENABLE 0x00010000 934 #define A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_ENABLE 0x00020000 935 936 937 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_1 0x00000001 938 #define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK 0xffffffff 939 #define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT 0 940 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE(uint32_t val) 941 { 942 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK; 943 } 944 945 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_2 0x00000002 946 #define A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK 0xffffffff 947 #define A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT 0 948 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE(uint32_t val) 949 { 950 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK; 951 } 952 953 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_3 0x00000003 954 #define A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK 0xffffffff 955 #define A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT 0 956 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT(uint32_t val) 957 { 958 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK; 959 } 960 961 962 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_1 0x00000001 963 #define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK 0xffffffff 964 #define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT 0 965 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO(uint32_t val) 966 { 967 return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK; 968 } 969 970 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_2 0x00000002 971 #define A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK 0xffffffff 972 #define A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT 0 973 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI(uint32_t val) 974 { 975 return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK; 976 } 977 978 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_INDX_BASE 0x00000001 979 980 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_3 0x00000003 981 #define A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK 0xffffffff 982 #define A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT 0 983 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(uint32_t val) 984 { 985 return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK; 986 } 987 988 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_4 0x00000004 989 #define A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK 0xffffffff 990 #define A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT 0 991 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO(uint32_t val) 992 { 993 return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK; 994 } 995 996 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_5 0x00000005 997 #define A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK 0xffffffff 998 #define A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT 0 999 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI(uint32_t val) 1000 { 1001 return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK; 1002 } 1003 1004 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_INDIRECT 0x00000004 1005 1006 #define REG_A6XX_CP_DRAW_INDIRECT_MULTI_0 0x00000000 1007 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__MASK 0x0000003f 1008 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__SHIFT 0 1009 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE(enum pc_di_primtype val) 1010 { 1011 return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__MASK; 1012 } 1013 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__MASK 0x000000c0 1014 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__SHIFT 6 1015 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT(enum pc_di_src_sel val) 1016 { 1017 return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__MASK; 1018 } 1019 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__MASK 0x00000300 1020 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__SHIFT 8 1021 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL(enum pc_di_vis_cull_mode val) 1022 { 1023 return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__MASK; 1024 } 1025 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__MASK 0x00000c00 1026 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__SHIFT 10 1027 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE(enum a4xx_index_size val) 1028 { 1029 return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__MASK; 1030 } 1031 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__MASK 0x00003000 1032 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__SHIFT 12 1033 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE(enum a6xx_patch_type val) 1034 { 1035 return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__MASK; 1036 } 1037 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_GS_ENABLE 0x00010000 1038 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_TESS_ENABLE 0x00020000 1039 1040 #define REG_A6XX_CP_DRAW_INDIRECT_MULTI_1 0x00000001 1041 #define A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__MASK 0x0000000f 1042 #define A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__SHIFT 0 1043 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(enum a6xx_draw_indirect_opcode val) 1044 { 1045 return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__MASK; 1046 } 1047 #define A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__MASK 0x003fff00 1048 #define A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__SHIFT 8 1049 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(uint32_t val) 1050 { 1051 return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__MASK; 1052 } 1053 1054 #define REG_A6XX_CP_DRAW_INDIRECT_MULTI_DRAW_COUNT 0x00000002 1055 1056 1057 #define REG_A6XX_CP_DRAW_INDIRECT_MULTI_INDIRECT 0x00000003 1058 1059 #define REG_A6XX_CP_DRAW_INDIRECT_MULTI_STRIDE 0x00000005 1060 1061 1062 #define REG_CP_DRAW_INDIRECT_MULTI_INDEX_INDEXED 0x00000003 1063 1064 #define REG_CP_DRAW_INDIRECT_MULTI_MAX_INDICES_INDEXED 0x00000005 1065 1066 #define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_INDEXED 0x00000006 1067 1068 #define REG_CP_DRAW_INDIRECT_MULTI_STRIDE_INDEXED 0x00000008 1069 1070 1071 #define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_INDIRECT 0x00000003 1072 1073 #define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT_INDIRECT 0x00000005 1074 1075 #define REG_CP_DRAW_INDIRECT_MULTI_STRIDE_INDIRECT 0x00000007 1076 1077 1078 #define REG_CP_DRAW_INDIRECT_MULTI_INDEX_INDIRECT_INDEXED 0x00000003 1079 1080 #define REG_CP_DRAW_INDIRECT_MULTI_MAX_INDICES_INDIRECT_INDEXED 0x00000005 1081 1082 #define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_INDIRECT_INDEXED 0x00000006 1083 1084 #define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT_INDIRECT_INDEXED 0x00000008 1085 1086 #define REG_CP_DRAW_INDIRECT_MULTI_STRIDE_INDIRECT_INDEXED 0x0000000a 1087 1088 #define REG_CP_DRAW_PRED_ENABLE_GLOBAL_0 0x00000000 1089 #define CP_DRAW_PRED_ENABLE_GLOBAL_0_ENABLE 0x00000001 1090 1091 #define REG_CP_DRAW_PRED_ENABLE_LOCAL_0 0x00000000 1092 #define CP_DRAW_PRED_ENABLE_LOCAL_0_ENABLE 0x00000001 1093 1094 #define REG_CP_DRAW_PRED_SET_0 0x00000000 1095 #define CP_DRAW_PRED_SET_0_SRC__MASK 0x000000f0 1096 #define CP_DRAW_PRED_SET_0_SRC__SHIFT 4 1097 static inline uint32_t CP_DRAW_PRED_SET_0_SRC(enum cp_draw_pred_src val) 1098 { 1099 return ((val) << CP_DRAW_PRED_SET_0_SRC__SHIFT) & CP_DRAW_PRED_SET_0_SRC__MASK; 1100 } 1101 #define CP_DRAW_PRED_SET_0_TEST__MASK 0x00000100 1102 #define CP_DRAW_PRED_SET_0_TEST__SHIFT 8 1103 static inline uint32_t CP_DRAW_PRED_SET_0_TEST(enum cp_draw_pred_test val) 1104 { 1105 return ((val) << CP_DRAW_PRED_SET_0_TEST__SHIFT) & CP_DRAW_PRED_SET_0_TEST__MASK; 1106 } 1107 1108 #define REG_CP_DRAW_PRED_SET_MEM_ADDR 0x00000001 1109 1110 static inline uint32_t REG_CP_SET_DRAW_STATE_(uint32_t i0) { return 0x00000000 + 0x3*i0; } 1111 1112 static inline uint32_t REG_CP_SET_DRAW_STATE__0(uint32_t i0) { return 0x00000000 + 0x3*i0; } 1113 #define CP_SET_DRAW_STATE__0_COUNT__MASK 0x0000ffff 1114 #define CP_SET_DRAW_STATE__0_COUNT__SHIFT 0 1115 static inline uint32_t CP_SET_DRAW_STATE__0_COUNT(uint32_t val) 1116 { 1117 return ((val) << CP_SET_DRAW_STATE__0_COUNT__SHIFT) & CP_SET_DRAW_STATE__0_COUNT__MASK; 1118 } 1119 #define CP_SET_DRAW_STATE__0_DIRTY 0x00010000 1120 #define CP_SET_DRAW_STATE__0_DISABLE 0x00020000 1121 #define CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS 0x00040000 1122 #define CP_SET_DRAW_STATE__0_LOAD_IMMED 0x00080000 1123 #define CP_SET_DRAW_STATE__0_BINNING 0x00100000 1124 #define CP_SET_DRAW_STATE__0_GMEM 0x00200000 1125 #define CP_SET_DRAW_STATE__0_SYSMEM 0x00400000 1126 #define CP_SET_DRAW_STATE__0_GROUP_ID__MASK 0x1f000000 1127 #define CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT 24 1128 static inline uint32_t CP_SET_DRAW_STATE__0_GROUP_ID(uint32_t val) 1129 { 1130 return ((val) << CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT) & CP_SET_DRAW_STATE__0_GROUP_ID__MASK; 1131 } 1132 1133 static inline uint32_t REG_CP_SET_DRAW_STATE__1(uint32_t i0) { return 0x00000001 + 0x3*i0; } 1134 #define CP_SET_DRAW_STATE__1_ADDR_LO__MASK 0xffffffff 1135 #define CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT 0 1136 static inline uint32_t CP_SET_DRAW_STATE__1_ADDR_LO(uint32_t val) 1137 { 1138 return ((val) << CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT) & CP_SET_DRAW_STATE__1_ADDR_LO__MASK; 1139 } 1140 1141 static inline uint32_t REG_CP_SET_DRAW_STATE__2(uint32_t i0) { return 0x00000002 + 0x3*i0; } 1142 #define CP_SET_DRAW_STATE__2_ADDR_HI__MASK 0xffffffff 1143 #define CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT 0 1144 static inline uint32_t CP_SET_DRAW_STATE__2_ADDR_HI(uint32_t val) 1145 { 1146 return ((val) << CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT) & CP_SET_DRAW_STATE__2_ADDR_HI__MASK; 1147 } 1148 1149 #define REG_CP_SET_BIN_0 0x00000000 1150 1151 #define REG_CP_SET_BIN_1 0x00000001 1152 #define CP_SET_BIN_1_X1__MASK 0x0000ffff 1153 #define CP_SET_BIN_1_X1__SHIFT 0 1154 static inline uint32_t CP_SET_BIN_1_X1(uint32_t val) 1155 { 1156 return ((val) << CP_SET_BIN_1_X1__SHIFT) & CP_SET_BIN_1_X1__MASK; 1157 } 1158 #define CP_SET_BIN_1_Y1__MASK 0xffff0000 1159 #define CP_SET_BIN_1_Y1__SHIFT 16 1160 static inline uint32_t CP_SET_BIN_1_Y1(uint32_t val) 1161 { 1162 return ((val) << CP_SET_BIN_1_Y1__SHIFT) & CP_SET_BIN_1_Y1__MASK; 1163 } 1164 1165 #define REG_CP_SET_BIN_2 0x00000002 1166 #define CP_SET_BIN_2_X2__MASK 0x0000ffff 1167 #define CP_SET_BIN_2_X2__SHIFT 0 1168 static inline uint32_t CP_SET_BIN_2_X2(uint32_t val) 1169 { 1170 return ((val) << CP_SET_BIN_2_X2__SHIFT) & CP_SET_BIN_2_X2__MASK; 1171 } 1172 #define CP_SET_BIN_2_Y2__MASK 0xffff0000 1173 #define CP_SET_BIN_2_Y2__SHIFT 16 1174 static inline uint32_t CP_SET_BIN_2_Y2(uint32_t val) 1175 { 1176 return ((val) << CP_SET_BIN_2_Y2__SHIFT) & CP_SET_BIN_2_Y2__MASK; 1177 } 1178 1179 #define REG_CP_SET_BIN_DATA_0 0x00000000 1180 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK 0xffffffff 1181 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT 0 1182 static inline uint32_t CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val) 1183 { 1184 return ((val) << CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT) & CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK; 1185 } 1186 1187 #define REG_CP_SET_BIN_DATA_1 0x00000001 1188 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK 0xffffffff 1189 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT 0 1190 static inline uint32_t CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val) 1191 { 1192 return ((val) << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK; 1193 } 1194 1195 #define REG_CP_SET_BIN_DATA5_0 0x00000000 1196 #define CP_SET_BIN_DATA5_0_VSC_SIZE__MASK 0x003f0000 1197 #define CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT 16 1198 static inline uint32_t CP_SET_BIN_DATA5_0_VSC_SIZE(uint32_t val) 1199 { 1200 return ((val) << CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT) & CP_SET_BIN_DATA5_0_VSC_SIZE__MASK; 1201 } 1202 #define CP_SET_BIN_DATA5_0_VSC_N__MASK 0x07c00000 1203 #define CP_SET_BIN_DATA5_0_VSC_N__SHIFT 22 1204 static inline uint32_t CP_SET_BIN_DATA5_0_VSC_N(uint32_t val) 1205 { 1206 return ((val) << CP_SET_BIN_DATA5_0_VSC_N__SHIFT) & CP_SET_BIN_DATA5_0_VSC_N__MASK; 1207 } 1208 1209 #define REG_CP_SET_BIN_DATA5_1 0x00000001 1210 #define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK 0xffffffff 1211 #define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT 0 1212 static inline uint32_t CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO(uint32_t val) 1213 { 1214 return ((val) << CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT) & CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK; 1215 } 1216 1217 #define REG_CP_SET_BIN_DATA5_2 0x00000002 1218 #define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK 0xffffffff 1219 #define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT 0 1220 static inline uint32_t CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI(uint32_t val) 1221 { 1222 return ((val) << CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT) & CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK; 1223 } 1224 1225 #define REG_CP_SET_BIN_DATA5_3 0x00000003 1226 #define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK 0xffffffff 1227 #define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT 0 1228 static inline uint32_t CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO(uint32_t val) 1229 { 1230 return ((val) << CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT) & CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK; 1231 } 1232 1233 #define REG_CP_SET_BIN_DATA5_4 0x00000004 1234 #define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK 0xffffffff 1235 #define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT 0 1236 static inline uint32_t CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI(uint32_t val) 1237 { 1238 return ((val) << CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT) & CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK; 1239 } 1240 1241 #define REG_CP_SET_BIN_DATA5_5 0x00000005 1242 #define CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__MASK 0xffffffff 1243 #define CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__SHIFT 0 1244 static inline uint32_t CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO(uint32_t val) 1245 { 1246 return ((val) << CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__SHIFT) & CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__MASK; 1247 } 1248 1249 #define REG_CP_SET_BIN_DATA5_6 0x00000006 1250 #define CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__MASK 0xffffffff 1251 #define CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__SHIFT 0 1252 static inline uint32_t CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI(uint32_t val) 1253 { 1254 return ((val) << CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__SHIFT) & CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__MASK; 1255 } 1256 1257 #define REG_CP_SET_BIN_DATA5_OFFSET_0 0x00000000 1258 #define CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__MASK 0x003f0000 1259 #define CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__SHIFT 16 1260 static inline uint32_t CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE(uint32_t val) 1261 { 1262 return ((val) << CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__SHIFT) & CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__MASK; 1263 } 1264 #define CP_SET_BIN_DATA5_OFFSET_0_VSC_N__MASK 0x07c00000 1265 #define CP_SET_BIN_DATA5_OFFSET_0_VSC_N__SHIFT 22 1266 static inline uint32_t CP_SET_BIN_DATA5_OFFSET_0_VSC_N(uint32_t val) 1267 { 1268 return ((val) << CP_SET_BIN_DATA5_OFFSET_0_VSC_N__SHIFT) & CP_SET_BIN_DATA5_OFFSET_0_VSC_N__MASK; 1269 } 1270 1271 #define REG_CP_SET_BIN_DATA5_OFFSET_1 0x00000001 1272 #define CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__MASK 0xffffffff 1273 #define CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__SHIFT 0 1274 static inline uint32_t CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET(uint32_t val) 1275 { 1276 return ((val) << CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__SHIFT) & CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__MASK; 1277 } 1278 1279 #define REG_CP_SET_BIN_DATA5_OFFSET_2 0x00000002 1280 #define CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__MASK 0xffffffff 1281 #define CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__SHIFT 0 1282 static inline uint32_t CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET(uint32_t val) 1283 { 1284 return ((val) << CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__SHIFT) & CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__MASK; 1285 } 1286 1287 #define REG_CP_SET_BIN_DATA5_OFFSET_3 0x00000003 1288 #define CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__MASK 0xffffffff 1289 #define CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__SHIFT 0 1290 static inline uint32_t CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET(uint32_t val) 1291 { 1292 return ((val) << CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__SHIFT) & CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__MASK; 1293 } 1294 1295 #define REG_CP_REG_RMW_0 0x00000000 1296 #define CP_REG_RMW_0_DST_REG__MASK 0x0003ffff 1297 #define CP_REG_RMW_0_DST_REG__SHIFT 0 1298 static inline uint32_t CP_REG_RMW_0_DST_REG(uint32_t val) 1299 { 1300 return ((val) << CP_REG_RMW_0_DST_REG__SHIFT) & CP_REG_RMW_0_DST_REG__MASK; 1301 } 1302 #define CP_REG_RMW_0_ROTATE__MASK 0x1f000000 1303 #define CP_REG_RMW_0_ROTATE__SHIFT 24 1304 static inline uint32_t CP_REG_RMW_0_ROTATE(uint32_t val) 1305 { 1306 return ((val) << CP_REG_RMW_0_ROTATE__SHIFT) & CP_REG_RMW_0_ROTATE__MASK; 1307 } 1308 #define CP_REG_RMW_0_SRC1_ADD 0x20000000 1309 #define CP_REG_RMW_0_SRC1_IS_REG 0x40000000 1310 #define CP_REG_RMW_0_SRC0_IS_REG 0x80000000 1311 1312 #define REG_CP_REG_RMW_1 0x00000001 1313 #define CP_REG_RMW_1_SRC0__MASK 0xffffffff 1314 #define CP_REG_RMW_1_SRC0__SHIFT 0 1315 static inline uint32_t CP_REG_RMW_1_SRC0(uint32_t val) 1316 { 1317 return ((val) << CP_REG_RMW_1_SRC0__SHIFT) & CP_REG_RMW_1_SRC0__MASK; 1318 } 1319 1320 #define REG_CP_REG_RMW_2 0x00000002 1321 #define CP_REG_RMW_2_SRC1__MASK 0xffffffff 1322 #define CP_REG_RMW_2_SRC1__SHIFT 0 1323 static inline uint32_t CP_REG_RMW_2_SRC1(uint32_t val) 1324 { 1325 return ((val) << CP_REG_RMW_2_SRC1__SHIFT) & CP_REG_RMW_2_SRC1__MASK; 1326 } 1327 1328 #define REG_CP_REG_TO_MEM_0 0x00000000 1329 #define CP_REG_TO_MEM_0_REG__MASK 0x0003ffff 1330 #define CP_REG_TO_MEM_0_REG__SHIFT 0 1331 static inline uint32_t CP_REG_TO_MEM_0_REG(uint32_t val) 1332 { 1333 return ((val) << CP_REG_TO_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_0_REG__MASK; 1334 } 1335 #define CP_REG_TO_MEM_0_CNT__MASK 0x3ffc0000 1336 #define CP_REG_TO_MEM_0_CNT__SHIFT 18 1337 static inline uint32_t CP_REG_TO_MEM_0_CNT(uint32_t val) 1338 { 1339 return ((val) << CP_REG_TO_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_0_CNT__MASK; 1340 } 1341 #define CP_REG_TO_MEM_0_64B 0x40000000 1342 #define CP_REG_TO_MEM_0_ACCUMULATE 0x80000000 1343 1344 #define REG_CP_REG_TO_MEM_1 0x00000001 1345 #define CP_REG_TO_MEM_1_DEST__MASK 0xffffffff 1346 #define CP_REG_TO_MEM_1_DEST__SHIFT 0 1347 static inline uint32_t CP_REG_TO_MEM_1_DEST(uint32_t val) 1348 { 1349 return ((val) << CP_REG_TO_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_1_DEST__MASK; 1350 } 1351 1352 #define REG_CP_REG_TO_MEM_2 0x00000002 1353 #define CP_REG_TO_MEM_2_DEST_HI__MASK 0xffffffff 1354 #define CP_REG_TO_MEM_2_DEST_HI__SHIFT 0 1355 static inline uint32_t CP_REG_TO_MEM_2_DEST_HI(uint32_t val) 1356 { 1357 return ((val) << CP_REG_TO_MEM_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_2_DEST_HI__MASK; 1358 } 1359 1360 #define REG_CP_REG_TO_MEM_OFFSET_REG_0 0x00000000 1361 #define CP_REG_TO_MEM_OFFSET_REG_0_REG__MASK 0x0003ffff 1362 #define CP_REG_TO_MEM_OFFSET_REG_0_REG__SHIFT 0 1363 static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_0_REG(uint32_t val) 1364 { 1365 return ((val) << CP_REG_TO_MEM_OFFSET_REG_0_REG__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_0_REG__MASK; 1366 } 1367 #define CP_REG_TO_MEM_OFFSET_REG_0_CNT__MASK 0x3ffc0000 1368 #define CP_REG_TO_MEM_OFFSET_REG_0_CNT__SHIFT 18 1369 static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_0_CNT(uint32_t val) 1370 { 1371 return ((val) << CP_REG_TO_MEM_OFFSET_REG_0_CNT__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_0_CNT__MASK; 1372 } 1373 #define CP_REG_TO_MEM_OFFSET_REG_0_64B 0x40000000 1374 #define CP_REG_TO_MEM_OFFSET_REG_0_ACCUMULATE 0x80000000 1375 1376 #define REG_CP_REG_TO_MEM_OFFSET_REG_1 0x00000001 1377 #define CP_REG_TO_MEM_OFFSET_REG_1_DEST__MASK 0xffffffff 1378 #define CP_REG_TO_MEM_OFFSET_REG_1_DEST__SHIFT 0 1379 static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_1_DEST(uint32_t val) 1380 { 1381 return ((val) << CP_REG_TO_MEM_OFFSET_REG_1_DEST__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_1_DEST__MASK; 1382 } 1383 1384 #define REG_CP_REG_TO_MEM_OFFSET_REG_2 0x00000002 1385 #define CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__MASK 0xffffffff 1386 #define CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__SHIFT 0 1387 static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI(uint32_t val) 1388 { 1389 return ((val) << CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__MASK; 1390 } 1391 1392 #define REG_CP_REG_TO_MEM_OFFSET_REG_3 0x00000003 1393 #define CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__MASK 0x0003ffff 1394 #define CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__SHIFT 0 1395 static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0(uint32_t val) 1396 { 1397 return ((val) << CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__MASK; 1398 } 1399 #define CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0_SCRATCH 0x00080000 1400 1401 #define REG_CP_REG_TO_MEM_OFFSET_MEM_0 0x00000000 1402 #define CP_REG_TO_MEM_OFFSET_MEM_0_REG__MASK 0x0003ffff 1403 #define CP_REG_TO_MEM_OFFSET_MEM_0_REG__SHIFT 0 1404 static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_0_REG(uint32_t val) 1405 { 1406 return ((val) << CP_REG_TO_MEM_OFFSET_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_0_REG__MASK; 1407 } 1408 #define CP_REG_TO_MEM_OFFSET_MEM_0_CNT__MASK 0x3ffc0000 1409 #define CP_REG_TO_MEM_OFFSET_MEM_0_CNT__SHIFT 18 1410 static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_0_CNT(uint32_t val) 1411 { 1412 return ((val) << CP_REG_TO_MEM_OFFSET_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_0_CNT__MASK; 1413 } 1414 #define CP_REG_TO_MEM_OFFSET_MEM_0_64B 0x40000000 1415 #define CP_REG_TO_MEM_OFFSET_MEM_0_ACCUMULATE 0x80000000 1416 1417 #define REG_CP_REG_TO_MEM_OFFSET_MEM_1 0x00000001 1418 #define CP_REG_TO_MEM_OFFSET_MEM_1_DEST__MASK 0xffffffff 1419 #define CP_REG_TO_MEM_OFFSET_MEM_1_DEST__SHIFT 0 1420 static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_1_DEST(uint32_t val) 1421 { 1422 return ((val) << CP_REG_TO_MEM_OFFSET_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_1_DEST__MASK; 1423 } 1424 1425 #define REG_CP_REG_TO_MEM_OFFSET_MEM_2 0x00000002 1426 #define CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__MASK 0xffffffff 1427 #define CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__SHIFT 0 1428 static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI(uint32_t val) 1429 { 1430 return ((val) << CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__MASK; 1431 } 1432 1433 #define REG_CP_REG_TO_MEM_OFFSET_MEM_3 0x00000003 1434 #define CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__MASK 0xffffffff 1435 #define CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__SHIFT 0 1436 static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO(uint32_t val) 1437 { 1438 return ((val) << CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__MASK; 1439 } 1440 1441 #define REG_CP_REG_TO_MEM_OFFSET_MEM_4 0x00000004 1442 #define CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__MASK 0xffffffff 1443 #define CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__SHIFT 0 1444 static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI(uint32_t val) 1445 { 1446 return ((val) << CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__MASK; 1447 } 1448 1449 #define REG_CP_MEM_TO_REG_0 0x00000000 1450 #define CP_MEM_TO_REG_0_REG__MASK 0x0003ffff 1451 #define CP_MEM_TO_REG_0_REG__SHIFT 0 1452 static inline uint32_t CP_MEM_TO_REG_0_REG(uint32_t val) 1453 { 1454 return ((val) << CP_MEM_TO_REG_0_REG__SHIFT) & CP_MEM_TO_REG_0_REG__MASK; 1455 } 1456 #define CP_MEM_TO_REG_0_CNT__MASK 0x3ff80000 1457 #define CP_MEM_TO_REG_0_CNT__SHIFT 19 1458 static inline uint32_t CP_MEM_TO_REG_0_CNT(uint32_t val) 1459 { 1460 return ((val) << CP_MEM_TO_REG_0_CNT__SHIFT) & CP_MEM_TO_REG_0_CNT__MASK; 1461 } 1462 #define CP_MEM_TO_REG_0_SHIFT_BY_2 0x40000000 1463 #define CP_MEM_TO_REG_0_UNK31 0x80000000 1464 1465 #define REG_CP_MEM_TO_REG_1 0x00000001 1466 #define CP_MEM_TO_REG_1_SRC__MASK 0xffffffff 1467 #define CP_MEM_TO_REG_1_SRC__SHIFT 0 1468 static inline uint32_t CP_MEM_TO_REG_1_SRC(uint32_t val) 1469 { 1470 return ((val) << CP_MEM_TO_REG_1_SRC__SHIFT) & CP_MEM_TO_REG_1_SRC__MASK; 1471 } 1472 1473 #define REG_CP_MEM_TO_REG_2 0x00000002 1474 #define CP_MEM_TO_REG_2_SRC_HI__MASK 0xffffffff 1475 #define CP_MEM_TO_REG_2_SRC_HI__SHIFT 0 1476 static inline uint32_t CP_MEM_TO_REG_2_SRC_HI(uint32_t val) 1477 { 1478 return ((val) << CP_MEM_TO_REG_2_SRC_HI__SHIFT) & CP_MEM_TO_REG_2_SRC_HI__MASK; 1479 } 1480 1481 #define REG_CP_MEM_TO_MEM_0 0x00000000 1482 #define CP_MEM_TO_MEM_0_NEG_A 0x00000001 1483 #define CP_MEM_TO_MEM_0_NEG_B 0x00000002 1484 #define CP_MEM_TO_MEM_0_NEG_C 0x00000004 1485 #define CP_MEM_TO_MEM_0_DOUBLE 0x20000000 1486 #define CP_MEM_TO_MEM_0_WAIT_FOR_MEM_WRITES 0x40000000 1487 #define CP_MEM_TO_MEM_0_UNK31 0x80000000 1488 1489 #define REG_CP_MEMCPY_0 0x00000000 1490 #define CP_MEMCPY_0_DWORDS__MASK 0xffffffff 1491 #define CP_MEMCPY_0_DWORDS__SHIFT 0 1492 static inline uint32_t CP_MEMCPY_0_DWORDS(uint32_t val) 1493 { 1494 return ((val) << CP_MEMCPY_0_DWORDS__SHIFT) & CP_MEMCPY_0_DWORDS__MASK; 1495 } 1496 1497 #define REG_CP_MEMCPY_1 0x00000001 1498 #define CP_MEMCPY_1_SRC_LO__MASK 0xffffffff 1499 #define CP_MEMCPY_1_SRC_LO__SHIFT 0 1500 static inline uint32_t CP_MEMCPY_1_SRC_LO(uint32_t val) 1501 { 1502 return ((val) << CP_MEMCPY_1_SRC_LO__SHIFT) & CP_MEMCPY_1_SRC_LO__MASK; 1503 } 1504 1505 #define REG_CP_MEMCPY_2 0x00000002 1506 #define CP_MEMCPY_2_SRC_HI__MASK 0xffffffff 1507 #define CP_MEMCPY_2_SRC_HI__SHIFT 0 1508 static inline uint32_t CP_MEMCPY_2_SRC_HI(uint32_t val) 1509 { 1510 return ((val) << CP_MEMCPY_2_SRC_HI__SHIFT) & CP_MEMCPY_2_SRC_HI__MASK; 1511 } 1512 1513 #define REG_CP_MEMCPY_3 0x00000003 1514 #define CP_MEMCPY_3_DST_LO__MASK 0xffffffff 1515 #define CP_MEMCPY_3_DST_LO__SHIFT 0 1516 static inline uint32_t CP_MEMCPY_3_DST_LO(uint32_t val) 1517 { 1518 return ((val) << CP_MEMCPY_3_DST_LO__SHIFT) & CP_MEMCPY_3_DST_LO__MASK; 1519 } 1520 1521 #define REG_CP_MEMCPY_4 0x00000004 1522 #define CP_MEMCPY_4_DST_HI__MASK 0xffffffff 1523 #define CP_MEMCPY_4_DST_HI__SHIFT 0 1524 static inline uint32_t CP_MEMCPY_4_DST_HI(uint32_t val) 1525 { 1526 return ((val) << CP_MEMCPY_4_DST_HI__SHIFT) & CP_MEMCPY_4_DST_HI__MASK; 1527 } 1528 1529 #define REG_CP_REG_TO_SCRATCH_0 0x00000000 1530 #define CP_REG_TO_SCRATCH_0_REG__MASK 0x0003ffff 1531 #define CP_REG_TO_SCRATCH_0_REG__SHIFT 0 1532 static inline uint32_t CP_REG_TO_SCRATCH_0_REG(uint32_t val) 1533 { 1534 return ((val) << CP_REG_TO_SCRATCH_0_REG__SHIFT) & CP_REG_TO_SCRATCH_0_REG__MASK; 1535 } 1536 #define CP_REG_TO_SCRATCH_0_SCRATCH__MASK 0x00700000 1537 #define CP_REG_TO_SCRATCH_0_SCRATCH__SHIFT 20 1538 static inline uint32_t CP_REG_TO_SCRATCH_0_SCRATCH(uint32_t val) 1539 { 1540 return ((val) << CP_REG_TO_SCRATCH_0_SCRATCH__SHIFT) & CP_REG_TO_SCRATCH_0_SCRATCH__MASK; 1541 } 1542 #define CP_REG_TO_SCRATCH_0_CNT__MASK 0x07000000 1543 #define CP_REG_TO_SCRATCH_0_CNT__SHIFT 24 1544 static inline uint32_t CP_REG_TO_SCRATCH_0_CNT(uint32_t val) 1545 { 1546 return ((val) << CP_REG_TO_SCRATCH_0_CNT__SHIFT) & CP_REG_TO_SCRATCH_0_CNT__MASK; 1547 } 1548 1549 #define REG_CP_SCRATCH_TO_REG_0 0x00000000 1550 #define CP_SCRATCH_TO_REG_0_REG__MASK 0x0003ffff 1551 #define CP_SCRATCH_TO_REG_0_REG__SHIFT 0 1552 static inline uint32_t CP_SCRATCH_TO_REG_0_REG(uint32_t val) 1553 { 1554 return ((val) << CP_SCRATCH_TO_REG_0_REG__SHIFT) & CP_SCRATCH_TO_REG_0_REG__MASK; 1555 } 1556 #define CP_SCRATCH_TO_REG_0_UNK18 0x00040000 1557 #define CP_SCRATCH_TO_REG_0_SCRATCH__MASK 0x00700000 1558 #define CP_SCRATCH_TO_REG_0_SCRATCH__SHIFT 20 1559 static inline uint32_t CP_SCRATCH_TO_REG_0_SCRATCH(uint32_t val) 1560 { 1561 return ((val) << CP_SCRATCH_TO_REG_0_SCRATCH__SHIFT) & CP_SCRATCH_TO_REG_0_SCRATCH__MASK; 1562 } 1563 #define CP_SCRATCH_TO_REG_0_CNT__MASK 0x07000000 1564 #define CP_SCRATCH_TO_REG_0_CNT__SHIFT 24 1565 static inline uint32_t CP_SCRATCH_TO_REG_0_CNT(uint32_t val) 1566 { 1567 return ((val) << CP_SCRATCH_TO_REG_0_CNT__SHIFT) & CP_SCRATCH_TO_REG_0_CNT__MASK; 1568 } 1569 1570 #define REG_CP_SCRATCH_WRITE_0 0x00000000 1571 #define CP_SCRATCH_WRITE_0_SCRATCH__MASK 0x00700000 1572 #define CP_SCRATCH_WRITE_0_SCRATCH__SHIFT 20 1573 static inline uint32_t CP_SCRATCH_WRITE_0_SCRATCH(uint32_t val) 1574 { 1575 return ((val) << CP_SCRATCH_WRITE_0_SCRATCH__SHIFT) & CP_SCRATCH_WRITE_0_SCRATCH__MASK; 1576 } 1577 1578 #define REG_CP_MEM_WRITE_0 0x00000000 1579 #define CP_MEM_WRITE_0_ADDR_LO__MASK 0xffffffff 1580 #define CP_MEM_WRITE_0_ADDR_LO__SHIFT 0 1581 static inline uint32_t CP_MEM_WRITE_0_ADDR_LO(uint32_t val) 1582 { 1583 return ((val) << CP_MEM_WRITE_0_ADDR_LO__SHIFT) & CP_MEM_WRITE_0_ADDR_LO__MASK; 1584 } 1585 1586 #define REG_CP_MEM_WRITE_1 0x00000001 1587 #define CP_MEM_WRITE_1_ADDR_HI__MASK 0xffffffff 1588 #define CP_MEM_WRITE_1_ADDR_HI__SHIFT 0 1589 static inline uint32_t CP_MEM_WRITE_1_ADDR_HI(uint32_t val) 1590 { 1591 return ((val) << CP_MEM_WRITE_1_ADDR_HI__SHIFT) & CP_MEM_WRITE_1_ADDR_HI__MASK; 1592 } 1593 1594 #define REG_CP_COND_WRITE_0 0x00000000 1595 #define CP_COND_WRITE_0_FUNCTION__MASK 0x00000007 1596 #define CP_COND_WRITE_0_FUNCTION__SHIFT 0 1597 static inline uint32_t CP_COND_WRITE_0_FUNCTION(enum cp_cond_function val) 1598 { 1599 return ((val) << CP_COND_WRITE_0_FUNCTION__SHIFT) & CP_COND_WRITE_0_FUNCTION__MASK; 1600 } 1601 #define CP_COND_WRITE_0_POLL_MEMORY 0x00000010 1602 #define CP_COND_WRITE_0_WRITE_MEMORY 0x00000100 1603 1604 #define REG_CP_COND_WRITE_1 0x00000001 1605 #define CP_COND_WRITE_1_POLL_ADDR__MASK 0xffffffff 1606 #define CP_COND_WRITE_1_POLL_ADDR__SHIFT 0 1607 static inline uint32_t CP_COND_WRITE_1_POLL_ADDR(uint32_t val) 1608 { 1609 return ((val) << CP_COND_WRITE_1_POLL_ADDR__SHIFT) & CP_COND_WRITE_1_POLL_ADDR__MASK; 1610 } 1611 1612 #define REG_CP_COND_WRITE_2 0x00000002 1613 #define CP_COND_WRITE_2_REF__MASK 0xffffffff 1614 #define CP_COND_WRITE_2_REF__SHIFT 0 1615 static inline uint32_t CP_COND_WRITE_2_REF(uint32_t val) 1616 { 1617 return ((val) << CP_COND_WRITE_2_REF__SHIFT) & CP_COND_WRITE_2_REF__MASK; 1618 } 1619 1620 #define REG_CP_COND_WRITE_3 0x00000003 1621 #define CP_COND_WRITE_3_MASK__MASK 0xffffffff 1622 #define CP_COND_WRITE_3_MASK__SHIFT 0 1623 static inline uint32_t CP_COND_WRITE_3_MASK(uint32_t val) 1624 { 1625 return ((val) << CP_COND_WRITE_3_MASK__SHIFT) & CP_COND_WRITE_3_MASK__MASK; 1626 } 1627 1628 #define REG_CP_COND_WRITE_4 0x00000004 1629 #define CP_COND_WRITE_4_WRITE_ADDR__MASK 0xffffffff 1630 #define CP_COND_WRITE_4_WRITE_ADDR__SHIFT 0 1631 static inline uint32_t CP_COND_WRITE_4_WRITE_ADDR(uint32_t val) 1632 { 1633 return ((val) << CP_COND_WRITE_4_WRITE_ADDR__SHIFT) & CP_COND_WRITE_4_WRITE_ADDR__MASK; 1634 } 1635 1636 #define REG_CP_COND_WRITE_5 0x00000005 1637 #define CP_COND_WRITE_5_WRITE_DATA__MASK 0xffffffff 1638 #define CP_COND_WRITE_5_WRITE_DATA__SHIFT 0 1639 static inline uint32_t CP_COND_WRITE_5_WRITE_DATA(uint32_t val) 1640 { 1641 return ((val) << CP_COND_WRITE_5_WRITE_DATA__SHIFT) & CP_COND_WRITE_5_WRITE_DATA__MASK; 1642 } 1643 1644 #define REG_CP_COND_WRITE5_0 0x00000000 1645 #define CP_COND_WRITE5_0_FUNCTION__MASK 0x00000007 1646 #define CP_COND_WRITE5_0_FUNCTION__SHIFT 0 1647 static inline uint32_t CP_COND_WRITE5_0_FUNCTION(enum cp_cond_function val) 1648 { 1649 return ((val) << CP_COND_WRITE5_0_FUNCTION__SHIFT) & CP_COND_WRITE5_0_FUNCTION__MASK; 1650 } 1651 #define CP_COND_WRITE5_0_SIGNED_COMPARE 0x00000008 1652 #define CP_COND_WRITE5_0_POLL_MEMORY 0x00000010 1653 #define CP_COND_WRITE5_0_POLL_SCRATCH 0x00000020 1654 #define CP_COND_WRITE5_0_WRITE_MEMORY 0x00000100 1655 1656 #define REG_CP_COND_WRITE5_1 0x00000001 1657 #define CP_COND_WRITE5_1_POLL_ADDR_LO__MASK 0xffffffff 1658 #define CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT 0 1659 static inline uint32_t CP_COND_WRITE5_1_POLL_ADDR_LO(uint32_t val) 1660 { 1661 return ((val) << CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT) & CP_COND_WRITE5_1_POLL_ADDR_LO__MASK; 1662 } 1663 1664 #define REG_CP_COND_WRITE5_2 0x00000002 1665 #define CP_COND_WRITE5_2_POLL_ADDR_HI__MASK 0xffffffff 1666 #define CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT 0 1667 static inline uint32_t CP_COND_WRITE5_2_POLL_ADDR_HI(uint32_t val) 1668 { 1669 return ((val) << CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT) & CP_COND_WRITE5_2_POLL_ADDR_HI__MASK; 1670 } 1671 1672 #define REG_CP_COND_WRITE5_3 0x00000003 1673 #define CP_COND_WRITE5_3_REF__MASK 0xffffffff 1674 #define CP_COND_WRITE5_3_REF__SHIFT 0 1675 static inline uint32_t CP_COND_WRITE5_3_REF(uint32_t val) 1676 { 1677 return ((val) << CP_COND_WRITE5_3_REF__SHIFT) & CP_COND_WRITE5_3_REF__MASK; 1678 } 1679 1680 #define REG_CP_COND_WRITE5_4 0x00000004 1681 #define CP_COND_WRITE5_4_MASK__MASK 0xffffffff 1682 #define CP_COND_WRITE5_4_MASK__SHIFT 0 1683 static inline uint32_t CP_COND_WRITE5_4_MASK(uint32_t val) 1684 { 1685 return ((val) << CP_COND_WRITE5_4_MASK__SHIFT) & CP_COND_WRITE5_4_MASK__MASK; 1686 } 1687 1688 #define REG_CP_COND_WRITE5_5 0x00000005 1689 #define CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK 0xffffffff 1690 #define CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT 0 1691 static inline uint32_t CP_COND_WRITE5_5_WRITE_ADDR_LO(uint32_t val) 1692 { 1693 return ((val) << CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT) & CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK; 1694 } 1695 1696 #define REG_CP_COND_WRITE5_6 0x00000006 1697 #define CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK 0xffffffff 1698 #define CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT 0 1699 static inline uint32_t CP_COND_WRITE5_6_WRITE_ADDR_HI(uint32_t val) 1700 { 1701 return ((val) << CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT) & CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK; 1702 } 1703 1704 #define REG_CP_COND_WRITE5_7 0x00000007 1705 #define CP_COND_WRITE5_7_WRITE_DATA__MASK 0xffffffff 1706 #define CP_COND_WRITE5_7_WRITE_DATA__SHIFT 0 1707 static inline uint32_t CP_COND_WRITE5_7_WRITE_DATA(uint32_t val) 1708 { 1709 return ((val) << CP_COND_WRITE5_7_WRITE_DATA__SHIFT) & CP_COND_WRITE5_7_WRITE_DATA__MASK; 1710 } 1711 1712 #define REG_CP_WAIT_MEM_GTE_0 0x00000000 1713 #define CP_WAIT_MEM_GTE_0_RESERVED__MASK 0xffffffff 1714 #define CP_WAIT_MEM_GTE_0_RESERVED__SHIFT 0 1715 static inline uint32_t CP_WAIT_MEM_GTE_0_RESERVED(uint32_t val) 1716 { 1717 return ((val) << CP_WAIT_MEM_GTE_0_RESERVED__SHIFT) & CP_WAIT_MEM_GTE_0_RESERVED__MASK; 1718 } 1719 1720 #define REG_CP_WAIT_MEM_GTE_1 0x00000001 1721 #define CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__MASK 0xffffffff 1722 #define CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__SHIFT 0 1723 static inline uint32_t CP_WAIT_MEM_GTE_1_POLL_ADDR_LO(uint32_t val) 1724 { 1725 return ((val) << CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__SHIFT) & CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__MASK; 1726 } 1727 1728 #define REG_CP_WAIT_MEM_GTE_2 0x00000002 1729 #define CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__MASK 0xffffffff 1730 #define CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__SHIFT 0 1731 static inline uint32_t CP_WAIT_MEM_GTE_2_POLL_ADDR_HI(uint32_t val) 1732 { 1733 return ((val) << CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__SHIFT) & CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__MASK; 1734 } 1735 1736 #define REG_CP_WAIT_MEM_GTE_3 0x00000003 1737 #define CP_WAIT_MEM_GTE_3_REF__MASK 0xffffffff 1738 #define CP_WAIT_MEM_GTE_3_REF__SHIFT 0 1739 static inline uint32_t CP_WAIT_MEM_GTE_3_REF(uint32_t val) 1740 { 1741 return ((val) << CP_WAIT_MEM_GTE_3_REF__SHIFT) & CP_WAIT_MEM_GTE_3_REF__MASK; 1742 } 1743 1744 #define REG_CP_WAIT_REG_MEM_0 0x00000000 1745 #define CP_WAIT_REG_MEM_0_FUNCTION__MASK 0x00000007 1746 #define CP_WAIT_REG_MEM_0_FUNCTION__SHIFT 0 1747 static inline uint32_t CP_WAIT_REG_MEM_0_FUNCTION(enum cp_cond_function val) 1748 { 1749 return ((val) << CP_WAIT_REG_MEM_0_FUNCTION__SHIFT) & CP_WAIT_REG_MEM_0_FUNCTION__MASK; 1750 } 1751 #define CP_WAIT_REG_MEM_0_SIGNED_COMPARE 0x00000008 1752 #define CP_WAIT_REG_MEM_0_POLL_MEMORY 0x00000010 1753 #define CP_WAIT_REG_MEM_0_POLL_SCRATCH 0x00000020 1754 #define CP_WAIT_REG_MEM_0_WRITE_MEMORY 0x00000100 1755 1756 #define REG_CP_WAIT_REG_MEM_1 0x00000001 1757 #define CP_WAIT_REG_MEM_1_POLL_ADDR_LO__MASK 0xffffffff 1758 #define CP_WAIT_REG_MEM_1_POLL_ADDR_LO__SHIFT 0 1759 static inline uint32_t CP_WAIT_REG_MEM_1_POLL_ADDR_LO(uint32_t val) 1760 { 1761 return ((val) << CP_WAIT_REG_MEM_1_POLL_ADDR_LO__SHIFT) & CP_WAIT_REG_MEM_1_POLL_ADDR_LO__MASK; 1762 } 1763 1764 #define REG_CP_WAIT_REG_MEM_2 0x00000002 1765 #define CP_WAIT_REG_MEM_2_POLL_ADDR_HI__MASK 0xffffffff 1766 #define CP_WAIT_REG_MEM_2_POLL_ADDR_HI__SHIFT 0 1767 static inline uint32_t CP_WAIT_REG_MEM_2_POLL_ADDR_HI(uint32_t val) 1768 { 1769 return ((val) << CP_WAIT_REG_MEM_2_POLL_ADDR_HI__SHIFT) & CP_WAIT_REG_MEM_2_POLL_ADDR_HI__MASK; 1770 } 1771 1772 #define REG_CP_WAIT_REG_MEM_3 0x00000003 1773 #define CP_WAIT_REG_MEM_3_REF__MASK 0xffffffff 1774 #define CP_WAIT_REG_MEM_3_REF__SHIFT 0 1775 static inline uint32_t CP_WAIT_REG_MEM_3_REF(uint32_t val) 1776 { 1777 return ((val) << CP_WAIT_REG_MEM_3_REF__SHIFT) & CP_WAIT_REG_MEM_3_REF__MASK; 1778 } 1779 1780 #define REG_CP_WAIT_REG_MEM_4 0x00000004 1781 #define CP_WAIT_REG_MEM_4_MASK__MASK 0xffffffff 1782 #define CP_WAIT_REG_MEM_4_MASK__SHIFT 0 1783 static inline uint32_t CP_WAIT_REG_MEM_4_MASK(uint32_t val) 1784 { 1785 return ((val) << CP_WAIT_REG_MEM_4_MASK__SHIFT) & CP_WAIT_REG_MEM_4_MASK__MASK; 1786 } 1787 1788 #define REG_CP_WAIT_REG_MEM_5 0x00000005 1789 #define CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__MASK 0xffffffff 1790 #define CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__SHIFT 0 1791 static inline uint32_t CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(uint32_t val) 1792 { 1793 return ((val) << CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__SHIFT) & CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__MASK; 1794 } 1795 1796 #define REG_CP_WAIT_TWO_REGS_0 0x00000000 1797 #define CP_WAIT_TWO_REGS_0_REG0__MASK 0x0003ffff 1798 #define CP_WAIT_TWO_REGS_0_REG0__SHIFT 0 1799 static inline uint32_t CP_WAIT_TWO_REGS_0_REG0(uint32_t val) 1800 { 1801 return ((val) << CP_WAIT_TWO_REGS_0_REG0__SHIFT) & CP_WAIT_TWO_REGS_0_REG0__MASK; 1802 } 1803 1804 #define REG_CP_WAIT_TWO_REGS_1 0x00000001 1805 #define CP_WAIT_TWO_REGS_1_REG1__MASK 0x0003ffff 1806 #define CP_WAIT_TWO_REGS_1_REG1__SHIFT 0 1807 static inline uint32_t CP_WAIT_TWO_REGS_1_REG1(uint32_t val) 1808 { 1809 return ((val) << CP_WAIT_TWO_REGS_1_REG1__SHIFT) & CP_WAIT_TWO_REGS_1_REG1__MASK; 1810 } 1811 1812 #define REG_CP_WAIT_TWO_REGS_2 0x00000002 1813 #define CP_WAIT_TWO_REGS_2_REF__MASK 0xffffffff 1814 #define CP_WAIT_TWO_REGS_2_REF__SHIFT 0 1815 static inline uint32_t CP_WAIT_TWO_REGS_2_REF(uint32_t val) 1816 { 1817 return ((val) << CP_WAIT_TWO_REGS_2_REF__SHIFT) & CP_WAIT_TWO_REGS_2_REF__MASK; 1818 } 1819 1820 #define REG_CP_DISPATCH_COMPUTE_0 0x00000000 1821 1822 #define REG_CP_DISPATCH_COMPUTE_1 0x00000001 1823 #define CP_DISPATCH_COMPUTE_1_X__MASK 0xffffffff 1824 #define CP_DISPATCH_COMPUTE_1_X__SHIFT 0 1825 static inline uint32_t CP_DISPATCH_COMPUTE_1_X(uint32_t val) 1826 { 1827 return ((val) << CP_DISPATCH_COMPUTE_1_X__SHIFT) & CP_DISPATCH_COMPUTE_1_X__MASK; 1828 } 1829 1830 #define REG_CP_DISPATCH_COMPUTE_2 0x00000002 1831 #define CP_DISPATCH_COMPUTE_2_Y__MASK 0xffffffff 1832 #define CP_DISPATCH_COMPUTE_2_Y__SHIFT 0 1833 static inline uint32_t CP_DISPATCH_COMPUTE_2_Y(uint32_t val) 1834 { 1835 return ((val) << CP_DISPATCH_COMPUTE_2_Y__SHIFT) & CP_DISPATCH_COMPUTE_2_Y__MASK; 1836 } 1837 1838 #define REG_CP_DISPATCH_COMPUTE_3 0x00000003 1839 #define CP_DISPATCH_COMPUTE_3_Z__MASK 0xffffffff 1840 #define CP_DISPATCH_COMPUTE_3_Z__SHIFT 0 1841 static inline uint32_t CP_DISPATCH_COMPUTE_3_Z(uint32_t val) 1842 { 1843 return ((val) << CP_DISPATCH_COMPUTE_3_Z__SHIFT) & CP_DISPATCH_COMPUTE_3_Z__MASK; 1844 } 1845 1846 #define REG_CP_SET_RENDER_MODE_0 0x00000000 1847 #define CP_SET_RENDER_MODE_0_MODE__MASK 0x000001ff 1848 #define CP_SET_RENDER_MODE_0_MODE__SHIFT 0 1849 static inline uint32_t CP_SET_RENDER_MODE_0_MODE(enum render_mode_cmd val) 1850 { 1851 return ((val) << CP_SET_RENDER_MODE_0_MODE__SHIFT) & CP_SET_RENDER_MODE_0_MODE__MASK; 1852 } 1853 1854 #define REG_CP_SET_RENDER_MODE_1 0x00000001 1855 #define CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK 0xffffffff 1856 #define CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT 0 1857 static inline uint32_t CP_SET_RENDER_MODE_1_ADDR_0_LO(uint32_t val) 1858 { 1859 return ((val) << CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT) & CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK; 1860 } 1861 1862 #define REG_CP_SET_RENDER_MODE_2 0x00000002 1863 #define CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK 0xffffffff 1864 #define CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT 0 1865 static inline uint32_t CP_SET_RENDER_MODE_2_ADDR_0_HI(uint32_t val) 1866 { 1867 return ((val) << CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT) & CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK; 1868 } 1869 1870 #define REG_CP_SET_RENDER_MODE_3 0x00000003 1871 #define CP_SET_RENDER_MODE_3_VSC_ENABLE 0x00000008 1872 #define CP_SET_RENDER_MODE_3_GMEM_ENABLE 0x00000010 1873 1874 #define REG_CP_SET_RENDER_MODE_4 0x00000004 1875 1876 #define REG_CP_SET_RENDER_MODE_5 0x00000005 1877 #define CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK 0xffffffff 1878 #define CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT 0 1879 static inline uint32_t CP_SET_RENDER_MODE_5_ADDR_1_LEN(uint32_t val) 1880 { 1881 return ((val) << CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT) & CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK; 1882 } 1883 1884 #define REG_CP_SET_RENDER_MODE_6 0x00000006 1885 #define CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK 0xffffffff 1886 #define CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT 0 1887 static inline uint32_t CP_SET_RENDER_MODE_6_ADDR_1_LO(uint32_t val) 1888 { 1889 return ((val) << CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT) & CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK; 1890 } 1891 1892 #define REG_CP_SET_RENDER_MODE_7 0x00000007 1893 #define CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK 0xffffffff 1894 #define CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT 0 1895 static inline uint32_t CP_SET_RENDER_MODE_7_ADDR_1_HI(uint32_t val) 1896 { 1897 return ((val) << CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT) & CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK; 1898 } 1899 1900 #define REG_CP_COMPUTE_CHECKPOINT_0 0x00000000 1901 #define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK 0xffffffff 1902 #define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT 0 1903 static inline uint32_t CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO(uint32_t val) 1904 { 1905 return ((val) << CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK; 1906 } 1907 1908 #define REG_CP_COMPUTE_CHECKPOINT_1 0x00000001 1909 #define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK 0xffffffff 1910 #define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT 0 1911 static inline uint32_t CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI(uint32_t val) 1912 { 1913 return ((val) << CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK; 1914 } 1915 1916 #define REG_CP_COMPUTE_CHECKPOINT_2 0x00000002 1917 1918 #define REG_CP_COMPUTE_CHECKPOINT_3 0x00000003 1919 #define CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__MASK 0xffffffff 1920 #define CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__SHIFT 0 1921 static inline uint32_t CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN(uint32_t val) 1922 { 1923 return ((val) << CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__SHIFT) & CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__MASK; 1924 } 1925 1926 #define REG_CP_COMPUTE_CHECKPOINT_4 0x00000004 1927 1928 #define REG_CP_COMPUTE_CHECKPOINT_5 0x00000005 1929 #define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK 0xffffffff 1930 #define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT 0 1931 static inline uint32_t CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO(uint32_t val) 1932 { 1933 return ((val) << CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK; 1934 } 1935 1936 #define REG_CP_COMPUTE_CHECKPOINT_6 0x00000006 1937 #define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK 0xffffffff 1938 #define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT 0 1939 static inline uint32_t CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI(uint32_t val) 1940 { 1941 return ((val) << CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK; 1942 } 1943 1944 #define REG_CP_COMPUTE_CHECKPOINT_7 0x00000007 1945 1946 #define REG_CP_PERFCOUNTER_ACTION_0 0x00000000 1947 1948 #define REG_CP_PERFCOUNTER_ACTION_1 0x00000001 1949 #define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK 0xffffffff 1950 #define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT 0 1951 static inline uint32_t CP_PERFCOUNTER_ACTION_1_ADDR_0_LO(uint32_t val) 1952 { 1953 return ((val) << CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT) & CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK; 1954 } 1955 1956 #define REG_CP_PERFCOUNTER_ACTION_2 0x00000002 1957 #define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK 0xffffffff 1958 #define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT 0 1959 static inline uint32_t CP_PERFCOUNTER_ACTION_2_ADDR_0_HI(uint32_t val) 1960 { 1961 return ((val) << CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT) & CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK; 1962 } 1963 1964 #define REG_CP_EVENT_WRITE_0 0x00000000 1965 #define CP_EVENT_WRITE_0_EVENT__MASK 0x000000ff 1966 #define CP_EVENT_WRITE_0_EVENT__SHIFT 0 1967 static inline uint32_t CP_EVENT_WRITE_0_EVENT(enum vgt_event_type val) 1968 { 1969 return ((val) << CP_EVENT_WRITE_0_EVENT__SHIFT) & CP_EVENT_WRITE_0_EVENT__MASK; 1970 } 1971 #define CP_EVENT_WRITE_0_TIMESTAMP 0x40000000 1972 #define CP_EVENT_WRITE_0_IRQ 0x80000000 1973 1974 #define REG_CP_EVENT_WRITE_1 0x00000001 1975 #define CP_EVENT_WRITE_1_ADDR_0_LO__MASK 0xffffffff 1976 #define CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT 0 1977 static inline uint32_t CP_EVENT_WRITE_1_ADDR_0_LO(uint32_t val) 1978 { 1979 return ((val) << CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT) & CP_EVENT_WRITE_1_ADDR_0_LO__MASK; 1980 } 1981 1982 #define REG_CP_EVENT_WRITE_2 0x00000002 1983 #define CP_EVENT_WRITE_2_ADDR_0_HI__MASK 0xffffffff 1984 #define CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT 0 1985 static inline uint32_t CP_EVENT_WRITE_2_ADDR_0_HI(uint32_t val) 1986 { 1987 return ((val) << CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT) & CP_EVENT_WRITE_2_ADDR_0_HI__MASK; 1988 } 1989 1990 #define REG_CP_EVENT_WRITE_3 0x00000003 1991 1992 #define REG_CP_BLIT_0 0x00000000 1993 #define CP_BLIT_0_OP__MASK 0x0000000f 1994 #define CP_BLIT_0_OP__SHIFT 0 1995 static inline uint32_t CP_BLIT_0_OP(enum cp_blit_cmd val) 1996 { 1997 return ((val) << CP_BLIT_0_OP__SHIFT) & CP_BLIT_0_OP__MASK; 1998 } 1999 2000 #define REG_CP_BLIT_1 0x00000001 2001 #define CP_BLIT_1_SRC_X1__MASK 0x00003fff 2002 #define CP_BLIT_1_SRC_X1__SHIFT 0 2003 static inline uint32_t CP_BLIT_1_SRC_X1(uint32_t val) 2004 { 2005 return ((val) << CP_BLIT_1_SRC_X1__SHIFT) & CP_BLIT_1_SRC_X1__MASK; 2006 } 2007 #define CP_BLIT_1_SRC_Y1__MASK 0x3fff0000 2008 #define CP_BLIT_1_SRC_Y1__SHIFT 16 2009 static inline uint32_t CP_BLIT_1_SRC_Y1(uint32_t val) 2010 { 2011 return ((val) << CP_BLIT_1_SRC_Y1__SHIFT) & CP_BLIT_1_SRC_Y1__MASK; 2012 } 2013 2014 #define REG_CP_BLIT_2 0x00000002 2015 #define CP_BLIT_2_SRC_X2__MASK 0x00003fff 2016 #define CP_BLIT_2_SRC_X2__SHIFT 0 2017 static inline uint32_t CP_BLIT_2_SRC_X2(uint32_t val) 2018 { 2019 return ((val) << CP_BLIT_2_SRC_X2__SHIFT) & CP_BLIT_2_SRC_X2__MASK; 2020 } 2021 #define CP_BLIT_2_SRC_Y2__MASK 0x3fff0000 2022 #define CP_BLIT_2_SRC_Y2__SHIFT 16 2023 static inline uint32_t CP_BLIT_2_SRC_Y2(uint32_t val) 2024 { 2025 return ((val) << CP_BLIT_2_SRC_Y2__SHIFT) & CP_BLIT_2_SRC_Y2__MASK; 2026 } 2027 2028 #define REG_CP_BLIT_3 0x00000003 2029 #define CP_BLIT_3_DST_X1__MASK 0x00003fff 2030 #define CP_BLIT_3_DST_X1__SHIFT 0 2031 static inline uint32_t CP_BLIT_3_DST_X1(uint32_t val) 2032 { 2033 return ((val) << CP_BLIT_3_DST_X1__SHIFT) & CP_BLIT_3_DST_X1__MASK; 2034 } 2035 #define CP_BLIT_3_DST_Y1__MASK 0x3fff0000 2036 #define CP_BLIT_3_DST_Y1__SHIFT 16 2037 static inline uint32_t CP_BLIT_3_DST_Y1(uint32_t val) 2038 { 2039 return ((val) << CP_BLIT_3_DST_Y1__SHIFT) & CP_BLIT_3_DST_Y1__MASK; 2040 } 2041 2042 #define REG_CP_BLIT_4 0x00000004 2043 #define CP_BLIT_4_DST_X2__MASK 0x00003fff 2044 #define CP_BLIT_4_DST_X2__SHIFT 0 2045 static inline uint32_t CP_BLIT_4_DST_X2(uint32_t val) 2046 { 2047 return ((val) << CP_BLIT_4_DST_X2__SHIFT) & CP_BLIT_4_DST_X2__MASK; 2048 } 2049 #define CP_BLIT_4_DST_Y2__MASK 0x3fff0000 2050 #define CP_BLIT_4_DST_Y2__SHIFT 16 2051 static inline uint32_t CP_BLIT_4_DST_Y2(uint32_t val) 2052 { 2053 return ((val) << CP_BLIT_4_DST_Y2__SHIFT) & CP_BLIT_4_DST_Y2__MASK; 2054 } 2055 2056 #define REG_CP_EXEC_CS_0 0x00000000 2057 2058 #define REG_CP_EXEC_CS_1 0x00000001 2059 #define CP_EXEC_CS_1_NGROUPS_X__MASK 0xffffffff 2060 #define CP_EXEC_CS_1_NGROUPS_X__SHIFT 0 2061 static inline uint32_t CP_EXEC_CS_1_NGROUPS_X(uint32_t val) 2062 { 2063 return ((val) << CP_EXEC_CS_1_NGROUPS_X__SHIFT) & CP_EXEC_CS_1_NGROUPS_X__MASK; 2064 } 2065 2066 #define REG_CP_EXEC_CS_2 0x00000002 2067 #define CP_EXEC_CS_2_NGROUPS_Y__MASK 0xffffffff 2068 #define CP_EXEC_CS_2_NGROUPS_Y__SHIFT 0 2069 static inline uint32_t CP_EXEC_CS_2_NGROUPS_Y(uint32_t val) 2070 { 2071 return ((val) << CP_EXEC_CS_2_NGROUPS_Y__SHIFT) & CP_EXEC_CS_2_NGROUPS_Y__MASK; 2072 } 2073 2074 #define REG_CP_EXEC_CS_3 0x00000003 2075 #define CP_EXEC_CS_3_NGROUPS_Z__MASK 0xffffffff 2076 #define CP_EXEC_CS_3_NGROUPS_Z__SHIFT 0 2077 static inline uint32_t CP_EXEC_CS_3_NGROUPS_Z(uint32_t val) 2078 { 2079 return ((val) << CP_EXEC_CS_3_NGROUPS_Z__SHIFT) & CP_EXEC_CS_3_NGROUPS_Z__MASK; 2080 } 2081 2082 #define REG_A4XX_CP_EXEC_CS_INDIRECT_0 0x00000000 2083 2084 2085 #define REG_A4XX_CP_EXEC_CS_INDIRECT_1 0x00000001 2086 #define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK 0xffffffff 2087 #define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT 0 2088 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_1_ADDR(uint32_t val) 2089 { 2090 return ((val) << A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK; 2091 } 2092 2093 #define REG_A4XX_CP_EXEC_CS_INDIRECT_2 0x00000002 2094 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK 0x00000ffc 2095 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT 2 2096 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX(uint32_t val) 2097 { 2098 return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK; 2099 } 2100 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK 0x003ff000 2101 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT 12 2102 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY(uint32_t val) 2103 { 2104 return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK; 2105 } 2106 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK 0xffc00000 2107 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT 22 2108 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ(uint32_t val) 2109 { 2110 return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK; 2111 } 2112 2113 2114 #define REG_A5XX_CP_EXEC_CS_INDIRECT_1 0x00000001 2115 #define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK 0xffffffff 2116 #define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT 0 2117 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO(uint32_t val) 2118 { 2119 return ((val) << A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK; 2120 } 2121 2122 #define REG_A5XX_CP_EXEC_CS_INDIRECT_2 0x00000002 2123 #define A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK 0xffffffff 2124 #define A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT 0 2125 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI(uint32_t val) 2126 { 2127 return ((val) << A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK; 2128 } 2129 2130 #define REG_A5XX_CP_EXEC_CS_INDIRECT_3 0x00000003 2131 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK 0x00000ffc 2132 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT 2 2133 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(uint32_t val) 2134 { 2135 return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK; 2136 } 2137 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK 0x003ff000 2138 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT 12 2139 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(uint32_t val) 2140 { 2141 return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK; 2142 } 2143 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK 0xffc00000 2144 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT 22 2145 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(uint32_t val) 2146 { 2147 return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK; 2148 } 2149 2150 #define REG_A6XX_CP_SET_MARKER_0 0x00000000 2151 #define A6XX_CP_SET_MARKER_0_MODE__MASK 0x000001ff 2152 #define A6XX_CP_SET_MARKER_0_MODE__SHIFT 0 2153 static inline uint32_t A6XX_CP_SET_MARKER_0_MODE(enum a6xx_render_mode val) 2154 { 2155 return ((val) << A6XX_CP_SET_MARKER_0_MODE__SHIFT) & A6XX_CP_SET_MARKER_0_MODE__MASK; 2156 } 2157 #define A6XX_CP_SET_MARKER_0_MARKER__MASK 0x0000000f 2158 #define A6XX_CP_SET_MARKER_0_MARKER__SHIFT 0 2159 static inline uint32_t A6XX_CP_SET_MARKER_0_MARKER(enum a6xx_render_mode val) 2160 { 2161 return ((val) << A6XX_CP_SET_MARKER_0_MARKER__SHIFT) & A6XX_CP_SET_MARKER_0_MARKER__MASK; 2162 } 2163 2164 static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG_(uint32_t i0) { return 0x00000000 + 0x3*i0; } 2165 2166 static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG__0(uint32_t i0) { return 0x00000000 + 0x3*i0; } 2167 #define A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK 0x00000007 2168 #define A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT 0 2169 static inline uint32_t A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG(enum pseudo_reg val) 2170 { 2171 return ((val) << A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT) & A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK; 2172 } 2173 2174 static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG__1(uint32_t i0) { return 0x00000001 + 0x3*i0; } 2175 #define A6XX_CP_SET_PSEUDO_REG__1_LO__MASK 0xffffffff 2176 #define A6XX_CP_SET_PSEUDO_REG__1_LO__SHIFT 0 2177 static inline uint32_t A6XX_CP_SET_PSEUDO_REG__1_LO(uint32_t val) 2178 { 2179 return ((val) << A6XX_CP_SET_PSEUDO_REG__1_LO__SHIFT) & A6XX_CP_SET_PSEUDO_REG__1_LO__MASK; 2180 } 2181 2182 static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG__2(uint32_t i0) { return 0x00000002 + 0x3*i0; } 2183 #define A6XX_CP_SET_PSEUDO_REG__2_HI__MASK 0xffffffff 2184 #define A6XX_CP_SET_PSEUDO_REG__2_HI__SHIFT 0 2185 static inline uint32_t A6XX_CP_SET_PSEUDO_REG__2_HI(uint32_t val) 2186 { 2187 return ((val) << A6XX_CP_SET_PSEUDO_REG__2_HI__SHIFT) & A6XX_CP_SET_PSEUDO_REG__2_HI__MASK; 2188 } 2189 2190 #define REG_A6XX_CP_REG_TEST_0 0x00000000 2191 #define A6XX_CP_REG_TEST_0_REG__MASK 0x0003ffff 2192 #define A6XX_CP_REG_TEST_0_REG__SHIFT 0 2193 static inline uint32_t A6XX_CP_REG_TEST_0_REG(uint32_t val) 2194 { 2195 return ((val) << A6XX_CP_REG_TEST_0_REG__SHIFT) & A6XX_CP_REG_TEST_0_REG__MASK; 2196 } 2197 #define A6XX_CP_REG_TEST_0_BIT__MASK 0x01f00000 2198 #define A6XX_CP_REG_TEST_0_BIT__SHIFT 20 2199 static inline uint32_t A6XX_CP_REG_TEST_0_BIT(uint32_t val) 2200 { 2201 return ((val) << A6XX_CP_REG_TEST_0_BIT__SHIFT) & A6XX_CP_REG_TEST_0_BIT__MASK; 2202 } 2203 #define A6XX_CP_REG_TEST_0_WAIT_FOR_ME 0x02000000 2204 2205 #define REG_CP_COND_REG_EXEC_0 0x00000000 2206 #define CP_COND_REG_EXEC_0_REG0__MASK 0x0003ffff 2207 #define CP_COND_REG_EXEC_0_REG0__SHIFT 0 2208 static inline uint32_t CP_COND_REG_EXEC_0_REG0(uint32_t val) 2209 { 2210 return ((val) << CP_COND_REG_EXEC_0_REG0__SHIFT) & CP_COND_REG_EXEC_0_REG0__MASK; 2211 } 2212 #define CP_COND_REG_EXEC_0_BINNING 0x02000000 2213 #define CP_COND_REG_EXEC_0_GMEM 0x04000000 2214 #define CP_COND_REG_EXEC_0_SYSMEM 0x08000000 2215 #define CP_COND_REG_EXEC_0_MODE__MASK 0xf0000000 2216 #define CP_COND_REG_EXEC_0_MODE__SHIFT 28 2217 static inline uint32_t CP_COND_REG_EXEC_0_MODE(enum compare_mode val) 2218 { 2219 return ((val) << CP_COND_REG_EXEC_0_MODE__SHIFT) & CP_COND_REG_EXEC_0_MODE__MASK; 2220 } 2221 2222 #define REG_CP_COND_REG_EXEC_1 0x00000001 2223 #define CP_COND_REG_EXEC_1_DWORDS__MASK 0xffffffff 2224 #define CP_COND_REG_EXEC_1_DWORDS__SHIFT 0 2225 static inline uint32_t CP_COND_REG_EXEC_1_DWORDS(uint32_t val) 2226 { 2227 return ((val) << CP_COND_REG_EXEC_1_DWORDS__SHIFT) & CP_COND_REG_EXEC_1_DWORDS__MASK; 2228 } 2229 2230 #define REG_CP_COND_EXEC_0 0x00000000 2231 #define CP_COND_EXEC_0_ADDR0_LO__MASK 0xffffffff 2232 #define CP_COND_EXEC_0_ADDR0_LO__SHIFT 0 2233 static inline uint32_t CP_COND_EXEC_0_ADDR0_LO(uint32_t val) 2234 { 2235 return ((val) << CP_COND_EXEC_0_ADDR0_LO__SHIFT) & CP_COND_EXEC_0_ADDR0_LO__MASK; 2236 } 2237 2238 #define REG_CP_COND_EXEC_1 0x00000001 2239 #define CP_COND_EXEC_1_ADDR0_HI__MASK 0xffffffff 2240 #define CP_COND_EXEC_1_ADDR0_HI__SHIFT 0 2241 static inline uint32_t CP_COND_EXEC_1_ADDR0_HI(uint32_t val) 2242 { 2243 return ((val) << CP_COND_EXEC_1_ADDR0_HI__SHIFT) & CP_COND_EXEC_1_ADDR0_HI__MASK; 2244 } 2245 2246 #define REG_CP_COND_EXEC_2 0x00000002 2247 #define CP_COND_EXEC_2_ADDR1_LO__MASK 0xffffffff 2248 #define CP_COND_EXEC_2_ADDR1_LO__SHIFT 0 2249 static inline uint32_t CP_COND_EXEC_2_ADDR1_LO(uint32_t val) 2250 { 2251 return ((val) << CP_COND_EXEC_2_ADDR1_LO__SHIFT) & CP_COND_EXEC_2_ADDR1_LO__MASK; 2252 } 2253 2254 #define REG_CP_COND_EXEC_3 0x00000003 2255 #define CP_COND_EXEC_3_ADDR1_HI__MASK 0xffffffff 2256 #define CP_COND_EXEC_3_ADDR1_HI__SHIFT 0 2257 static inline uint32_t CP_COND_EXEC_3_ADDR1_HI(uint32_t val) 2258 { 2259 return ((val) << CP_COND_EXEC_3_ADDR1_HI__SHIFT) & CP_COND_EXEC_3_ADDR1_HI__MASK; 2260 } 2261 2262 #define REG_CP_COND_EXEC_4 0x00000004 2263 #define CP_COND_EXEC_4_REF__MASK 0xffffffff 2264 #define CP_COND_EXEC_4_REF__SHIFT 0 2265 static inline uint32_t CP_COND_EXEC_4_REF(uint32_t val) 2266 { 2267 return ((val) << CP_COND_EXEC_4_REF__SHIFT) & CP_COND_EXEC_4_REF__MASK; 2268 } 2269 2270 #define REG_CP_COND_EXEC_5 0x00000005 2271 #define CP_COND_EXEC_5_DWORDS__MASK 0xffffffff 2272 #define CP_COND_EXEC_5_DWORDS__SHIFT 0 2273 static inline uint32_t CP_COND_EXEC_5_DWORDS(uint32_t val) 2274 { 2275 return ((val) << CP_COND_EXEC_5_DWORDS__SHIFT) & CP_COND_EXEC_5_DWORDS__MASK; 2276 } 2277 2278 #define REG_CP_SET_CTXSWITCH_IB_0 0x00000000 2279 #define CP_SET_CTXSWITCH_IB_0_ADDR_LO__MASK 0xffffffff 2280 #define CP_SET_CTXSWITCH_IB_0_ADDR_LO__SHIFT 0 2281 static inline uint32_t CP_SET_CTXSWITCH_IB_0_ADDR_LO(uint32_t val) 2282 { 2283 return ((val) << CP_SET_CTXSWITCH_IB_0_ADDR_LO__SHIFT) & CP_SET_CTXSWITCH_IB_0_ADDR_LO__MASK; 2284 } 2285 2286 #define REG_CP_SET_CTXSWITCH_IB_1 0x00000001 2287 #define CP_SET_CTXSWITCH_IB_1_ADDR_HI__MASK 0xffffffff 2288 #define CP_SET_CTXSWITCH_IB_1_ADDR_HI__SHIFT 0 2289 static inline uint32_t CP_SET_CTXSWITCH_IB_1_ADDR_HI(uint32_t val) 2290 { 2291 return ((val) << CP_SET_CTXSWITCH_IB_1_ADDR_HI__SHIFT) & CP_SET_CTXSWITCH_IB_1_ADDR_HI__MASK; 2292 } 2293 2294 #define REG_CP_SET_CTXSWITCH_IB_2 0x00000002 2295 #define CP_SET_CTXSWITCH_IB_2_DWORDS__MASK 0x000fffff 2296 #define CP_SET_CTXSWITCH_IB_2_DWORDS__SHIFT 0 2297 static inline uint32_t CP_SET_CTXSWITCH_IB_2_DWORDS(uint32_t val) 2298 { 2299 return ((val) << CP_SET_CTXSWITCH_IB_2_DWORDS__SHIFT) & CP_SET_CTXSWITCH_IB_2_DWORDS__MASK; 2300 } 2301 #define CP_SET_CTXSWITCH_IB_2_TYPE__MASK 0x00300000 2302 #define CP_SET_CTXSWITCH_IB_2_TYPE__SHIFT 20 2303 static inline uint32_t CP_SET_CTXSWITCH_IB_2_TYPE(enum ctxswitch_ib val) 2304 { 2305 return ((val) << CP_SET_CTXSWITCH_IB_2_TYPE__SHIFT) & CP_SET_CTXSWITCH_IB_2_TYPE__MASK; 2306 } 2307 2308 #define REG_CP_REG_WRITE_0 0x00000000 2309 #define CP_REG_WRITE_0_TRACKER__MASK 0x00000007 2310 #define CP_REG_WRITE_0_TRACKER__SHIFT 0 2311 static inline uint32_t CP_REG_WRITE_0_TRACKER(enum reg_tracker val) 2312 { 2313 return ((val) << CP_REG_WRITE_0_TRACKER__SHIFT) & CP_REG_WRITE_0_TRACKER__MASK; 2314 } 2315 2316 #define REG_CP_SMMU_TABLE_UPDATE_0 0x00000000 2317 #define CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__MASK 0xffffffff 2318 #define CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__SHIFT 0 2319 static inline uint32_t CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(uint32_t val) 2320 { 2321 return ((val) << CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__SHIFT) & CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__MASK; 2322 } 2323 2324 #define REG_CP_SMMU_TABLE_UPDATE_1 0x00000001 2325 #define CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__MASK 0x0000ffff 2326 #define CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__SHIFT 0 2327 static inline uint32_t CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(uint32_t val) 2328 { 2329 return ((val) << CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__SHIFT) & CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__MASK; 2330 } 2331 #define CP_SMMU_TABLE_UPDATE_1_ASID__MASK 0xffff0000 2332 #define CP_SMMU_TABLE_UPDATE_1_ASID__SHIFT 16 2333 static inline uint32_t CP_SMMU_TABLE_UPDATE_1_ASID(uint32_t val) 2334 { 2335 return ((val) << CP_SMMU_TABLE_UPDATE_1_ASID__SHIFT) & CP_SMMU_TABLE_UPDATE_1_ASID__MASK; 2336 } 2337 2338 #define REG_CP_SMMU_TABLE_UPDATE_2 0x00000002 2339 #define CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__MASK 0xffffffff 2340 #define CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__SHIFT 0 2341 static inline uint32_t CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(uint32_t val) 2342 { 2343 return ((val) << CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__SHIFT) & CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__MASK; 2344 } 2345 2346 #define REG_CP_SMMU_TABLE_UPDATE_3 0x00000003 2347 #define CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__MASK 0xffffffff 2348 #define CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__SHIFT 0 2349 static inline uint32_t CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(uint32_t val) 2350 { 2351 return ((val) << CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__SHIFT) & CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__MASK; 2352 } 2353 2354 2355 #endif /* ADRENO_PM4_XML */ 2356