1 #ifndef ADRENO_PM4_XML 2 #define ADRENO_PM4_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2013-11-30 14:47:15) 12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32814 bytes, from 2013-11-30 15:07:33) 14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 8900 bytes, from 2013-10-22 23:57:49) 15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 10574 bytes, from 2013-11-13 05:44:45) 16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 53644 bytes, from 2013-11-30 15:07:33) 17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 8344 bytes, from 2013-11-30 14:49:47) 18 19 Copyright (C) 2013 by the following authors: 20 - Rob Clark <robdclark@gmail.com> (robclark) 21 22 Permission is hereby granted, free of charge, to any person obtaining 23 a copy of this software and associated documentation files (the 24 "Software"), to deal in the Software without restriction, including 25 without limitation the rights to use, copy, modify, merge, publish, 26 distribute, sublicense, and/or sell copies of the Software, and to 27 permit persons to whom the Software is furnished to do so, subject to 28 the following conditions: 29 30 The above copyright notice and this permission notice (including the 31 next paragraph) shall be included in all copies or substantial 32 portions of the Software. 33 34 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 35 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 36 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 37 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 38 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 39 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 40 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43 44 enum vgt_event_type { 45 VS_DEALLOC = 0, 46 PS_DEALLOC = 1, 47 VS_DONE_TS = 2, 48 PS_DONE_TS = 3, 49 CACHE_FLUSH_TS = 4, 50 CONTEXT_DONE = 5, 51 CACHE_FLUSH = 6, 52 HLSQ_FLUSH = 7, 53 VIZQUERY_START = 7, 54 VIZQUERY_END = 8, 55 SC_WAIT_WC = 9, 56 RST_PIX_CNT = 13, 57 RST_VTX_CNT = 14, 58 TILE_FLUSH = 15, 59 CACHE_FLUSH_AND_INV_TS_EVENT = 20, 60 ZPASS_DONE = 21, 61 CACHE_FLUSH_AND_INV_EVENT = 22, 62 PERFCOUNTER_START = 23, 63 PERFCOUNTER_STOP = 24, 64 VS_FETCH_DONE = 27, 65 FACENESS_FLUSH = 28, 66 }; 67 68 enum pc_di_primtype { 69 DI_PT_NONE = 0, 70 DI_PT_POINTLIST_A2XX = 1, 71 DI_PT_LINELIST = 2, 72 DI_PT_LINESTRIP = 3, 73 DI_PT_TRILIST = 4, 74 DI_PT_TRIFAN = 5, 75 DI_PT_TRISTRIP = 6, 76 DI_PT_LINELOOP = 7, 77 DI_PT_RECTLIST = 8, 78 DI_PT_POINTLIST_A3XX = 9, 79 DI_PT_QUADLIST = 13, 80 DI_PT_QUADSTRIP = 14, 81 DI_PT_POLYGON = 15, 82 DI_PT_2D_COPY_RECT_LIST_V0 = 16, 83 DI_PT_2D_COPY_RECT_LIST_V1 = 17, 84 DI_PT_2D_COPY_RECT_LIST_V2 = 18, 85 DI_PT_2D_COPY_RECT_LIST_V3 = 19, 86 DI_PT_2D_FILL_RECT_LIST = 20, 87 DI_PT_2D_LINE_STRIP = 21, 88 DI_PT_2D_TRI_STRIP = 22, 89 }; 90 91 enum pc_di_src_sel { 92 DI_SRC_SEL_DMA = 0, 93 DI_SRC_SEL_IMMEDIATE = 1, 94 DI_SRC_SEL_AUTO_INDEX = 2, 95 DI_SRC_SEL_RESERVED = 3, 96 }; 97 98 enum pc_di_index_size { 99 INDEX_SIZE_IGN = 0, 100 INDEX_SIZE_16_BIT = 0, 101 INDEX_SIZE_32_BIT = 1, 102 INDEX_SIZE_8_BIT = 2, 103 INDEX_SIZE_INVALID = 0, 104 }; 105 106 enum pc_di_vis_cull_mode { 107 IGNORE_VISIBILITY = 0, 108 }; 109 110 enum adreno_pm4_packet_type { 111 CP_TYPE0_PKT = 0, 112 CP_TYPE1_PKT = 0x40000000, 113 CP_TYPE2_PKT = 0x80000000, 114 CP_TYPE3_PKT = 0xc0000000, 115 }; 116 117 enum adreno_pm4_type3_packets { 118 CP_ME_INIT = 72, 119 CP_NOP = 16, 120 CP_INDIRECT_BUFFER = 63, 121 CP_INDIRECT_BUFFER_PFD = 55, 122 CP_WAIT_FOR_IDLE = 38, 123 CP_WAIT_REG_MEM = 60, 124 CP_WAIT_REG_EQ = 82, 125 CP_WAIT_REG_GTE = 83, 126 CP_WAIT_UNTIL_READ = 92, 127 CP_WAIT_IB_PFD_COMPLETE = 93, 128 CP_REG_RMW = 33, 129 CP_SET_BIN_DATA = 47, 130 CP_REG_TO_MEM = 62, 131 CP_MEM_WRITE = 61, 132 CP_MEM_WRITE_CNTR = 79, 133 CP_COND_EXEC = 68, 134 CP_COND_WRITE = 69, 135 CP_EVENT_WRITE = 70, 136 CP_EVENT_WRITE_SHD = 88, 137 CP_EVENT_WRITE_CFL = 89, 138 CP_EVENT_WRITE_ZPD = 91, 139 CP_RUN_OPENCL = 49, 140 CP_DRAW_INDX = 34, 141 CP_DRAW_INDX_2 = 54, 142 CP_DRAW_INDX_BIN = 52, 143 CP_DRAW_INDX_2_BIN = 53, 144 CP_VIZ_QUERY = 35, 145 CP_SET_STATE = 37, 146 CP_SET_CONSTANT = 45, 147 CP_IM_LOAD = 39, 148 CP_IM_LOAD_IMMEDIATE = 43, 149 CP_LOAD_CONSTANT_CONTEXT = 46, 150 CP_INVALIDATE_STATE = 59, 151 CP_SET_SHADER_BASES = 74, 152 CP_SET_BIN_MASK = 80, 153 CP_SET_BIN_SELECT = 81, 154 CP_CONTEXT_UPDATE = 94, 155 CP_INTERRUPT = 64, 156 CP_IM_STORE = 44, 157 CP_SET_DRAW_INIT_FLAGS = 75, 158 CP_SET_PROTECTED_MODE = 95, 159 CP_LOAD_STATE = 48, 160 CP_COND_INDIRECT_BUFFER_PFE = 58, 161 CP_COND_INDIRECT_BUFFER_PFD = 50, 162 CP_INDIRECT_BUFFER_PFE = 63, 163 CP_SET_BIN = 76, 164 CP_TEST_TWO_MEMS = 113, 165 CP_WAIT_FOR_ME = 19, 166 IN_IB_PREFETCH_END = 23, 167 IN_SUBBLK_PREFETCH = 31, 168 IN_INSTR_PREFETCH = 32, 169 IN_INSTR_MATCH = 71, 170 IN_CONST_PREFETCH = 73, 171 IN_INCR_UPDT_STATE = 85, 172 IN_INCR_UPDT_CONST = 86, 173 IN_INCR_UPDT_INSTR = 87, 174 }; 175 176 enum adreno_state_block { 177 SB_VERT_TEX = 0, 178 SB_VERT_MIPADDR = 1, 179 SB_FRAG_TEX = 2, 180 SB_FRAG_MIPADDR = 3, 181 SB_VERT_SHADER = 4, 182 SB_FRAG_SHADER = 6, 183 }; 184 185 enum adreno_state_type { 186 ST_SHADER = 0, 187 ST_CONSTANTS = 1, 188 }; 189 190 enum adreno_state_src { 191 SS_DIRECT = 0, 192 SS_INDIRECT = 4, 193 }; 194 195 #define REG_CP_LOAD_STATE_0 0x00000000 196 #define CP_LOAD_STATE_0_DST_OFF__MASK 0x0000ffff 197 #define CP_LOAD_STATE_0_DST_OFF__SHIFT 0 198 static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val) 199 { 200 return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK; 201 } 202 #define CP_LOAD_STATE_0_STATE_SRC__MASK 0x00070000 203 #define CP_LOAD_STATE_0_STATE_SRC__SHIFT 16 204 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val) 205 { 206 return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK; 207 } 208 #define CP_LOAD_STATE_0_STATE_BLOCK__MASK 0x00380000 209 #define CP_LOAD_STATE_0_STATE_BLOCK__SHIFT 19 210 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val) 211 { 212 return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK; 213 } 214 #define CP_LOAD_STATE_0_NUM_UNIT__MASK 0x7fc00000 215 #define CP_LOAD_STATE_0_NUM_UNIT__SHIFT 22 216 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val) 217 { 218 return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK; 219 } 220 221 #define REG_CP_LOAD_STATE_1 0x00000001 222 #define CP_LOAD_STATE_1_STATE_TYPE__MASK 0x00000003 223 #define CP_LOAD_STATE_1_STATE_TYPE__SHIFT 0 224 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val) 225 { 226 return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK; 227 } 228 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK 0xfffffffc 229 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT 2 230 static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val) 231 { 232 return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK; 233 } 234 235 #define REG_CP_SET_BIN_0 0x00000000 236 237 #define REG_CP_SET_BIN_1 0x00000001 238 #define CP_SET_BIN_1_X1__MASK 0x0000ffff 239 #define CP_SET_BIN_1_X1__SHIFT 0 240 static inline uint32_t CP_SET_BIN_1_X1(uint32_t val) 241 { 242 return ((val) << CP_SET_BIN_1_X1__SHIFT) & CP_SET_BIN_1_X1__MASK; 243 } 244 #define CP_SET_BIN_1_Y1__MASK 0xffff0000 245 #define CP_SET_BIN_1_Y1__SHIFT 16 246 static inline uint32_t CP_SET_BIN_1_Y1(uint32_t val) 247 { 248 return ((val) << CP_SET_BIN_1_Y1__SHIFT) & CP_SET_BIN_1_Y1__MASK; 249 } 250 251 #define REG_CP_SET_BIN_2 0x00000002 252 #define CP_SET_BIN_2_X2__MASK 0x0000ffff 253 #define CP_SET_BIN_2_X2__SHIFT 0 254 static inline uint32_t CP_SET_BIN_2_X2(uint32_t val) 255 { 256 return ((val) << CP_SET_BIN_2_X2__SHIFT) & CP_SET_BIN_2_X2__MASK; 257 } 258 #define CP_SET_BIN_2_Y2__MASK 0xffff0000 259 #define CP_SET_BIN_2_Y2__SHIFT 16 260 static inline uint32_t CP_SET_BIN_2_Y2(uint32_t val) 261 { 262 return ((val) << CP_SET_BIN_2_Y2__SHIFT) & CP_SET_BIN_2_Y2__MASK; 263 } 264 265 266 #endif /* ADRENO_PM4_XML */ 267