1 #ifndef ADRENO_PM4_XML 2 #define ADRENO_PM4_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 327 bytes, from 2013-07-05 19:21:12) 12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 13 - /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml ( 31003 bytes, from 2013-09-19 18:50:16) 14 - /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml ( 8983 bytes, from 2013-07-24 01:38:36) 15 - /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 9759 bytes, from 2013-09-10 00:52:33) 16 - /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml ( 51983 bytes, from 2013-09-10 00:52:32) 17 18 Copyright (C) 2013 by the following authors: 19 - Rob Clark <robdclark@gmail.com> (robclark) 20 21 Permission is hereby granted, free of charge, to any person obtaining 22 a copy of this software and associated documentation files (the 23 "Software"), to deal in the Software without restriction, including 24 without limitation the rights to use, copy, modify, merge, publish, 25 distribute, sublicense, and/or sell copies of the Software, and to 26 permit persons to whom the Software is furnished to do so, subject to 27 the following conditions: 28 29 The above copyright notice and this permission notice (including the 30 next paragraph) shall be included in all copies or substantial 31 portions of the Software. 32 33 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 35 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 36 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 37 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 38 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 39 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 40 */ 41 42 43 enum vgt_event_type { 44 VS_DEALLOC = 0, 45 PS_DEALLOC = 1, 46 VS_DONE_TS = 2, 47 PS_DONE_TS = 3, 48 CACHE_FLUSH_TS = 4, 49 CONTEXT_DONE = 5, 50 CACHE_FLUSH = 6, 51 HLSQ_FLUSH = 7, 52 VIZQUERY_START = 7, 53 VIZQUERY_END = 8, 54 SC_WAIT_WC = 9, 55 RST_PIX_CNT = 13, 56 RST_VTX_CNT = 14, 57 TILE_FLUSH = 15, 58 CACHE_FLUSH_AND_INV_TS_EVENT = 20, 59 ZPASS_DONE = 21, 60 CACHE_FLUSH_AND_INV_EVENT = 22, 61 PERFCOUNTER_START = 23, 62 PERFCOUNTER_STOP = 24, 63 VS_FETCH_DONE = 27, 64 FACENESS_FLUSH = 28, 65 }; 66 67 enum pc_di_primtype { 68 DI_PT_NONE = 0, 69 DI_PT_POINTLIST = 1, 70 DI_PT_LINELIST = 2, 71 DI_PT_LINESTRIP = 3, 72 DI_PT_TRILIST = 4, 73 DI_PT_TRIFAN = 5, 74 DI_PT_TRISTRIP = 6, 75 DI_PT_RECTLIST = 8, 76 DI_PT_QUADLIST = 13, 77 DI_PT_QUADSTRIP = 14, 78 DI_PT_POLYGON = 15, 79 DI_PT_2D_COPY_RECT_LIST_V0 = 16, 80 DI_PT_2D_COPY_RECT_LIST_V1 = 17, 81 DI_PT_2D_COPY_RECT_LIST_V2 = 18, 82 DI_PT_2D_COPY_RECT_LIST_V3 = 19, 83 DI_PT_2D_FILL_RECT_LIST = 20, 84 DI_PT_2D_LINE_STRIP = 21, 85 DI_PT_2D_TRI_STRIP = 22, 86 }; 87 88 enum pc_di_src_sel { 89 DI_SRC_SEL_DMA = 0, 90 DI_SRC_SEL_IMMEDIATE = 1, 91 DI_SRC_SEL_AUTO_INDEX = 2, 92 DI_SRC_SEL_RESERVED = 3, 93 }; 94 95 enum pc_di_index_size { 96 INDEX_SIZE_IGN = 0, 97 INDEX_SIZE_16_BIT = 0, 98 INDEX_SIZE_32_BIT = 1, 99 INDEX_SIZE_8_BIT = 2, 100 INDEX_SIZE_INVALID = 0, 101 }; 102 103 enum pc_di_vis_cull_mode { 104 IGNORE_VISIBILITY = 0, 105 }; 106 107 enum adreno_pm4_packet_type { 108 CP_TYPE0_PKT = 0, 109 CP_TYPE1_PKT = 0x40000000, 110 CP_TYPE2_PKT = 0x80000000, 111 CP_TYPE3_PKT = 0xc0000000, 112 }; 113 114 enum adreno_pm4_type3_packets { 115 CP_ME_INIT = 72, 116 CP_NOP = 16, 117 CP_INDIRECT_BUFFER = 63, 118 CP_INDIRECT_BUFFER_PFD = 55, 119 CP_WAIT_FOR_IDLE = 38, 120 CP_WAIT_REG_MEM = 60, 121 CP_WAIT_REG_EQ = 82, 122 CP_WAT_REG_GTE = 83, 123 CP_WAIT_UNTIL_READ = 92, 124 CP_WAIT_IB_PFD_COMPLETE = 93, 125 CP_REG_RMW = 33, 126 CP_SET_BIN_DATA = 47, 127 CP_REG_TO_MEM = 62, 128 CP_MEM_WRITE = 61, 129 CP_MEM_WRITE_CNTR = 79, 130 CP_COND_EXEC = 68, 131 CP_COND_WRITE = 69, 132 CP_EVENT_WRITE = 70, 133 CP_EVENT_WRITE_SHD = 88, 134 CP_EVENT_WRITE_CFL = 89, 135 CP_EVENT_WRITE_ZPD = 91, 136 CP_RUN_OPENCL = 49, 137 CP_DRAW_INDX = 34, 138 CP_DRAW_INDX_2 = 54, 139 CP_DRAW_INDX_BIN = 52, 140 CP_DRAW_INDX_2_BIN = 53, 141 CP_VIZ_QUERY = 35, 142 CP_SET_STATE = 37, 143 CP_SET_CONSTANT = 45, 144 CP_IM_LOAD = 39, 145 CP_IM_LOAD_IMMEDIATE = 43, 146 CP_LOAD_CONSTANT_CONTEXT = 46, 147 CP_INVALIDATE_STATE = 59, 148 CP_SET_SHADER_BASES = 74, 149 CP_SET_BIN_MASK = 80, 150 CP_SET_BIN_SELECT = 81, 151 CP_CONTEXT_UPDATE = 94, 152 CP_INTERRUPT = 64, 153 CP_IM_STORE = 44, 154 CP_SET_BIN_BASE_OFFSET = 75, 155 CP_SET_DRAW_INIT_FLAGS = 75, 156 CP_SET_PROTECTED_MODE = 95, 157 CP_LOAD_STATE = 48, 158 CP_COND_INDIRECT_BUFFER_PFE = 58, 159 CP_COND_INDIRECT_BUFFER_PFD = 50, 160 CP_INDIRECT_BUFFER_PFE = 63, 161 CP_SET_BIN = 76, 162 }; 163 164 enum adreno_state_block { 165 SB_VERT_TEX = 0, 166 SB_VERT_MIPADDR = 1, 167 SB_FRAG_TEX = 2, 168 SB_FRAG_MIPADDR = 3, 169 SB_VERT_SHADER = 4, 170 SB_FRAG_SHADER = 6, 171 }; 172 173 enum adreno_state_type { 174 ST_SHADER = 0, 175 ST_CONSTANTS = 1, 176 }; 177 178 enum adreno_state_src { 179 SS_DIRECT = 0, 180 SS_INDIRECT = 4, 181 }; 182 183 #define REG_CP_LOAD_STATE_0 0x00000000 184 #define CP_LOAD_STATE_0_DST_OFF__MASK 0x0000ffff 185 #define CP_LOAD_STATE_0_DST_OFF__SHIFT 0 186 static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val) 187 { 188 return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK; 189 } 190 #define CP_LOAD_STATE_0_STATE_SRC__MASK 0x00070000 191 #define CP_LOAD_STATE_0_STATE_SRC__SHIFT 16 192 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val) 193 { 194 return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK; 195 } 196 #define CP_LOAD_STATE_0_STATE_BLOCK__MASK 0x00380000 197 #define CP_LOAD_STATE_0_STATE_BLOCK__SHIFT 19 198 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val) 199 { 200 return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK; 201 } 202 #define CP_LOAD_STATE_0_NUM_UNIT__MASK 0x7fc00000 203 #define CP_LOAD_STATE_0_NUM_UNIT__SHIFT 22 204 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val) 205 { 206 return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK; 207 } 208 209 #define REG_CP_LOAD_STATE_1 0x00000001 210 #define CP_LOAD_STATE_1_STATE_TYPE__MASK 0x00000003 211 #define CP_LOAD_STATE_1_STATE_TYPE__SHIFT 0 212 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val) 213 { 214 return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK; 215 } 216 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK 0xfffffffc 217 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT 2 218 static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val) 219 { 220 return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK; 221 } 222 223 #define REG_CP_SET_BIN_0 0x00000000 224 225 #define REG_CP_SET_BIN_1 0x00000001 226 #define CP_SET_BIN_1_X1__MASK 0x0000ffff 227 #define CP_SET_BIN_1_X1__SHIFT 0 228 static inline uint32_t CP_SET_BIN_1_X1(uint32_t val) 229 { 230 return ((val) << CP_SET_BIN_1_X1__SHIFT) & CP_SET_BIN_1_X1__MASK; 231 } 232 #define CP_SET_BIN_1_Y1__MASK 0xffff0000 233 #define CP_SET_BIN_1_Y1__SHIFT 16 234 static inline uint32_t CP_SET_BIN_1_Y1(uint32_t val) 235 { 236 return ((val) << CP_SET_BIN_1_Y1__SHIFT) & CP_SET_BIN_1_Y1__MASK; 237 } 238 239 #define REG_CP_SET_BIN_2 0x00000002 240 #define CP_SET_BIN_2_X2__MASK 0x0000ffff 241 #define CP_SET_BIN_2_X2__SHIFT 0 242 static inline uint32_t CP_SET_BIN_2_X2(uint32_t val) 243 { 244 return ((val) << CP_SET_BIN_2_X2__SHIFT) & CP_SET_BIN_2_X2__MASK; 245 } 246 #define CP_SET_BIN_2_Y2__MASK 0xffff0000 247 #define CP_SET_BIN_2_Y2__SHIFT 16 248 static inline uint32_t CP_SET_BIN_2_Y2(uint32_t val) 249 { 250 return ((val) << CP_SET_BIN_2_Y2__SHIFT) & CP_SET_BIN_2_Y2__MASK; 251 } 252 253 254 #endif /* ADRENO_PM4_XML */ 255