1 #ifndef ADRENO_PM4_XML 2 #define ADRENO_PM4_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2013-11-30 14:47:15) 12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2014-06-02 15:21:30) 14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2014-11-13 22:44:30) 15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 15085 bytes, from 2014-12-20 21:49:41) 16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 64344 bytes, from 2014-12-12 20:22:26) 17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 51069 bytes, from 2014-12-21 15:51:54) 18 19 Copyright (C) 2013-2014 by the following authors: 20 - Rob Clark <robdclark@gmail.com> (robclark) 21 22 Permission is hereby granted, free of charge, to any person obtaining 23 a copy of this software and associated documentation files (the 24 "Software"), to deal in the Software without restriction, including 25 without limitation the rights to use, copy, modify, merge, publish, 26 distribute, sublicense, and/or sell copies of the Software, and to 27 permit persons to whom the Software is furnished to do so, subject to 28 the following conditions: 29 30 The above copyright notice and this permission notice (including the 31 next paragraph) shall be included in all copies or substantial 32 portions of the Software. 33 34 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 35 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 36 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 37 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 38 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 39 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 40 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43 44 enum vgt_event_type { 45 VS_DEALLOC = 0, 46 PS_DEALLOC = 1, 47 VS_DONE_TS = 2, 48 PS_DONE_TS = 3, 49 CACHE_FLUSH_TS = 4, 50 CONTEXT_DONE = 5, 51 CACHE_FLUSH = 6, 52 HLSQ_FLUSH = 7, 53 VIZQUERY_START = 7, 54 VIZQUERY_END = 8, 55 SC_WAIT_WC = 9, 56 RST_PIX_CNT = 13, 57 RST_VTX_CNT = 14, 58 TILE_FLUSH = 15, 59 CACHE_FLUSH_AND_INV_TS_EVENT = 20, 60 ZPASS_DONE = 21, 61 CACHE_FLUSH_AND_INV_EVENT = 22, 62 PERFCOUNTER_START = 23, 63 PERFCOUNTER_STOP = 24, 64 VS_FETCH_DONE = 27, 65 FACENESS_FLUSH = 28, 66 }; 67 68 enum pc_di_primtype { 69 DI_PT_NONE = 0, 70 DI_PT_POINTLIST_A2XX = 1, 71 DI_PT_LINELIST = 2, 72 DI_PT_LINESTRIP = 3, 73 DI_PT_TRILIST = 4, 74 DI_PT_TRIFAN = 5, 75 DI_PT_TRISTRIP = 6, 76 DI_PT_LINELOOP = 7, 77 DI_PT_RECTLIST = 8, 78 DI_PT_POINTLIST_A3XX = 9, 79 DI_PT_QUADLIST = 13, 80 DI_PT_QUADSTRIP = 14, 81 DI_PT_POLYGON = 15, 82 DI_PT_2D_COPY_RECT_LIST_V0 = 16, 83 DI_PT_2D_COPY_RECT_LIST_V1 = 17, 84 DI_PT_2D_COPY_RECT_LIST_V2 = 18, 85 DI_PT_2D_COPY_RECT_LIST_V3 = 19, 86 DI_PT_2D_FILL_RECT_LIST = 20, 87 DI_PT_2D_LINE_STRIP = 21, 88 DI_PT_2D_TRI_STRIP = 22, 89 }; 90 91 enum pc_di_src_sel { 92 DI_SRC_SEL_DMA = 0, 93 DI_SRC_SEL_IMMEDIATE = 1, 94 DI_SRC_SEL_AUTO_INDEX = 2, 95 DI_SRC_SEL_RESERVED = 3, 96 }; 97 98 enum pc_di_index_size { 99 INDEX_SIZE_IGN = 0, 100 INDEX_SIZE_16_BIT = 0, 101 INDEX_SIZE_32_BIT = 1, 102 INDEX_SIZE_8_BIT = 2, 103 INDEX_SIZE_INVALID = 0, 104 }; 105 106 enum pc_di_vis_cull_mode { 107 IGNORE_VISIBILITY = 0, 108 USE_VISIBILITY = 1, 109 }; 110 111 enum adreno_pm4_packet_type { 112 CP_TYPE0_PKT = 0, 113 CP_TYPE1_PKT = 0x40000000, 114 CP_TYPE2_PKT = 0x80000000, 115 CP_TYPE3_PKT = 0xc0000000, 116 }; 117 118 enum adreno_pm4_type3_packets { 119 CP_ME_INIT = 72, 120 CP_NOP = 16, 121 CP_INDIRECT_BUFFER = 63, 122 CP_INDIRECT_BUFFER_PFD = 55, 123 CP_WAIT_FOR_IDLE = 38, 124 CP_WAIT_REG_MEM = 60, 125 CP_WAIT_REG_EQ = 82, 126 CP_WAIT_REG_GTE = 83, 127 CP_WAIT_UNTIL_READ = 92, 128 CP_WAIT_IB_PFD_COMPLETE = 93, 129 CP_REG_RMW = 33, 130 CP_SET_BIN_DATA = 47, 131 CP_REG_TO_MEM = 62, 132 CP_MEM_WRITE = 61, 133 CP_MEM_WRITE_CNTR = 79, 134 CP_COND_EXEC = 68, 135 CP_COND_WRITE = 69, 136 CP_EVENT_WRITE = 70, 137 CP_EVENT_WRITE_SHD = 88, 138 CP_EVENT_WRITE_CFL = 89, 139 CP_EVENT_WRITE_ZPD = 91, 140 CP_RUN_OPENCL = 49, 141 CP_DRAW_INDX = 34, 142 CP_DRAW_INDX_2 = 54, 143 CP_DRAW_INDX_BIN = 52, 144 CP_DRAW_INDX_2_BIN = 53, 145 CP_VIZ_QUERY = 35, 146 CP_SET_STATE = 37, 147 CP_SET_CONSTANT = 45, 148 CP_IM_LOAD = 39, 149 CP_IM_LOAD_IMMEDIATE = 43, 150 CP_LOAD_CONSTANT_CONTEXT = 46, 151 CP_INVALIDATE_STATE = 59, 152 CP_SET_SHADER_BASES = 74, 153 CP_SET_BIN_MASK = 80, 154 CP_SET_BIN_SELECT = 81, 155 CP_CONTEXT_UPDATE = 94, 156 CP_INTERRUPT = 64, 157 CP_IM_STORE = 44, 158 CP_SET_DRAW_INIT_FLAGS = 75, 159 CP_SET_PROTECTED_MODE = 95, 160 CP_BOOTSTRAP_UCODE = 111, 161 CP_LOAD_STATE = 48, 162 CP_COND_INDIRECT_BUFFER_PFE = 58, 163 CP_COND_INDIRECT_BUFFER_PFD = 50, 164 CP_INDIRECT_BUFFER_PFE = 63, 165 CP_SET_BIN = 76, 166 CP_TEST_TWO_MEMS = 113, 167 CP_REG_WR_NO_CTXT = 120, 168 CP_RECORD_PFP_TIMESTAMP = 17, 169 CP_WAIT_FOR_ME = 19, 170 CP_SET_DRAW_STATE = 67, 171 CP_DRAW_INDX_OFFSET = 56, 172 CP_DRAW_INDIRECT = 40, 173 CP_DRAW_INDX_INDIRECT = 41, 174 CP_DRAW_AUTO = 36, 175 CP_UNKNOWN_19 = 25, 176 CP_UNKNOWN_1A = 26, 177 CP_UNKNOWN_4E = 78, 178 CP_WIDE_REG_WRITE = 116, 179 IN_IB_PREFETCH_END = 23, 180 IN_SUBBLK_PREFETCH = 31, 181 IN_INSTR_PREFETCH = 32, 182 IN_INSTR_MATCH = 71, 183 IN_CONST_PREFETCH = 73, 184 IN_INCR_UPDT_STATE = 85, 185 IN_INCR_UPDT_CONST = 86, 186 IN_INCR_UPDT_INSTR = 87, 187 }; 188 189 enum adreno_state_block { 190 SB_VERT_TEX = 0, 191 SB_VERT_MIPADDR = 1, 192 SB_FRAG_TEX = 2, 193 SB_FRAG_MIPADDR = 3, 194 SB_VERT_SHADER = 4, 195 SB_FRAG_SHADER = 6, 196 }; 197 198 enum adreno_state_type { 199 ST_SHADER = 0, 200 ST_CONSTANTS = 1, 201 }; 202 203 enum adreno_state_src { 204 SS_DIRECT = 0, 205 SS_INDIRECT = 4, 206 }; 207 208 enum a4xx_index_size { 209 INDEX4_SIZE_8_BIT = 0, 210 INDEX4_SIZE_16_BIT = 1, 211 INDEX4_SIZE_32_BIT = 2, 212 }; 213 214 #define REG_CP_LOAD_STATE_0 0x00000000 215 #define CP_LOAD_STATE_0_DST_OFF__MASK 0x0000ffff 216 #define CP_LOAD_STATE_0_DST_OFF__SHIFT 0 217 static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val) 218 { 219 return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK; 220 } 221 #define CP_LOAD_STATE_0_STATE_SRC__MASK 0x00070000 222 #define CP_LOAD_STATE_0_STATE_SRC__SHIFT 16 223 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val) 224 { 225 return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK; 226 } 227 #define CP_LOAD_STATE_0_STATE_BLOCK__MASK 0x00380000 228 #define CP_LOAD_STATE_0_STATE_BLOCK__SHIFT 19 229 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val) 230 { 231 return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK; 232 } 233 #define CP_LOAD_STATE_0_NUM_UNIT__MASK 0x7fc00000 234 #define CP_LOAD_STATE_0_NUM_UNIT__SHIFT 22 235 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val) 236 { 237 return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK; 238 } 239 240 #define REG_CP_LOAD_STATE_1 0x00000001 241 #define CP_LOAD_STATE_1_STATE_TYPE__MASK 0x00000003 242 #define CP_LOAD_STATE_1_STATE_TYPE__SHIFT 0 243 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val) 244 { 245 return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK; 246 } 247 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK 0xfffffffc 248 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT 2 249 static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val) 250 { 251 return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK; 252 } 253 254 #define REG_CP_DRAW_INDX_0 0x00000000 255 #define CP_DRAW_INDX_0_VIZ_QUERY__MASK 0xffffffff 256 #define CP_DRAW_INDX_0_VIZ_QUERY__SHIFT 0 257 static inline uint32_t CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val) 258 { 259 return ((val) << CP_DRAW_INDX_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_0_VIZ_QUERY__MASK; 260 } 261 262 #define REG_CP_DRAW_INDX_1 0x00000001 263 #define CP_DRAW_INDX_1_PRIM_TYPE__MASK 0x0000003f 264 #define CP_DRAW_INDX_1_PRIM_TYPE__SHIFT 0 265 static inline uint32_t CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val) 266 { 267 return ((val) << CP_DRAW_INDX_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_1_PRIM_TYPE__MASK; 268 } 269 #define CP_DRAW_INDX_1_SOURCE_SELECT__MASK 0x000000c0 270 #define CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT 6 271 static inline uint32_t CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val) 272 { 273 return ((val) << CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_1_SOURCE_SELECT__MASK; 274 } 275 #define CP_DRAW_INDX_1_VIS_CULL__MASK 0x00000600 276 #define CP_DRAW_INDX_1_VIS_CULL__SHIFT 9 277 static inline uint32_t CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val) 278 { 279 return ((val) << CP_DRAW_INDX_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_1_VIS_CULL__MASK; 280 } 281 #define CP_DRAW_INDX_1_INDEX_SIZE__MASK 0x00000800 282 #define CP_DRAW_INDX_1_INDEX_SIZE__SHIFT 11 283 static inline uint32_t CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val) 284 { 285 return ((val) << CP_DRAW_INDX_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_1_INDEX_SIZE__MASK; 286 } 287 #define CP_DRAW_INDX_1_NOT_EOP 0x00001000 288 #define CP_DRAW_INDX_1_SMALL_INDEX 0x00002000 289 #define CP_DRAW_INDX_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000 290 #define CP_DRAW_INDX_1_NUM_INSTANCES__MASK 0xff000000 291 #define CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT 24 292 static inline uint32_t CP_DRAW_INDX_1_NUM_INSTANCES(uint32_t val) 293 { 294 return ((val) << CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_1_NUM_INSTANCES__MASK; 295 } 296 297 #define REG_CP_DRAW_INDX_2 0x00000002 298 #define CP_DRAW_INDX_2_NUM_INDICES__MASK 0xffffffff 299 #define CP_DRAW_INDX_2_NUM_INDICES__SHIFT 0 300 static inline uint32_t CP_DRAW_INDX_2_NUM_INDICES(uint32_t val) 301 { 302 return ((val) << CP_DRAW_INDX_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_NUM_INDICES__MASK; 303 } 304 305 #define REG_CP_DRAW_INDX_3 0x00000003 306 #define CP_DRAW_INDX_3_INDX_BASE__MASK 0xffffffff 307 #define CP_DRAW_INDX_3_INDX_BASE__SHIFT 0 308 static inline uint32_t CP_DRAW_INDX_3_INDX_BASE(uint32_t val) 309 { 310 return ((val) << CP_DRAW_INDX_3_INDX_BASE__SHIFT) & CP_DRAW_INDX_3_INDX_BASE__MASK; 311 } 312 313 #define REG_CP_DRAW_INDX_4 0x00000004 314 #define CP_DRAW_INDX_4_INDX_SIZE__MASK 0xffffffff 315 #define CP_DRAW_INDX_4_INDX_SIZE__SHIFT 0 316 static inline uint32_t CP_DRAW_INDX_4_INDX_SIZE(uint32_t val) 317 { 318 return ((val) << CP_DRAW_INDX_4_INDX_SIZE__SHIFT) & CP_DRAW_INDX_4_INDX_SIZE__MASK; 319 } 320 321 #define REG_CP_DRAW_INDX_2_0 0x00000000 322 #define CP_DRAW_INDX_2_0_VIZ_QUERY__MASK 0xffffffff 323 #define CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT 0 324 static inline uint32_t CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val) 325 { 326 return ((val) << CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_2_0_VIZ_QUERY__MASK; 327 } 328 329 #define REG_CP_DRAW_INDX_2_1 0x00000001 330 #define CP_DRAW_INDX_2_1_PRIM_TYPE__MASK 0x0000003f 331 #define CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT 0 332 static inline uint32_t CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val) 333 { 334 return ((val) << CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_2_1_PRIM_TYPE__MASK; 335 } 336 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK 0x000000c0 337 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT 6 338 static inline uint32_t CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val) 339 { 340 return ((val) << CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK; 341 } 342 #define CP_DRAW_INDX_2_1_VIS_CULL__MASK 0x00000600 343 #define CP_DRAW_INDX_2_1_VIS_CULL__SHIFT 9 344 static inline uint32_t CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val) 345 { 346 return ((val) << CP_DRAW_INDX_2_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_2_1_VIS_CULL__MASK; 347 } 348 #define CP_DRAW_INDX_2_1_INDEX_SIZE__MASK 0x00000800 349 #define CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT 11 350 static inline uint32_t CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val) 351 { 352 return ((val) << CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_2_1_INDEX_SIZE__MASK; 353 } 354 #define CP_DRAW_INDX_2_1_NOT_EOP 0x00001000 355 #define CP_DRAW_INDX_2_1_SMALL_INDEX 0x00002000 356 #define CP_DRAW_INDX_2_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000 357 #define CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK 0xff000000 358 #define CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT 24 359 static inline uint32_t CP_DRAW_INDX_2_1_NUM_INSTANCES(uint32_t val) 360 { 361 return ((val) << CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK; 362 } 363 364 #define REG_CP_DRAW_INDX_2_2 0x00000002 365 #define CP_DRAW_INDX_2_2_NUM_INDICES__MASK 0xffffffff 366 #define CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT 0 367 static inline uint32_t CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val) 368 { 369 return ((val) << CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_2_NUM_INDICES__MASK; 370 } 371 372 #define REG_CP_DRAW_INDX_OFFSET_0 0x00000000 373 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK 0x0000003f 374 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT 0 375 static inline uint32_t CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val) 376 { 377 return ((val) << CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK; 378 } 379 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK 0x000000c0 380 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT 6 381 static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val) 382 { 383 return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK; 384 } 385 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK 0x00000c00 386 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT 10 387 static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val) 388 { 389 return ((val) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK; 390 } 391 392 #define REG_CP_DRAW_INDX_OFFSET_1 0x00000001 393 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK 0xffffffff 394 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT 0 395 static inline uint32_t CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES(uint32_t val) 396 { 397 return ((val) << CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK; 398 } 399 400 #define REG_CP_DRAW_INDX_OFFSET_2 0x00000002 401 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK 0xffffffff 402 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT 0 403 static inline uint32_t CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val) 404 { 405 return ((val) << CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK; 406 } 407 408 #define REG_CP_DRAW_INDX_OFFSET_3 0x00000003 409 410 #define REG_CP_DRAW_INDX_OFFSET_4 0x00000004 411 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK 0xffffffff 412 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT 0 413 static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE(uint32_t val) 414 { 415 return ((val) << CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK; 416 } 417 418 #define REG_CP_DRAW_INDX_OFFSET_5 0x00000005 419 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK 0xffffffff 420 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT 0 421 static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_SIZE(uint32_t val) 422 { 423 return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK; 424 } 425 426 #define REG_CP_SET_DRAW_STATE_0 0x00000000 427 #define CP_SET_DRAW_STATE_0_COUNT__MASK 0x0000ffff 428 #define CP_SET_DRAW_STATE_0_COUNT__SHIFT 0 429 static inline uint32_t CP_SET_DRAW_STATE_0_COUNT(uint32_t val) 430 { 431 return ((val) << CP_SET_DRAW_STATE_0_COUNT__SHIFT) & CP_SET_DRAW_STATE_0_COUNT__MASK; 432 } 433 #define CP_SET_DRAW_STATE_0_DIRTY 0x00010000 434 #define CP_SET_DRAW_STATE_0_DISABLE 0x00020000 435 #define CP_SET_DRAW_STATE_0_DISABLE_ALL_GROUPS 0x00040000 436 #define CP_SET_DRAW_STATE_0_LOAD_IMMED 0x00080000 437 #define CP_SET_DRAW_STATE_0_GROUP_ID__MASK 0x1f000000 438 #define CP_SET_DRAW_STATE_0_GROUP_ID__SHIFT 24 439 static inline uint32_t CP_SET_DRAW_STATE_0_GROUP_ID(uint32_t val) 440 { 441 return ((val) << CP_SET_DRAW_STATE_0_GROUP_ID__SHIFT) & CP_SET_DRAW_STATE_0_GROUP_ID__MASK; 442 } 443 444 #define REG_CP_SET_DRAW_STATE_1 0x00000001 445 #define CP_SET_DRAW_STATE_1_ADDR__MASK 0xffffffff 446 #define CP_SET_DRAW_STATE_1_ADDR__SHIFT 0 447 static inline uint32_t CP_SET_DRAW_STATE_1_ADDR(uint32_t val) 448 { 449 return ((val) << CP_SET_DRAW_STATE_1_ADDR__SHIFT) & CP_SET_DRAW_STATE_1_ADDR__MASK; 450 } 451 452 #define REG_CP_SET_BIN_0 0x00000000 453 454 #define REG_CP_SET_BIN_1 0x00000001 455 #define CP_SET_BIN_1_X1__MASK 0x0000ffff 456 #define CP_SET_BIN_1_X1__SHIFT 0 457 static inline uint32_t CP_SET_BIN_1_X1(uint32_t val) 458 { 459 return ((val) << CP_SET_BIN_1_X1__SHIFT) & CP_SET_BIN_1_X1__MASK; 460 } 461 #define CP_SET_BIN_1_Y1__MASK 0xffff0000 462 #define CP_SET_BIN_1_Y1__SHIFT 16 463 static inline uint32_t CP_SET_BIN_1_Y1(uint32_t val) 464 { 465 return ((val) << CP_SET_BIN_1_Y1__SHIFT) & CP_SET_BIN_1_Y1__MASK; 466 } 467 468 #define REG_CP_SET_BIN_2 0x00000002 469 #define CP_SET_BIN_2_X2__MASK 0x0000ffff 470 #define CP_SET_BIN_2_X2__SHIFT 0 471 static inline uint32_t CP_SET_BIN_2_X2(uint32_t val) 472 { 473 return ((val) << CP_SET_BIN_2_X2__SHIFT) & CP_SET_BIN_2_X2__MASK; 474 } 475 #define CP_SET_BIN_2_Y2__MASK 0xffff0000 476 #define CP_SET_BIN_2_Y2__SHIFT 16 477 static inline uint32_t CP_SET_BIN_2_Y2(uint32_t val) 478 { 479 return ((val) << CP_SET_BIN_2_Y2__SHIFT) & CP_SET_BIN_2_Y2__MASK; 480 } 481 482 #define REG_CP_SET_BIN_DATA_0 0x00000000 483 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK 0xffffffff 484 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT 0 485 static inline uint32_t CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val) 486 { 487 return ((val) << CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT) & CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK; 488 } 489 490 #define REG_CP_SET_BIN_DATA_1 0x00000001 491 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK 0xffffffff 492 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT 0 493 static inline uint32_t CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val) 494 { 495 return ((val) << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK; 496 } 497 498 499 #endif /* ADRENO_PM4_XML */ 500