1 #ifndef ADRENO_PM4_XML
2 #define ADRENO_PM4_XML
3 
4 /* Autogenerated file, DO NOT EDIT manually!
5 
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
9 
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml                     (    594 bytes, from 2023-03-10 18:32:52)
12 - /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml        (   1572 bytes, from 2022-07-23 20:21:46)
13 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml                (  91929 bytes, from 2023-02-28 23:52:27)
14 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml       (  15434 bytes, from 2023-03-10 18:32:53)
15 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml          (  74995 bytes, from 2023-03-20 18:06:23)
16 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml                (  84231 bytes, from 2022-08-02 16:38:43)
17 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml                ( 113474 bytes, from 2022-08-02 16:38:43)
18 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml                ( 149590 bytes, from 2023-02-14 19:37:12)
19 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml                ( 198949 bytes, from 2023-03-20 18:06:23)
20 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml            (  11404 bytes, from 2023-03-10 18:32:53)
21 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml               (   1773 bytes, from 2022-08-02 16:38:43)
22 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml (   9055 bytes, from 2023-03-10 18:32:52)
23 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml    (   2976 bytes, from 2023-03-10 18:32:52)
24 
25 Copyright (C) 2013-2023 by the following authors:
26 - Rob Clark <robdclark@gmail.com> (robclark)
27 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
28 
29 Permission is hereby granted, free of charge, to any person obtaining
30 a copy of this software and associated documentation files (the
31 "Software"), to deal in the Software without restriction, including
32 without limitation the rights to use, copy, modify, merge, publish,
33 distribute, sublicense, and/or sell copies of the Software, and to
34 permit persons to whom the Software is furnished to do so, subject to
35 the following conditions:
36 
37 The above copyright notice and this permission notice (including the
38 next paragraph) shall be included in all copies or substantial
39 portions of the Software.
40 
41 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
42 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
43 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
44 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
45 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
46 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
47 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
48 */
49 
50 
51 enum vgt_event_type {
52 	VS_DEALLOC = 0,
53 	PS_DEALLOC = 1,
54 	VS_DONE_TS = 2,
55 	PS_DONE_TS = 3,
56 	CACHE_FLUSH_TS = 4,
57 	CONTEXT_DONE = 5,
58 	CACHE_FLUSH = 6,
59 	VIZQUERY_START = 7,
60 	HLSQ_FLUSH = 7,
61 	VIZQUERY_END = 8,
62 	SC_WAIT_WC = 9,
63 	WRITE_PRIMITIVE_COUNTS = 9,
64 	START_PRIMITIVE_CTRS = 11,
65 	STOP_PRIMITIVE_CTRS = 12,
66 	RST_PIX_CNT = 13,
67 	RST_VTX_CNT = 14,
68 	TILE_FLUSH = 15,
69 	STAT_EVENT = 16,
70 	CACHE_FLUSH_AND_INV_TS_EVENT = 20,
71 	ZPASS_DONE = 21,
72 	CACHE_FLUSH_AND_INV_EVENT = 22,
73 	RB_DONE_TS = 22,
74 	PERFCOUNTER_START = 23,
75 	PERFCOUNTER_STOP = 24,
76 	VS_FETCH_DONE = 27,
77 	FACENESS_FLUSH = 28,
78 	WT_DONE_TS = 8,
79 	START_FRAGMENT_CTRS = 13,
80 	STOP_FRAGMENT_CTRS = 14,
81 	START_COMPUTE_CTRS = 15,
82 	STOP_COMPUTE_CTRS = 16,
83 	FLUSH_SO_0 = 17,
84 	FLUSH_SO_1 = 18,
85 	FLUSH_SO_2 = 19,
86 	FLUSH_SO_3 = 20,
87 	PC_CCU_INVALIDATE_DEPTH = 24,
88 	PC_CCU_INVALIDATE_COLOR = 25,
89 	PC_CCU_RESOLVE_TS = 26,
90 	PC_CCU_FLUSH_DEPTH_TS = 28,
91 	PC_CCU_FLUSH_COLOR_TS = 29,
92 	BLIT = 30,
93 	LRZ_CLEAR = 37,
94 	LRZ_FLUSH = 38,
95 	BLIT_OP_FILL_2D = 39,
96 	BLIT_OP_COPY_2D = 40,
97 	BLIT_OP_SCALE_2D = 42,
98 	CONTEXT_DONE_2D = 43,
99 	UNK_2C = 44,
100 	UNK_2D = 45,
101 	CACHE_INVALIDATE = 49,
102 	LABEL = 63,
103 	CCU_INVALIDATE_DEPTH = 24,
104 	CCU_INVALIDATE_COLOR = 25,
105 	CCU_RESOLVE_CLEAN = 26,
106 	CCU_FLUSH_DEPTH = 28,
107 	CCU_FLUSH_COLOR = 29,
108 	CCU_RESOLVE = 30,
109 	CCU_END_RESOLVE_GROUP = 31,
110 	CCU_CLEAN_DEPTH = 32,
111 	CCU_CLEAN_COLOR = 33,
112 	CACHE_RESET = 48,
113 	CACHE_CLEAN = 49,
114 	CACHE_FLUSH7 = 50,
115 	CACHE_INVALIDATE7 = 51,
116 };
117 
118 enum pc_di_primtype {
119 	DI_PT_NONE = 0,
120 	DI_PT_POINTLIST_PSIZE = 1,
121 	DI_PT_LINELIST = 2,
122 	DI_PT_LINESTRIP = 3,
123 	DI_PT_TRILIST = 4,
124 	DI_PT_TRIFAN = 5,
125 	DI_PT_TRISTRIP = 6,
126 	DI_PT_LINELOOP = 7,
127 	DI_PT_RECTLIST = 8,
128 	DI_PT_POINTLIST = 9,
129 	DI_PT_LINE_ADJ = 10,
130 	DI_PT_LINESTRIP_ADJ = 11,
131 	DI_PT_TRI_ADJ = 12,
132 	DI_PT_TRISTRIP_ADJ = 13,
133 	DI_PT_PATCHES0 = 31,
134 	DI_PT_PATCHES1 = 32,
135 	DI_PT_PATCHES2 = 33,
136 	DI_PT_PATCHES3 = 34,
137 	DI_PT_PATCHES4 = 35,
138 	DI_PT_PATCHES5 = 36,
139 	DI_PT_PATCHES6 = 37,
140 	DI_PT_PATCHES7 = 38,
141 	DI_PT_PATCHES8 = 39,
142 	DI_PT_PATCHES9 = 40,
143 	DI_PT_PATCHES10 = 41,
144 	DI_PT_PATCHES11 = 42,
145 	DI_PT_PATCHES12 = 43,
146 	DI_PT_PATCHES13 = 44,
147 	DI_PT_PATCHES14 = 45,
148 	DI_PT_PATCHES15 = 46,
149 	DI_PT_PATCHES16 = 47,
150 	DI_PT_PATCHES17 = 48,
151 	DI_PT_PATCHES18 = 49,
152 	DI_PT_PATCHES19 = 50,
153 	DI_PT_PATCHES20 = 51,
154 	DI_PT_PATCHES21 = 52,
155 	DI_PT_PATCHES22 = 53,
156 	DI_PT_PATCHES23 = 54,
157 	DI_PT_PATCHES24 = 55,
158 	DI_PT_PATCHES25 = 56,
159 	DI_PT_PATCHES26 = 57,
160 	DI_PT_PATCHES27 = 58,
161 	DI_PT_PATCHES28 = 59,
162 	DI_PT_PATCHES29 = 60,
163 	DI_PT_PATCHES30 = 61,
164 	DI_PT_PATCHES31 = 62,
165 };
166 
167 enum pc_di_src_sel {
168 	DI_SRC_SEL_DMA = 0,
169 	DI_SRC_SEL_IMMEDIATE = 1,
170 	DI_SRC_SEL_AUTO_INDEX = 2,
171 	DI_SRC_SEL_AUTO_XFB = 3,
172 };
173 
174 enum pc_di_face_cull_sel {
175 	DI_FACE_CULL_NONE = 0,
176 	DI_FACE_CULL_FETCH = 1,
177 	DI_FACE_BACKFACE_CULL = 2,
178 	DI_FACE_FRONTFACE_CULL = 3,
179 };
180 
181 enum pc_di_index_size {
182 	INDEX_SIZE_IGN = 0,
183 	INDEX_SIZE_16_BIT = 0,
184 	INDEX_SIZE_32_BIT = 1,
185 	INDEX_SIZE_8_BIT = 2,
186 	INDEX_SIZE_INVALID = 0,
187 };
188 
189 enum pc_di_vis_cull_mode {
190 	IGNORE_VISIBILITY = 0,
191 	USE_VISIBILITY = 1,
192 };
193 
194 enum adreno_pm4_packet_type {
195 	CP_TYPE0_PKT = 0,
196 	CP_TYPE1_PKT = 0x40000000,
197 	CP_TYPE2_PKT = 0x80000000,
198 	CP_TYPE3_PKT = 0xc0000000,
199 	CP_TYPE4_PKT = 0x40000000,
200 	CP_TYPE7_PKT = 0x70000000,
201 };
202 
203 enum adreno_pm4_type3_packets {
204 	CP_ME_INIT = 72,
205 	CP_NOP = 16,
206 	CP_PREEMPT_ENABLE = 28,
207 	CP_PREEMPT_TOKEN = 30,
208 	CP_INDIRECT_BUFFER = 63,
209 	CP_INDIRECT_BUFFER_CHAIN = 87,
210 	CP_INDIRECT_BUFFER_PFD = 55,
211 	CP_WAIT_FOR_IDLE = 38,
212 	CP_WAIT_REG_MEM = 60,
213 	CP_WAIT_REG_EQ = 82,
214 	CP_WAIT_REG_GTE = 83,
215 	CP_WAIT_UNTIL_READ = 92,
216 	CP_WAIT_IB_PFD_COMPLETE = 93,
217 	CP_REG_RMW = 33,
218 	CP_SET_BIN_DATA = 47,
219 	CP_SET_BIN_DATA5 = 47,
220 	CP_REG_TO_MEM = 62,
221 	CP_MEM_WRITE = 61,
222 	CP_MEM_WRITE_CNTR = 79,
223 	CP_COND_EXEC = 68,
224 	CP_COND_WRITE = 69,
225 	CP_COND_WRITE5 = 69,
226 	CP_EVENT_WRITE = 70,
227 	CP_EVENT_WRITE_SHD = 88,
228 	CP_EVENT_WRITE_CFL = 89,
229 	CP_EVENT_WRITE_ZPD = 91,
230 	CP_RUN_OPENCL = 49,
231 	CP_DRAW_INDX = 34,
232 	CP_DRAW_INDX_2 = 54,
233 	CP_DRAW_INDX_BIN = 52,
234 	CP_DRAW_INDX_2_BIN = 53,
235 	CP_VIZ_QUERY = 35,
236 	CP_SET_STATE = 37,
237 	CP_SET_CONSTANT = 45,
238 	CP_IM_LOAD = 39,
239 	CP_IM_LOAD_IMMEDIATE = 43,
240 	CP_LOAD_CONSTANT_CONTEXT = 46,
241 	CP_INVALIDATE_STATE = 59,
242 	CP_SET_SHADER_BASES = 74,
243 	CP_SET_BIN_MASK = 80,
244 	CP_SET_BIN_SELECT = 81,
245 	CP_CONTEXT_UPDATE = 94,
246 	CP_INTERRUPT = 64,
247 	CP_IM_STORE = 44,
248 	CP_SET_DRAW_INIT_FLAGS = 75,
249 	CP_SET_PROTECTED_MODE = 95,
250 	CP_BOOTSTRAP_UCODE = 111,
251 	CP_LOAD_STATE = 48,
252 	CP_LOAD_STATE4 = 48,
253 	CP_COND_INDIRECT_BUFFER_PFE = 58,
254 	CP_COND_INDIRECT_BUFFER_PFD = 50,
255 	CP_INDIRECT_BUFFER_PFE = 63,
256 	CP_SET_BIN = 76,
257 	CP_TEST_TWO_MEMS = 113,
258 	CP_REG_WR_NO_CTXT = 120,
259 	CP_RECORD_PFP_TIMESTAMP = 17,
260 	CP_SET_SECURE_MODE = 102,
261 	CP_WAIT_FOR_ME = 19,
262 	CP_SET_DRAW_STATE = 67,
263 	CP_DRAW_INDX_OFFSET = 56,
264 	CP_DRAW_INDIRECT = 40,
265 	CP_DRAW_INDX_INDIRECT = 41,
266 	CP_DRAW_INDIRECT_MULTI = 42,
267 	CP_DRAW_AUTO = 36,
268 	CP_DRAW_PRED_ENABLE_GLOBAL = 25,
269 	CP_DRAW_PRED_ENABLE_LOCAL = 26,
270 	CP_DRAW_PRED_SET = 78,
271 	CP_WIDE_REG_WRITE = 116,
272 	CP_SCRATCH_TO_REG = 77,
273 	CP_REG_TO_SCRATCH = 74,
274 	CP_WAIT_MEM_WRITES = 18,
275 	CP_COND_REG_EXEC = 71,
276 	CP_MEM_TO_REG = 66,
277 	CP_EXEC_CS_INDIRECT = 65,
278 	CP_EXEC_CS = 51,
279 	CP_PERFCOUNTER_ACTION = 80,
280 	CP_SMMU_TABLE_UPDATE = 83,
281 	CP_SET_MARKER = 101,
282 	CP_SET_PSEUDO_REG = 86,
283 	CP_CONTEXT_REG_BUNCH = 92,
284 	CP_YIELD_ENABLE = 28,
285 	CP_SKIP_IB2_ENABLE_GLOBAL = 29,
286 	CP_SKIP_IB2_ENABLE_LOCAL = 35,
287 	CP_SET_SUBDRAW_SIZE = 53,
288 	CP_WHERE_AM_I = 98,
289 	CP_SET_VISIBILITY_OVERRIDE = 100,
290 	CP_PREEMPT_ENABLE_GLOBAL = 105,
291 	CP_PREEMPT_ENABLE_LOCAL = 106,
292 	CP_CONTEXT_SWITCH_YIELD = 107,
293 	CP_SET_RENDER_MODE = 108,
294 	CP_COMPUTE_CHECKPOINT = 110,
295 	CP_MEM_TO_MEM = 115,
296 	CP_BLIT = 44,
297 	CP_REG_TEST = 57,
298 	CP_SET_MODE = 99,
299 	CP_LOAD_STATE6_GEOM = 50,
300 	CP_LOAD_STATE6_FRAG = 52,
301 	CP_LOAD_STATE6 = 54,
302 	IN_IB_PREFETCH_END = 23,
303 	IN_SUBBLK_PREFETCH = 31,
304 	IN_INSTR_PREFETCH = 32,
305 	IN_INSTR_MATCH = 71,
306 	IN_CONST_PREFETCH = 73,
307 	IN_INCR_UPDT_STATE = 85,
308 	IN_INCR_UPDT_CONST = 86,
309 	IN_INCR_UPDT_INSTR = 87,
310 	PKT4 = 4,
311 	IN_IB_END = 10,
312 	IN_GMU_INTERRUPT = 11,
313 	IN_PREEMPT = 15,
314 	CP_SCRATCH_WRITE = 76,
315 	CP_REG_TO_MEM_OFFSET_MEM = 116,
316 	CP_REG_TO_MEM_OFFSET_REG = 114,
317 	CP_WAIT_MEM_GTE = 20,
318 	CP_WAIT_TWO_REGS = 112,
319 	CP_MEMCPY = 117,
320 	CP_SET_BIN_DATA5_OFFSET = 46,
321 	CP_CONTEXT_SWITCH = 84,
322 	CP_SET_CTXSWITCH_IB = 85,
323 	CP_REG_WRITE = 109,
324 	CP_START_BIN = 80,
325 	CP_END_BIN = 81,
326 	CP_PREEMPT_DISABLE = 108,
327 	CP_WAIT_TIMESTAMP = 20,
328 	CP_THREAD_CONTROL = 23,
329 	CP_CONTEXT_REG_BUNCH2 = 93,
330 	CP_UNK15 = 21,
331 	CP_UNK16 = 22,
332 	CP_UNK18 = 24,
333 	CP_UNK1B = 27,
334 	CP_UNK49 = 73,
335 };
336 
337 enum adreno_state_block {
338 	SB_VERT_TEX = 0,
339 	SB_VERT_MIPADDR = 1,
340 	SB_FRAG_TEX = 2,
341 	SB_FRAG_MIPADDR = 3,
342 	SB_VERT_SHADER = 4,
343 	SB_GEOM_SHADER = 5,
344 	SB_FRAG_SHADER = 6,
345 	SB_COMPUTE_SHADER = 7,
346 };
347 
348 enum adreno_state_type {
349 	ST_SHADER = 0,
350 	ST_CONSTANTS = 1,
351 };
352 
353 enum adreno_state_src {
354 	SS_DIRECT = 0,
355 	SS_INVALID_ALL_IC = 2,
356 	SS_INVALID_PART_IC = 3,
357 	SS_INDIRECT = 4,
358 	SS_INDIRECT_TCM = 5,
359 	SS_INDIRECT_STM = 6,
360 };
361 
362 enum a4xx_state_block {
363 	SB4_VS_TEX = 0,
364 	SB4_HS_TEX = 1,
365 	SB4_DS_TEX = 2,
366 	SB4_GS_TEX = 3,
367 	SB4_FS_TEX = 4,
368 	SB4_CS_TEX = 5,
369 	SB4_VS_SHADER = 8,
370 	SB4_HS_SHADER = 9,
371 	SB4_DS_SHADER = 10,
372 	SB4_GS_SHADER = 11,
373 	SB4_FS_SHADER = 12,
374 	SB4_CS_SHADER = 13,
375 	SB4_SSBO = 14,
376 	SB4_CS_SSBO = 15,
377 };
378 
379 enum a4xx_state_type {
380 	ST4_SHADER = 0,
381 	ST4_CONSTANTS = 1,
382 	ST4_UBO = 2,
383 };
384 
385 enum a4xx_state_src {
386 	SS4_DIRECT = 0,
387 	SS4_INDIRECT = 2,
388 };
389 
390 enum a6xx_state_block {
391 	SB6_VS_TEX = 0,
392 	SB6_HS_TEX = 1,
393 	SB6_DS_TEX = 2,
394 	SB6_GS_TEX = 3,
395 	SB6_FS_TEX = 4,
396 	SB6_CS_TEX = 5,
397 	SB6_VS_SHADER = 8,
398 	SB6_HS_SHADER = 9,
399 	SB6_DS_SHADER = 10,
400 	SB6_GS_SHADER = 11,
401 	SB6_FS_SHADER = 12,
402 	SB6_CS_SHADER = 13,
403 	SB6_IBO = 14,
404 	SB6_CS_IBO = 15,
405 };
406 
407 enum a6xx_state_type {
408 	ST6_SHADER = 0,
409 	ST6_CONSTANTS = 1,
410 	ST6_UBO = 2,
411 	ST6_IBO = 3,
412 };
413 
414 enum a6xx_state_src {
415 	SS6_DIRECT = 0,
416 	SS6_BINDLESS = 1,
417 	SS6_INDIRECT = 2,
418 	SS6_UBO = 3,
419 };
420 
421 enum a4xx_index_size {
422 	INDEX4_SIZE_8_BIT = 0,
423 	INDEX4_SIZE_16_BIT = 1,
424 	INDEX4_SIZE_32_BIT = 2,
425 };
426 
427 enum a6xx_patch_type {
428 	TESS_QUADS = 0,
429 	TESS_TRIANGLES = 1,
430 	TESS_ISOLINES = 2,
431 };
432 
433 enum a6xx_draw_indirect_opcode {
434 	INDIRECT_OP_NORMAL = 2,
435 	INDIRECT_OP_INDEXED = 4,
436 	INDIRECT_OP_INDIRECT_COUNT = 6,
437 	INDIRECT_OP_INDIRECT_COUNT_INDEXED = 7,
438 };
439 
440 enum cp_draw_pred_src {
441 	PRED_SRC_MEM = 5,
442 };
443 
444 enum cp_draw_pred_test {
445 	NE_0_PASS = 0,
446 	EQ_0_PASS = 1,
447 };
448 
449 enum cp_cond_function {
450 	WRITE_ALWAYS = 0,
451 	WRITE_LT = 1,
452 	WRITE_LE = 2,
453 	WRITE_EQ = 3,
454 	WRITE_NE = 4,
455 	WRITE_GE = 5,
456 	WRITE_GT = 6,
457 };
458 
459 enum render_mode_cmd {
460 	BYPASS = 1,
461 	BINNING = 2,
462 	GMEM = 3,
463 	BLIT2D = 5,
464 	BLIT2DSCALE = 7,
465 	END2D = 8,
466 };
467 
468 enum cp_blit_cmd {
469 	BLIT_OP_FILL = 0,
470 	BLIT_OP_COPY = 1,
471 	BLIT_OP_SCALE = 3,
472 };
473 
474 enum a6xx_marker {
475 	RM6_BYPASS = 1,
476 	RM6_BINNING = 2,
477 	RM6_GMEM = 4,
478 	RM6_ENDVIS = 5,
479 	RM6_RESOLVE = 6,
480 	RM6_YIELD = 7,
481 	RM6_COMPUTE = 8,
482 	RM6_BLIT2DSCALE = 12,
483 	RM6_IB1LIST_START = 13,
484 	RM6_IB1LIST_END = 14,
485 	RM6_IFPC_ENABLE = 256,
486 	RM6_IFPC_DISABLE = 257,
487 };
488 
489 enum pseudo_reg {
490 	SMMU_INFO = 0,
491 	NON_SECURE_SAVE_ADDR = 1,
492 	SECURE_SAVE_ADDR = 2,
493 	NON_PRIV_SAVE_ADDR = 3,
494 	COUNTER = 4,
495 };
496 
497 enum compare_mode {
498 	PRED_TEST = 1,
499 	REG_COMPARE = 2,
500 	RENDER_MODE = 3,
501 };
502 
503 enum ctxswitch_ib {
504 	RESTORE_IB = 0,
505 	YIELD_RESTORE_IB = 1,
506 	SAVE_IB = 2,
507 	RB_SAVE_IB = 3,
508 };
509 
510 enum reg_tracker {
511 	TRACK_CNTL_REG = 1,
512 	TRACK_RENDER_CNTL = 2,
513 	UNK_EVENT_WRITE = 4,
514 	TRACK_LRZ = 8,
515 };
516 
517 enum cp_thread {
518 	CP_SET_THREAD_BR = 1,
519 	CP_SET_THREAD_BV = 2,
520 	CP_SET_THREAD_BOTH = 3,
521 };
522 
523 #define REG_CP_LOAD_STATE_0					0x00000000
524 #define CP_LOAD_STATE_0_DST_OFF__MASK				0x0000ffff
525 #define CP_LOAD_STATE_0_DST_OFF__SHIFT				0
526 static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val)
527 {
528 	return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK;
529 }
530 #define CP_LOAD_STATE_0_STATE_SRC__MASK				0x00070000
531 #define CP_LOAD_STATE_0_STATE_SRC__SHIFT			16
532 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val)
533 {
534 	return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK;
535 }
536 #define CP_LOAD_STATE_0_STATE_BLOCK__MASK			0x00380000
537 #define CP_LOAD_STATE_0_STATE_BLOCK__SHIFT			19
538 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val)
539 {
540 	return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK;
541 }
542 #define CP_LOAD_STATE_0_NUM_UNIT__MASK				0xffc00000
543 #define CP_LOAD_STATE_0_NUM_UNIT__SHIFT				22
544 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val)
545 {
546 	return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK;
547 }
548 
549 #define REG_CP_LOAD_STATE_1					0x00000001
550 #define CP_LOAD_STATE_1_STATE_TYPE__MASK			0x00000003
551 #define CP_LOAD_STATE_1_STATE_TYPE__SHIFT			0
552 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val)
553 {
554 	return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK;
555 }
556 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK			0xfffffffc
557 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT			2
558 static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val)
559 {
560 	return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK;
561 }
562 
563 #define REG_CP_LOAD_STATE4_0					0x00000000
564 #define CP_LOAD_STATE4_0_DST_OFF__MASK				0x00003fff
565 #define CP_LOAD_STATE4_0_DST_OFF__SHIFT				0
566 static inline uint32_t CP_LOAD_STATE4_0_DST_OFF(uint32_t val)
567 {
568 	return ((val) << CP_LOAD_STATE4_0_DST_OFF__SHIFT) & CP_LOAD_STATE4_0_DST_OFF__MASK;
569 }
570 #define CP_LOAD_STATE4_0_STATE_SRC__MASK			0x00030000
571 #define CP_LOAD_STATE4_0_STATE_SRC__SHIFT			16
572 static inline uint32_t CP_LOAD_STATE4_0_STATE_SRC(enum a4xx_state_src val)
573 {
574 	return ((val) << CP_LOAD_STATE4_0_STATE_SRC__SHIFT) & CP_LOAD_STATE4_0_STATE_SRC__MASK;
575 }
576 #define CP_LOAD_STATE4_0_STATE_BLOCK__MASK			0x003c0000
577 #define CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT			18
578 static inline uint32_t CP_LOAD_STATE4_0_STATE_BLOCK(enum a4xx_state_block val)
579 {
580 	return ((val) << CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE4_0_STATE_BLOCK__MASK;
581 }
582 #define CP_LOAD_STATE4_0_NUM_UNIT__MASK				0xffc00000
583 #define CP_LOAD_STATE4_0_NUM_UNIT__SHIFT			22
584 static inline uint32_t CP_LOAD_STATE4_0_NUM_UNIT(uint32_t val)
585 {
586 	return ((val) << CP_LOAD_STATE4_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE4_0_NUM_UNIT__MASK;
587 }
588 
589 #define REG_CP_LOAD_STATE4_1					0x00000001
590 #define CP_LOAD_STATE4_1_STATE_TYPE__MASK			0x00000003
591 #define CP_LOAD_STATE4_1_STATE_TYPE__SHIFT			0
592 static inline uint32_t CP_LOAD_STATE4_1_STATE_TYPE(enum a4xx_state_type val)
593 {
594 	return ((val) << CP_LOAD_STATE4_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE4_1_STATE_TYPE__MASK;
595 }
596 #define CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK			0xfffffffc
597 #define CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT			2
598 static inline uint32_t CP_LOAD_STATE4_1_EXT_SRC_ADDR(uint32_t val)
599 {
600 	return ((val >> 2) << CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK;
601 }
602 
603 #define REG_CP_LOAD_STATE4_2					0x00000002
604 #define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK			0xffffffff
605 #define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT			0
606 static inline uint32_t CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(uint32_t val)
607 {
608 	return ((val) << CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK;
609 }
610 
611 #define REG_CP_LOAD_STATE6_0					0x00000000
612 #define CP_LOAD_STATE6_0_DST_OFF__MASK				0x00003fff
613 #define CP_LOAD_STATE6_0_DST_OFF__SHIFT				0
614 static inline uint32_t CP_LOAD_STATE6_0_DST_OFF(uint32_t val)
615 {
616 	return ((val) << CP_LOAD_STATE6_0_DST_OFF__SHIFT) & CP_LOAD_STATE6_0_DST_OFF__MASK;
617 }
618 #define CP_LOAD_STATE6_0_STATE_TYPE__MASK			0x0000c000
619 #define CP_LOAD_STATE6_0_STATE_TYPE__SHIFT			14
620 static inline uint32_t CP_LOAD_STATE6_0_STATE_TYPE(enum a6xx_state_type val)
621 {
622 	return ((val) << CP_LOAD_STATE6_0_STATE_TYPE__SHIFT) & CP_LOAD_STATE6_0_STATE_TYPE__MASK;
623 }
624 #define CP_LOAD_STATE6_0_STATE_SRC__MASK			0x00030000
625 #define CP_LOAD_STATE6_0_STATE_SRC__SHIFT			16
626 static inline uint32_t CP_LOAD_STATE6_0_STATE_SRC(enum a6xx_state_src val)
627 {
628 	return ((val) << CP_LOAD_STATE6_0_STATE_SRC__SHIFT) & CP_LOAD_STATE6_0_STATE_SRC__MASK;
629 }
630 #define CP_LOAD_STATE6_0_STATE_BLOCK__MASK			0x003c0000
631 #define CP_LOAD_STATE6_0_STATE_BLOCK__SHIFT			18
632 static inline uint32_t CP_LOAD_STATE6_0_STATE_BLOCK(enum a6xx_state_block val)
633 {
634 	return ((val) << CP_LOAD_STATE6_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE6_0_STATE_BLOCK__MASK;
635 }
636 #define CP_LOAD_STATE6_0_NUM_UNIT__MASK				0xffc00000
637 #define CP_LOAD_STATE6_0_NUM_UNIT__SHIFT			22
638 static inline uint32_t CP_LOAD_STATE6_0_NUM_UNIT(uint32_t val)
639 {
640 	return ((val) << CP_LOAD_STATE6_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE6_0_NUM_UNIT__MASK;
641 }
642 
643 #define REG_CP_LOAD_STATE6_1					0x00000001
644 #define CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK			0xfffffffc
645 #define CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT			2
646 static inline uint32_t CP_LOAD_STATE6_1_EXT_SRC_ADDR(uint32_t val)
647 {
648 	return ((val >> 2) << CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK;
649 }
650 
651 #define REG_CP_LOAD_STATE6_2					0x00000002
652 #define CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK			0xffffffff
653 #define CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT			0
654 static inline uint32_t CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(uint32_t val)
655 {
656 	return ((val) << CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK;
657 }
658 
659 #define REG_CP_LOAD_STATE6_EXT_SRC_ADDR				0x00000001
660 
661 #define REG_CP_DRAW_INDX_0					0x00000000
662 #define CP_DRAW_INDX_0_VIZ_QUERY__MASK				0xffffffff
663 #define CP_DRAW_INDX_0_VIZ_QUERY__SHIFT				0
664 static inline uint32_t CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val)
665 {
666 	return ((val) << CP_DRAW_INDX_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_0_VIZ_QUERY__MASK;
667 }
668 
669 #define REG_CP_DRAW_INDX_1					0x00000001
670 #define CP_DRAW_INDX_1_PRIM_TYPE__MASK				0x0000003f
671 #define CP_DRAW_INDX_1_PRIM_TYPE__SHIFT				0
672 static inline uint32_t CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val)
673 {
674 	return ((val) << CP_DRAW_INDX_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_1_PRIM_TYPE__MASK;
675 }
676 #define CP_DRAW_INDX_1_SOURCE_SELECT__MASK			0x000000c0
677 #define CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT			6
678 static inline uint32_t CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val)
679 {
680 	return ((val) << CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_1_SOURCE_SELECT__MASK;
681 }
682 #define CP_DRAW_INDX_1_VIS_CULL__MASK				0x00000600
683 #define CP_DRAW_INDX_1_VIS_CULL__SHIFT				9
684 static inline uint32_t CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val)
685 {
686 	return ((val) << CP_DRAW_INDX_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_1_VIS_CULL__MASK;
687 }
688 #define CP_DRAW_INDX_1_INDEX_SIZE__MASK				0x00000800
689 #define CP_DRAW_INDX_1_INDEX_SIZE__SHIFT			11
690 static inline uint32_t CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val)
691 {
692 	return ((val) << CP_DRAW_INDX_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_1_INDEX_SIZE__MASK;
693 }
694 #define CP_DRAW_INDX_1_NOT_EOP					0x00001000
695 #define CP_DRAW_INDX_1_SMALL_INDEX				0x00002000
696 #define CP_DRAW_INDX_1_PRE_DRAW_INITIATOR_ENABLE		0x00004000
697 #define CP_DRAW_INDX_1_NUM_INSTANCES__MASK			0xff000000
698 #define CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT			24
699 static inline uint32_t CP_DRAW_INDX_1_NUM_INSTANCES(uint32_t val)
700 {
701 	return ((val) << CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_1_NUM_INSTANCES__MASK;
702 }
703 
704 #define REG_CP_DRAW_INDX_2					0x00000002
705 #define CP_DRAW_INDX_2_NUM_INDICES__MASK			0xffffffff
706 #define CP_DRAW_INDX_2_NUM_INDICES__SHIFT			0
707 static inline uint32_t CP_DRAW_INDX_2_NUM_INDICES(uint32_t val)
708 {
709 	return ((val) << CP_DRAW_INDX_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_NUM_INDICES__MASK;
710 }
711 
712 #define REG_CP_DRAW_INDX_3					0x00000003
713 #define CP_DRAW_INDX_3_INDX_BASE__MASK				0xffffffff
714 #define CP_DRAW_INDX_3_INDX_BASE__SHIFT				0
715 static inline uint32_t CP_DRAW_INDX_3_INDX_BASE(uint32_t val)
716 {
717 	return ((val) << CP_DRAW_INDX_3_INDX_BASE__SHIFT) & CP_DRAW_INDX_3_INDX_BASE__MASK;
718 }
719 
720 #define REG_CP_DRAW_INDX_4					0x00000004
721 #define CP_DRAW_INDX_4_INDX_SIZE__MASK				0xffffffff
722 #define CP_DRAW_INDX_4_INDX_SIZE__SHIFT				0
723 static inline uint32_t CP_DRAW_INDX_4_INDX_SIZE(uint32_t val)
724 {
725 	return ((val) << CP_DRAW_INDX_4_INDX_SIZE__SHIFT) & CP_DRAW_INDX_4_INDX_SIZE__MASK;
726 }
727 
728 #define REG_CP_DRAW_INDX_2_0					0x00000000
729 #define CP_DRAW_INDX_2_0_VIZ_QUERY__MASK			0xffffffff
730 #define CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT			0
731 static inline uint32_t CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val)
732 {
733 	return ((val) << CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_2_0_VIZ_QUERY__MASK;
734 }
735 
736 #define REG_CP_DRAW_INDX_2_1					0x00000001
737 #define CP_DRAW_INDX_2_1_PRIM_TYPE__MASK			0x0000003f
738 #define CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT			0
739 static inline uint32_t CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val)
740 {
741 	return ((val) << CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_2_1_PRIM_TYPE__MASK;
742 }
743 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK			0x000000c0
744 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT			6
745 static inline uint32_t CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val)
746 {
747 	return ((val) << CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK;
748 }
749 #define CP_DRAW_INDX_2_1_VIS_CULL__MASK				0x00000600
750 #define CP_DRAW_INDX_2_1_VIS_CULL__SHIFT			9
751 static inline uint32_t CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val)
752 {
753 	return ((val) << CP_DRAW_INDX_2_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_2_1_VIS_CULL__MASK;
754 }
755 #define CP_DRAW_INDX_2_1_INDEX_SIZE__MASK			0x00000800
756 #define CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT			11
757 static inline uint32_t CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val)
758 {
759 	return ((val) << CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_2_1_INDEX_SIZE__MASK;
760 }
761 #define CP_DRAW_INDX_2_1_NOT_EOP				0x00001000
762 #define CP_DRAW_INDX_2_1_SMALL_INDEX				0x00002000
763 #define CP_DRAW_INDX_2_1_PRE_DRAW_INITIATOR_ENABLE		0x00004000
764 #define CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK			0xff000000
765 #define CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT			24
766 static inline uint32_t CP_DRAW_INDX_2_1_NUM_INSTANCES(uint32_t val)
767 {
768 	return ((val) << CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK;
769 }
770 
771 #define REG_CP_DRAW_INDX_2_2					0x00000002
772 #define CP_DRAW_INDX_2_2_NUM_INDICES__MASK			0xffffffff
773 #define CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT			0
774 static inline uint32_t CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val)
775 {
776 	return ((val) << CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_2_NUM_INDICES__MASK;
777 }
778 
779 #define REG_CP_DRAW_INDX_OFFSET_0				0x00000000
780 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK			0x0000003f
781 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT			0
782 static inline uint32_t CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val)
783 {
784 	return ((val) << CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK;
785 }
786 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK		0x000000c0
787 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT		6
788 static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val)
789 {
790 	return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK;
791 }
792 #define CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK			0x00000300
793 #define CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT			8
794 static inline uint32_t CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val)
795 {
796 	return ((val) << CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT) & CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK;
797 }
798 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK			0x00000c00
799 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT			10
800 static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val)
801 {
802 	return ((val) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK;
803 }
804 #define CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__MASK			0x00003000
805 #define CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__SHIFT			12
806 static inline uint32_t CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(enum a6xx_patch_type val)
807 {
808 	return ((val) << CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__MASK;
809 }
810 #define CP_DRAW_INDX_OFFSET_0_GS_ENABLE				0x00010000
811 #define CP_DRAW_INDX_OFFSET_0_TESS_ENABLE			0x00020000
812 
813 #define REG_CP_DRAW_INDX_OFFSET_1				0x00000001
814 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK		0xffffffff
815 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT		0
816 static inline uint32_t CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES(uint32_t val)
817 {
818 	return ((val) << CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK;
819 }
820 
821 #define REG_CP_DRAW_INDX_OFFSET_2				0x00000002
822 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK			0xffffffff
823 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT		0
824 static inline uint32_t CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val)
825 {
826 	return ((val) << CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK;
827 }
828 
829 #define REG_CP_DRAW_INDX_OFFSET_3				0x00000003
830 #define CP_DRAW_INDX_OFFSET_3_FIRST_INDX__MASK			0xffffffff
831 #define CP_DRAW_INDX_OFFSET_3_FIRST_INDX__SHIFT			0
832 static inline uint32_t CP_DRAW_INDX_OFFSET_3_FIRST_INDX(uint32_t val)
833 {
834 	return ((val) << CP_DRAW_INDX_OFFSET_3_FIRST_INDX__SHIFT) & CP_DRAW_INDX_OFFSET_3_FIRST_INDX__MASK;
835 }
836 
837 
838 #define REG_CP_DRAW_INDX_OFFSET_4				0x00000004
839 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__MASK		0xffffffff
840 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__SHIFT		0
841 static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO(uint32_t val)
842 {
843 	return ((val) << CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__MASK;
844 }
845 
846 #define REG_CP_DRAW_INDX_OFFSET_5				0x00000005
847 #define CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__MASK		0xffffffff
848 #define CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__SHIFT		0
849 static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI(uint32_t val)
850 {
851 	return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__MASK;
852 }
853 
854 #define REG_CP_DRAW_INDX_OFFSET_INDX_BASE			0x00000004
855 
856 #define REG_CP_DRAW_INDX_OFFSET_6				0x00000006
857 #define CP_DRAW_INDX_OFFSET_6_MAX_INDICES__MASK			0xffffffff
858 #define CP_DRAW_INDX_OFFSET_6_MAX_INDICES__SHIFT		0
859 static inline uint32_t CP_DRAW_INDX_OFFSET_6_MAX_INDICES(uint32_t val)
860 {
861 	return ((val) << CP_DRAW_INDX_OFFSET_6_MAX_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_6_MAX_INDICES__MASK;
862 }
863 
864 #define REG_CP_DRAW_INDX_OFFSET_4				0x00000004
865 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK			0xffffffff
866 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT			0
867 static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE(uint32_t val)
868 {
869 	return ((val) << CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK;
870 }
871 
872 #define REG_CP_DRAW_INDX_OFFSET_5				0x00000005
873 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK			0xffffffff
874 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT			0
875 static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_SIZE(uint32_t val)
876 {
877 	return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK;
878 }
879 
880 #define REG_A4XX_CP_DRAW_INDIRECT_0				0x00000000
881 #define A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK			0x0000003f
882 #define A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT		0
883 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val)
884 {
885 	return ((val) << A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK;
886 }
887 #define A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK		0x000000c0
888 #define A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT		6
889 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val)
890 {
891 	return ((val) << A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK;
892 }
893 #define A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK			0x00000300
894 #define A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT			8
895 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val)
896 {
897 	return ((val) << A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK;
898 }
899 #define A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK		0x00000c00
900 #define A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT		10
901 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val)
902 {
903 	return ((val) << A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK;
904 }
905 #define A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__MASK		0x00003000
906 #define A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__SHIFT		12
907 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE(enum a6xx_patch_type val)
908 {
909 	return ((val) << A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__MASK;
910 }
911 #define A4XX_CP_DRAW_INDIRECT_0_GS_ENABLE			0x00010000
912 #define A4XX_CP_DRAW_INDIRECT_0_TESS_ENABLE			0x00020000
913 
914 
915 #define REG_A4XX_CP_DRAW_INDIRECT_1				0x00000001
916 #define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK			0xffffffff
917 #define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT			0
918 static inline uint32_t A4XX_CP_DRAW_INDIRECT_1_INDIRECT(uint32_t val)
919 {
920 	return ((val) << A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK;
921 }
922 
923 
924 #define REG_A5XX_CP_DRAW_INDIRECT_1				0x00000001
925 #define A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__MASK		0xffffffff
926 #define A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__SHIFT		0
927 static inline uint32_t A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO(uint32_t val)
928 {
929 	return ((val) << A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__SHIFT) & A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__MASK;
930 }
931 
932 #define REG_A5XX_CP_DRAW_INDIRECT_2				0x00000002
933 #define A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK		0xffffffff
934 #define A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT		0
935 static inline uint32_t A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI(uint32_t val)
936 {
937 	return ((val) << A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK;
938 }
939 
940 #define REG_A5XX_CP_DRAW_INDIRECT_INDIRECT			0x00000001
941 
942 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_0			0x00000000
943 #define A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK		0x0000003f
944 #define A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT		0
945 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val)
946 {
947 	return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK;
948 }
949 #define A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK	0x000000c0
950 #define A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT	6
951 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val)
952 {
953 	return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK;
954 }
955 #define A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK		0x00000300
956 #define A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT		8
957 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val)
958 {
959 	return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK;
960 }
961 #define A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK		0x00000c00
962 #define A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT		10
963 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val)
964 {
965 	return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK;
966 }
967 #define A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__MASK		0x00003000
968 #define A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__SHIFT		12
969 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE(enum a6xx_patch_type val)
970 {
971 	return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__MASK;
972 }
973 #define A4XX_CP_DRAW_INDX_INDIRECT_0_GS_ENABLE			0x00010000
974 #define A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_ENABLE		0x00020000
975 
976 
977 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_1			0x00000001
978 #define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK		0xffffffff
979 #define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT		0
980 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE(uint32_t val)
981 {
982 	return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK;
983 }
984 
985 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_2			0x00000002
986 #define A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK		0xffffffff
987 #define A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT		0
988 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE(uint32_t val)
989 {
990 	return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK;
991 }
992 
993 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_3			0x00000003
994 #define A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK		0xffffffff
995 #define A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT		0
996 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT(uint32_t val)
997 {
998 	return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK;
999 }
1000 
1001 
1002 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_1			0x00000001
1003 #define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK		0xffffffff
1004 #define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT	0
1005 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO(uint32_t val)
1006 {
1007 	return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK;
1008 }
1009 
1010 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_2			0x00000002
1011 #define A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK		0xffffffff
1012 #define A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT	0
1013 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI(uint32_t val)
1014 {
1015 	return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK;
1016 }
1017 
1018 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_INDX_BASE		0x00000001
1019 
1020 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_3			0x00000003
1021 #define A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK		0xffffffff
1022 #define A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT		0
1023 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(uint32_t val)
1024 {
1025 	return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK;
1026 }
1027 
1028 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_4			0x00000004
1029 #define A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK		0xffffffff
1030 #define A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT		0
1031 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO(uint32_t val)
1032 {
1033 	return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK;
1034 }
1035 
1036 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_5			0x00000005
1037 #define A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK		0xffffffff
1038 #define A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT		0
1039 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI(uint32_t val)
1040 {
1041 	return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK;
1042 }
1043 
1044 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_INDIRECT			0x00000004
1045 
1046 #define REG_A6XX_CP_DRAW_INDIRECT_MULTI_0			0x00000000
1047 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__MASK		0x0000003f
1048 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__SHIFT		0
1049 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE(enum pc_di_primtype val)
1050 {
1051 	return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__MASK;
1052 }
1053 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__MASK	0x000000c0
1054 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__SHIFT	6
1055 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT(enum pc_di_src_sel val)
1056 {
1057 	return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__MASK;
1058 }
1059 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__MASK		0x00000300
1060 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__SHIFT		8
1061 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL(enum pc_di_vis_cull_mode val)
1062 {
1063 	return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__MASK;
1064 }
1065 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__MASK		0x00000c00
1066 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__SHIFT		10
1067 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE(enum a4xx_index_size val)
1068 {
1069 	return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__MASK;
1070 }
1071 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__MASK		0x00003000
1072 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__SHIFT		12
1073 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE(enum a6xx_patch_type val)
1074 {
1075 	return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__MASK;
1076 }
1077 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_GS_ENABLE			0x00010000
1078 #define A6XX_CP_DRAW_INDIRECT_MULTI_0_TESS_ENABLE		0x00020000
1079 
1080 #define REG_A6XX_CP_DRAW_INDIRECT_MULTI_1			0x00000001
1081 #define A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__MASK		0x0000000f
1082 #define A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__SHIFT		0
1083 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(enum a6xx_draw_indirect_opcode val)
1084 {
1085 	return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__MASK;
1086 }
1087 #define A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__MASK		0x003fff00
1088 #define A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__SHIFT		8
1089 static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(uint32_t val)
1090 {
1091 	return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__MASK;
1092 }
1093 
1094 #define REG_A6XX_CP_DRAW_INDIRECT_MULTI_DRAW_COUNT		0x00000002
1095 
1096 
1097 #define REG_A6XX_CP_DRAW_INDIRECT_MULTI_INDIRECT		0x00000003
1098 
1099 #define REG_A6XX_CP_DRAW_INDIRECT_MULTI_STRIDE			0x00000005
1100 
1101 
1102 #define REG_CP_DRAW_INDIRECT_MULTI_INDEX_INDEXED		0x00000003
1103 
1104 #define REG_CP_DRAW_INDIRECT_MULTI_MAX_INDICES_INDEXED		0x00000005
1105 
1106 #define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_INDEXED		0x00000006
1107 
1108 #define REG_CP_DRAW_INDIRECT_MULTI_STRIDE_INDEXED		0x00000008
1109 
1110 
1111 #define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_INDIRECT		0x00000003
1112 
1113 #define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT_INDIRECT	0x00000005
1114 
1115 #define REG_CP_DRAW_INDIRECT_MULTI_STRIDE_INDIRECT		0x00000007
1116 
1117 
1118 #define REG_CP_DRAW_INDIRECT_MULTI_INDEX_INDIRECT_INDEXED	0x00000003
1119 
1120 #define REG_CP_DRAW_INDIRECT_MULTI_MAX_INDICES_INDIRECT_INDEXED	0x00000005
1121 
1122 #define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_INDIRECT_INDEXED	0x00000006
1123 
1124 #define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT_INDIRECT_INDEXED	0x00000008
1125 
1126 #define REG_CP_DRAW_INDIRECT_MULTI_STRIDE_INDIRECT_INDEXED	0x0000000a
1127 
1128 #define REG_CP_DRAW_PRED_ENABLE_GLOBAL_0			0x00000000
1129 #define CP_DRAW_PRED_ENABLE_GLOBAL_0_ENABLE			0x00000001
1130 
1131 #define REG_CP_DRAW_PRED_ENABLE_LOCAL_0				0x00000000
1132 #define CP_DRAW_PRED_ENABLE_LOCAL_0_ENABLE			0x00000001
1133 
1134 #define REG_CP_DRAW_PRED_SET_0					0x00000000
1135 #define CP_DRAW_PRED_SET_0_SRC__MASK				0x000000f0
1136 #define CP_DRAW_PRED_SET_0_SRC__SHIFT				4
1137 static inline uint32_t CP_DRAW_PRED_SET_0_SRC(enum cp_draw_pred_src val)
1138 {
1139 	return ((val) << CP_DRAW_PRED_SET_0_SRC__SHIFT) & CP_DRAW_PRED_SET_0_SRC__MASK;
1140 }
1141 #define CP_DRAW_PRED_SET_0_TEST__MASK				0x00000100
1142 #define CP_DRAW_PRED_SET_0_TEST__SHIFT				8
1143 static inline uint32_t CP_DRAW_PRED_SET_0_TEST(enum cp_draw_pred_test val)
1144 {
1145 	return ((val) << CP_DRAW_PRED_SET_0_TEST__SHIFT) & CP_DRAW_PRED_SET_0_TEST__MASK;
1146 }
1147 
1148 #define REG_CP_DRAW_PRED_SET_MEM_ADDR				0x00000001
1149 
1150 static inline uint32_t REG_CP_SET_DRAW_STATE_(uint32_t i0) { return 0x00000000 + 0x3*i0; }
1151 
1152 static inline uint32_t REG_CP_SET_DRAW_STATE__0(uint32_t i0) { return 0x00000000 + 0x3*i0; }
1153 #define CP_SET_DRAW_STATE__0_COUNT__MASK			0x0000ffff
1154 #define CP_SET_DRAW_STATE__0_COUNT__SHIFT			0
1155 static inline uint32_t CP_SET_DRAW_STATE__0_COUNT(uint32_t val)
1156 {
1157 	return ((val) << CP_SET_DRAW_STATE__0_COUNT__SHIFT) & CP_SET_DRAW_STATE__0_COUNT__MASK;
1158 }
1159 #define CP_SET_DRAW_STATE__0_DIRTY				0x00010000
1160 #define CP_SET_DRAW_STATE__0_DISABLE				0x00020000
1161 #define CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS			0x00040000
1162 #define CP_SET_DRAW_STATE__0_LOAD_IMMED				0x00080000
1163 #define CP_SET_DRAW_STATE__0_BINNING				0x00100000
1164 #define CP_SET_DRAW_STATE__0_GMEM				0x00200000
1165 #define CP_SET_DRAW_STATE__0_SYSMEM				0x00400000
1166 #define CP_SET_DRAW_STATE__0_GROUP_ID__MASK			0x1f000000
1167 #define CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT			24
1168 static inline uint32_t CP_SET_DRAW_STATE__0_GROUP_ID(uint32_t val)
1169 {
1170 	return ((val) << CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT) & CP_SET_DRAW_STATE__0_GROUP_ID__MASK;
1171 }
1172 
1173 static inline uint32_t REG_CP_SET_DRAW_STATE__1(uint32_t i0) { return 0x00000001 + 0x3*i0; }
1174 #define CP_SET_DRAW_STATE__1_ADDR_LO__MASK			0xffffffff
1175 #define CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT			0
1176 static inline uint32_t CP_SET_DRAW_STATE__1_ADDR_LO(uint32_t val)
1177 {
1178 	return ((val) << CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT) & CP_SET_DRAW_STATE__1_ADDR_LO__MASK;
1179 }
1180 
1181 static inline uint32_t REG_CP_SET_DRAW_STATE__2(uint32_t i0) { return 0x00000002 + 0x3*i0; }
1182 #define CP_SET_DRAW_STATE__2_ADDR_HI__MASK			0xffffffff
1183 #define CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT			0
1184 static inline uint32_t CP_SET_DRAW_STATE__2_ADDR_HI(uint32_t val)
1185 {
1186 	return ((val) << CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT) & CP_SET_DRAW_STATE__2_ADDR_HI__MASK;
1187 }
1188 
1189 #define REG_CP_SET_BIN_0					0x00000000
1190 
1191 #define REG_CP_SET_BIN_1					0x00000001
1192 #define CP_SET_BIN_1_X1__MASK					0x0000ffff
1193 #define CP_SET_BIN_1_X1__SHIFT					0
1194 static inline uint32_t CP_SET_BIN_1_X1(uint32_t val)
1195 {
1196 	return ((val) << CP_SET_BIN_1_X1__SHIFT) & CP_SET_BIN_1_X1__MASK;
1197 }
1198 #define CP_SET_BIN_1_Y1__MASK					0xffff0000
1199 #define CP_SET_BIN_1_Y1__SHIFT					16
1200 static inline uint32_t CP_SET_BIN_1_Y1(uint32_t val)
1201 {
1202 	return ((val) << CP_SET_BIN_1_Y1__SHIFT) & CP_SET_BIN_1_Y1__MASK;
1203 }
1204 
1205 #define REG_CP_SET_BIN_2					0x00000002
1206 #define CP_SET_BIN_2_X2__MASK					0x0000ffff
1207 #define CP_SET_BIN_2_X2__SHIFT					0
1208 static inline uint32_t CP_SET_BIN_2_X2(uint32_t val)
1209 {
1210 	return ((val) << CP_SET_BIN_2_X2__SHIFT) & CP_SET_BIN_2_X2__MASK;
1211 }
1212 #define CP_SET_BIN_2_Y2__MASK					0xffff0000
1213 #define CP_SET_BIN_2_Y2__SHIFT					16
1214 static inline uint32_t CP_SET_BIN_2_Y2(uint32_t val)
1215 {
1216 	return ((val) << CP_SET_BIN_2_Y2__SHIFT) & CP_SET_BIN_2_Y2__MASK;
1217 }
1218 
1219 #define REG_CP_SET_BIN_DATA_0					0x00000000
1220 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK			0xffffffff
1221 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT			0
1222 static inline uint32_t CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val)
1223 {
1224 	return ((val) << CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT) & CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK;
1225 }
1226 
1227 #define REG_CP_SET_BIN_DATA_1					0x00000001
1228 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK		0xffffffff
1229 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT		0
1230 static inline uint32_t CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val)
1231 {
1232 	return ((val) << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK;
1233 }
1234 
1235 #define REG_CP_SET_BIN_DATA5_0					0x00000000
1236 #define CP_SET_BIN_DATA5_0_VSC_SIZE__MASK			0x003f0000
1237 #define CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT			16
1238 static inline uint32_t CP_SET_BIN_DATA5_0_VSC_SIZE(uint32_t val)
1239 {
1240 	return ((val) << CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT) & CP_SET_BIN_DATA5_0_VSC_SIZE__MASK;
1241 }
1242 #define CP_SET_BIN_DATA5_0_VSC_N__MASK				0x07c00000
1243 #define CP_SET_BIN_DATA5_0_VSC_N__SHIFT				22
1244 static inline uint32_t CP_SET_BIN_DATA5_0_VSC_N(uint32_t val)
1245 {
1246 	return ((val) << CP_SET_BIN_DATA5_0_VSC_N__SHIFT) & CP_SET_BIN_DATA5_0_VSC_N__MASK;
1247 }
1248 
1249 #define REG_CP_SET_BIN_DATA5_1					0x00000001
1250 #define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK		0xffffffff
1251 #define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT		0
1252 static inline uint32_t CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO(uint32_t val)
1253 {
1254 	return ((val) << CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT) & CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK;
1255 }
1256 
1257 #define REG_CP_SET_BIN_DATA5_2					0x00000002
1258 #define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK		0xffffffff
1259 #define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT		0
1260 static inline uint32_t CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI(uint32_t val)
1261 {
1262 	return ((val) << CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT) & CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK;
1263 }
1264 
1265 #define REG_CP_SET_BIN_DATA5_3					0x00000003
1266 #define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK		0xffffffff
1267 #define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT		0
1268 static inline uint32_t CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO(uint32_t val)
1269 {
1270 	return ((val) << CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT) & CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK;
1271 }
1272 
1273 #define REG_CP_SET_BIN_DATA5_4					0x00000004
1274 #define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK		0xffffffff
1275 #define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT		0
1276 static inline uint32_t CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI(uint32_t val)
1277 {
1278 	return ((val) << CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT) & CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK;
1279 }
1280 
1281 #define REG_CP_SET_BIN_DATA5_5					0x00000005
1282 #define CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__MASK		0xffffffff
1283 #define CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__SHIFT		0
1284 static inline uint32_t CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO(uint32_t val)
1285 {
1286 	return ((val) << CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__SHIFT) & CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__MASK;
1287 }
1288 
1289 #define REG_CP_SET_BIN_DATA5_6					0x00000006
1290 #define CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__MASK		0xffffffff
1291 #define CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__SHIFT		0
1292 static inline uint32_t CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI(uint32_t val)
1293 {
1294 	return ((val) << CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__SHIFT) & CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__MASK;
1295 }
1296 
1297 #define REG_CP_SET_BIN_DATA5_7					0x00000007
1298 
1299 #define REG_CP_SET_BIN_DATA5_9					0x00000009
1300 
1301 #define REG_CP_SET_BIN_DATA5_OFFSET_0				0x00000000
1302 #define CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__MASK		0x003f0000
1303 #define CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__SHIFT		16
1304 static inline uint32_t CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE(uint32_t val)
1305 {
1306 	return ((val) << CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__SHIFT) & CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__MASK;
1307 }
1308 #define CP_SET_BIN_DATA5_OFFSET_0_VSC_N__MASK			0x07c00000
1309 #define CP_SET_BIN_DATA5_OFFSET_0_VSC_N__SHIFT			22
1310 static inline uint32_t CP_SET_BIN_DATA5_OFFSET_0_VSC_N(uint32_t val)
1311 {
1312 	return ((val) << CP_SET_BIN_DATA5_OFFSET_0_VSC_N__SHIFT) & CP_SET_BIN_DATA5_OFFSET_0_VSC_N__MASK;
1313 }
1314 
1315 #define REG_CP_SET_BIN_DATA5_OFFSET_1				0x00000001
1316 #define CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__MASK		0xffffffff
1317 #define CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__SHIFT	0
1318 static inline uint32_t CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET(uint32_t val)
1319 {
1320 	return ((val) << CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__SHIFT) & CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__MASK;
1321 }
1322 
1323 #define REG_CP_SET_BIN_DATA5_OFFSET_2				0x00000002
1324 #define CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__MASK		0xffffffff
1325 #define CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__SHIFT	0
1326 static inline uint32_t CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET(uint32_t val)
1327 {
1328 	return ((val) << CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__SHIFT) & CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__MASK;
1329 }
1330 
1331 #define REG_CP_SET_BIN_DATA5_OFFSET_3				0x00000003
1332 #define CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__MASK	0xffffffff
1333 #define CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__SHIFT	0
1334 static inline uint32_t CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET(uint32_t val)
1335 {
1336 	return ((val) << CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__SHIFT) & CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__MASK;
1337 }
1338 
1339 #define REG_CP_REG_RMW_0					0x00000000
1340 #define CP_REG_RMW_0_DST_REG__MASK				0x0003ffff
1341 #define CP_REG_RMW_0_DST_REG__SHIFT				0
1342 static inline uint32_t CP_REG_RMW_0_DST_REG(uint32_t val)
1343 {
1344 	return ((val) << CP_REG_RMW_0_DST_REG__SHIFT) & CP_REG_RMW_0_DST_REG__MASK;
1345 }
1346 #define CP_REG_RMW_0_ROTATE__MASK				0x1f000000
1347 #define CP_REG_RMW_0_ROTATE__SHIFT				24
1348 static inline uint32_t CP_REG_RMW_0_ROTATE(uint32_t val)
1349 {
1350 	return ((val) << CP_REG_RMW_0_ROTATE__SHIFT) & CP_REG_RMW_0_ROTATE__MASK;
1351 }
1352 #define CP_REG_RMW_0_SRC1_ADD					0x20000000
1353 #define CP_REG_RMW_0_SRC1_IS_REG				0x40000000
1354 #define CP_REG_RMW_0_SRC0_IS_REG				0x80000000
1355 
1356 #define REG_CP_REG_RMW_1					0x00000001
1357 #define CP_REG_RMW_1_SRC0__MASK					0xffffffff
1358 #define CP_REG_RMW_1_SRC0__SHIFT				0
1359 static inline uint32_t CP_REG_RMW_1_SRC0(uint32_t val)
1360 {
1361 	return ((val) << CP_REG_RMW_1_SRC0__SHIFT) & CP_REG_RMW_1_SRC0__MASK;
1362 }
1363 
1364 #define REG_CP_REG_RMW_2					0x00000002
1365 #define CP_REG_RMW_2_SRC1__MASK					0xffffffff
1366 #define CP_REG_RMW_2_SRC1__SHIFT				0
1367 static inline uint32_t CP_REG_RMW_2_SRC1(uint32_t val)
1368 {
1369 	return ((val) << CP_REG_RMW_2_SRC1__SHIFT) & CP_REG_RMW_2_SRC1__MASK;
1370 }
1371 
1372 #define REG_CP_REG_TO_MEM_0					0x00000000
1373 #define CP_REG_TO_MEM_0_REG__MASK				0x0003ffff
1374 #define CP_REG_TO_MEM_0_REG__SHIFT				0
1375 static inline uint32_t CP_REG_TO_MEM_0_REG(uint32_t val)
1376 {
1377 	return ((val) << CP_REG_TO_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_0_REG__MASK;
1378 }
1379 #define CP_REG_TO_MEM_0_CNT__MASK				0x3ffc0000
1380 #define CP_REG_TO_MEM_0_CNT__SHIFT				18
1381 static inline uint32_t CP_REG_TO_MEM_0_CNT(uint32_t val)
1382 {
1383 	return ((val) << CP_REG_TO_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_0_CNT__MASK;
1384 }
1385 #define CP_REG_TO_MEM_0_64B					0x40000000
1386 #define CP_REG_TO_MEM_0_ACCUMULATE				0x80000000
1387 
1388 #define REG_CP_REG_TO_MEM_1					0x00000001
1389 #define CP_REG_TO_MEM_1_DEST__MASK				0xffffffff
1390 #define CP_REG_TO_MEM_1_DEST__SHIFT				0
1391 static inline uint32_t CP_REG_TO_MEM_1_DEST(uint32_t val)
1392 {
1393 	return ((val) << CP_REG_TO_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_1_DEST__MASK;
1394 }
1395 
1396 #define REG_CP_REG_TO_MEM_2					0x00000002
1397 #define CP_REG_TO_MEM_2_DEST_HI__MASK				0xffffffff
1398 #define CP_REG_TO_MEM_2_DEST_HI__SHIFT				0
1399 static inline uint32_t CP_REG_TO_MEM_2_DEST_HI(uint32_t val)
1400 {
1401 	return ((val) << CP_REG_TO_MEM_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_2_DEST_HI__MASK;
1402 }
1403 
1404 #define REG_CP_REG_TO_MEM_OFFSET_REG_0				0x00000000
1405 #define CP_REG_TO_MEM_OFFSET_REG_0_REG__MASK			0x0003ffff
1406 #define CP_REG_TO_MEM_OFFSET_REG_0_REG__SHIFT			0
1407 static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_0_REG(uint32_t val)
1408 {
1409 	return ((val) << CP_REG_TO_MEM_OFFSET_REG_0_REG__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_0_REG__MASK;
1410 }
1411 #define CP_REG_TO_MEM_OFFSET_REG_0_CNT__MASK			0x3ffc0000
1412 #define CP_REG_TO_MEM_OFFSET_REG_0_CNT__SHIFT			18
1413 static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_0_CNT(uint32_t val)
1414 {
1415 	return ((val) << CP_REG_TO_MEM_OFFSET_REG_0_CNT__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_0_CNT__MASK;
1416 }
1417 #define CP_REG_TO_MEM_OFFSET_REG_0_64B				0x40000000
1418 #define CP_REG_TO_MEM_OFFSET_REG_0_ACCUMULATE			0x80000000
1419 
1420 #define REG_CP_REG_TO_MEM_OFFSET_REG_1				0x00000001
1421 #define CP_REG_TO_MEM_OFFSET_REG_1_DEST__MASK			0xffffffff
1422 #define CP_REG_TO_MEM_OFFSET_REG_1_DEST__SHIFT			0
1423 static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_1_DEST(uint32_t val)
1424 {
1425 	return ((val) << CP_REG_TO_MEM_OFFSET_REG_1_DEST__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_1_DEST__MASK;
1426 }
1427 
1428 #define REG_CP_REG_TO_MEM_OFFSET_REG_2				0x00000002
1429 #define CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__MASK		0xffffffff
1430 #define CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__SHIFT		0
1431 static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI(uint32_t val)
1432 {
1433 	return ((val) << CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__MASK;
1434 }
1435 
1436 #define REG_CP_REG_TO_MEM_OFFSET_REG_3				0x00000003
1437 #define CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__MASK		0x0003ffff
1438 #define CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__SHIFT		0
1439 static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0(uint32_t val)
1440 {
1441 	return ((val) << CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__MASK;
1442 }
1443 #define CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0_SCRATCH		0x00080000
1444 
1445 #define REG_CP_REG_TO_MEM_OFFSET_MEM_0				0x00000000
1446 #define CP_REG_TO_MEM_OFFSET_MEM_0_REG__MASK			0x0003ffff
1447 #define CP_REG_TO_MEM_OFFSET_MEM_0_REG__SHIFT			0
1448 static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_0_REG(uint32_t val)
1449 {
1450 	return ((val) << CP_REG_TO_MEM_OFFSET_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_0_REG__MASK;
1451 }
1452 #define CP_REG_TO_MEM_OFFSET_MEM_0_CNT__MASK			0x3ffc0000
1453 #define CP_REG_TO_MEM_OFFSET_MEM_0_CNT__SHIFT			18
1454 static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_0_CNT(uint32_t val)
1455 {
1456 	return ((val) << CP_REG_TO_MEM_OFFSET_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_0_CNT__MASK;
1457 }
1458 #define CP_REG_TO_MEM_OFFSET_MEM_0_64B				0x40000000
1459 #define CP_REG_TO_MEM_OFFSET_MEM_0_ACCUMULATE			0x80000000
1460 
1461 #define REG_CP_REG_TO_MEM_OFFSET_MEM_1				0x00000001
1462 #define CP_REG_TO_MEM_OFFSET_MEM_1_DEST__MASK			0xffffffff
1463 #define CP_REG_TO_MEM_OFFSET_MEM_1_DEST__SHIFT			0
1464 static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_1_DEST(uint32_t val)
1465 {
1466 	return ((val) << CP_REG_TO_MEM_OFFSET_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_1_DEST__MASK;
1467 }
1468 
1469 #define REG_CP_REG_TO_MEM_OFFSET_MEM_2				0x00000002
1470 #define CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__MASK		0xffffffff
1471 #define CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__SHIFT		0
1472 static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI(uint32_t val)
1473 {
1474 	return ((val) << CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__MASK;
1475 }
1476 
1477 #define REG_CP_REG_TO_MEM_OFFSET_MEM_3				0x00000003
1478 #define CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__MASK		0xffffffff
1479 #define CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__SHIFT		0
1480 static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO(uint32_t val)
1481 {
1482 	return ((val) << CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__MASK;
1483 }
1484 
1485 #define REG_CP_REG_TO_MEM_OFFSET_MEM_4				0x00000004
1486 #define CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__MASK		0xffffffff
1487 #define CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__SHIFT		0
1488 static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI(uint32_t val)
1489 {
1490 	return ((val) << CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__MASK;
1491 }
1492 
1493 #define REG_CP_MEM_TO_REG_0					0x00000000
1494 #define CP_MEM_TO_REG_0_REG__MASK				0x0003ffff
1495 #define CP_MEM_TO_REG_0_REG__SHIFT				0
1496 static inline uint32_t CP_MEM_TO_REG_0_REG(uint32_t val)
1497 {
1498 	return ((val) << CP_MEM_TO_REG_0_REG__SHIFT) & CP_MEM_TO_REG_0_REG__MASK;
1499 }
1500 #define CP_MEM_TO_REG_0_CNT__MASK				0x3ff80000
1501 #define CP_MEM_TO_REG_0_CNT__SHIFT				19
1502 static inline uint32_t CP_MEM_TO_REG_0_CNT(uint32_t val)
1503 {
1504 	return ((val) << CP_MEM_TO_REG_0_CNT__SHIFT) & CP_MEM_TO_REG_0_CNT__MASK;
1505 }
1506 #define CP_MEM_TO_REG_0_SHIFT_BY_2				0x40000000
1507 #define CP_MEM_TO_REG_0_UNK31					0x80000000
1508 
1509 #define REG_CP_MEM_TO_REG_1					0x00000001
1510 #define CP_MEM_TO_REG_1_SRC__MASK				0xffffffff
1511 #define CP_MEM_TO_REG_1_SRC__SHIFT				0
1512 static inline uint32_t CP_MEM_TO_REG_1_SRC(uint32_t val)
1513 {
1514 	return ((val) << CP_MEM_TO_REG_1_SRC__SHIFT) & CP_MEM_TO_REG_1_SRC__MASK;
1515 }
1516 
1517 #define REG_CP_MEM_TO_REG_2					0x00000002
1518 #define CP_MEM_TO_REG_2_SRC_HI__MASK				0xffffffff
1519 #define CP_MEM_TO_REG_2_SRC_HI__SHIFT				0
1520 static inline uint32_t CP_MEM_TO_REG_2_SRC_HI(uint32_t val)
1521 {
1522 	return ((val) << CP_MEM_TO_REG_2_SRC_HI__SHIFT) & CP_MEM_TO_REG_2_SRC_HI__MASK;
1523 }
1524 
1525 #define REG_CP_MEM_TO_MEM_0					0x00000000
1526 #define CP_MEM_TO_MEM_0_NEG_A					0x00000001
1527 #define CP_MEM_TO_MEM_0_NEG_B					0x00000002
1528 #define CP_MEM_TO_MEM_0_NEG_C					0x00000004
1529 #define CP_MEM_TO_MEM_0_DOUBLE					0x20000000
1530 #define CP_MEM_TO_MEM_0_WAIT_FOR_MEM_WRITES			0x40000000
1531 #define CP_MEM_TO_MEM_0_UNK31					0x80000000
1532 
1533 #define REG_CP_MEMCPY_0						0x00000000
1534 #define CP_MEMCPY_0_DWORDS__MASK				0xffffffff
1535 #define CP_MEMCPY_0_DWORDS__SHIFT				0
1536 static inline uint32_t CP_MEMCPY_0_DWORDS(uint32_t val)
1537 {
1538 	return ((val) << CP_MEMCPY_0_DWORDS__SHIFT) & CP_MEMCPY_0_DWORDS__MASK;
1539 }
1540 
1541 #define REG_CP_MEMCPY_1						0x00000001
1542 #define CP_MEMCPY_1_SRC_LO__MASK				0xffffffff
1543 #define CP_MEMCPY_1_SRC_LO__SHIFT				0
1544 static inline uint32_t CP_MEMCPY_1_SRC_LO(uint32_t val)
1545 {
1546 	return ((val) << CP_MEMCPY_1_SRC_LO__SHIFT) & CP_MEMCPY_1_SRC_LO__MASK;
1547 }
1548 
1549 #define REG_CP_MEMCPY_2						0x00000002
1550 #define CP_MEMCPY_2_SRC_HI__MASK				0xffffffff
1551 #define CP_MEMCPY_2_SRC_HI__SHIFT				0
1552 static inline uint32_t CP_MEMCPY_2_SRC_HI(uint32_t val)
1553 {
1554 	return ((val) << CP_MEMCPY_2_SRC_HI__SHIFT) & CP_MEMCPY_2_SRC_HI__MASK;
1555 }
1556 
1557 #define REG_CP_MEMCPY_3						0x00000003
1558 #define CP_MEMCPY_3_DST_LO__MASK				0xffffffff
1559 #define CP_MEMCPY_3_DST_LO__SHIFT				0
1560 static inline uint32_t CP_MEMCPY_3_DST_LO(uint32_t val)
1561 {
1562 	return ((val) << CP_MEMCPY_3_DST_LO__SHIFT) & CP_MEMCPY_3_DST_LO__MASK;
1563 }
1564 
1565 #define REG_CP_MEMCPY_4						0x00000004
1566 #define CP_MEMCPY_4_DST_HI__MASK				0xffffffff
1567 #define CP_MEMCPY_4_DST_HI__SHIFT				0
1568 static inline uint32_t CP_MEMCPY_4_DST_HI(uint32_t val)
1569 {
1570 	return ((val) << CP_MEMCPY_4_DST_HI__SHIFT) & CP_MEMCPY_4_DST_HI__MASK;
1571 }
1572 
1573 #define REG_CP_REG_TO_SCRATCH_0					0x00000000
1574 #define CP_REG_TO_SCRATCH_0_REG__MASK				0x0003ffff
1575 #define CP_REG_TO_SCRATCH_0_REG__SHIFT				0
1576 static inline uint32_t CP_REG_TO_SCRATCH_0_REG(uint32_t val)
1577 {
1578 	return ((val) << CP_REG_TO_SCRATCH_0_REG__SHIFT) & CP_REG_TO_SCRATCH_0_REG__MASK;
1579 }
1580 #define CP_REG_TO_SCRATCH_0_SCRATCH__MASK			0x00700000
1581 #define CP_REG_TO_SCRATCH_0_SCRATCH__SHIFT			20
1582 static inline uint32_t CP_REG_TO_SCRATCH_0_SCRATCH(uint32_t val)
1583 {
1584 	return ((val) << CP_REG_TO_SCRATCH_0_SCRATCH__SHIFT) & CP_REG_TO_SCRATCH_0_SCRATCH__MASK;
1585 }
1586 #define CP_REG_TO_SCRATCH_0_CNT__MASK				0x07000000
1587 #define CP_REG_TO_SCRATCH_0_CNT__SHIFT				24
1588 static inline uint32_t CP_REG_TO_SCRATCH_0_CNT(uint32_t val)
1589 {
1590 	return ((val) << CP_REG_TO_SCRATCH_0_CNT__SHIFT) & CP_REG_TO_SCRATCH_0_CNT__MASK;
1591 }
1592 
1593 #define REG_CP_SCRATCH_TO_REG_0					0x00000000
1594 #define CP_SCRATCH_TO_REG_0_REG__MASK				0x0003ffff
1595 #define CP_SCRATCH_TO_REG_0_REG__SHIFT				0
1596 static inline uint32_t CP_SCRATCH_TO_REG_0_REG(uint32_t val)
1597 {
1598 	return ((val) << CP_SCRATCH_TO_REG_0_REG__SHIFT) & CP_SCRATCH_TO_REG_0_REG__MASK;
1599 }
1600 #define CP_SCRATCH_TO_REG_0_UNK18				0x00040000
1601 #define CP_SCRATCH_TO_REG_0_SCRATCH__MASK			0x00700000
1602 #define CP_SCRATCH_TO_REG_0_SCRATCH__SHIFT			20
1603 static inline uint32_t CP_SCRATCH_TO_REG_0_SCRATCH(uint32_t val)
1604 {
1605 	return ((val) << CP_SCRATCH_TO_REG_0_SCRATCH__SHIFT) & CP_SCRATCH_TO_REG_0_SCRATCH__MASK;
1606 }
1607 #define CP_SCRATCH_TO_REG_0_CNT__MASK				0x07000000
1608 #define CP_SCRATCH_TO_REG_0_CNT__SHIFT				24
1609 static inline uint32_t CP_SCRATCH_TO_REG_0_CNT(uint32_t val)
1610 {
1611 	return ((val) << CP_SCRATCH_TO_REG_0_CNT__SHIFT) & CP_SCRATCH_TO_REG_0_CNT__MASK;
1612 }
1613 
1614 #define REG_CP_SCRATCH_WRITE_0					0x00000000
1615 #define CP_SCRATCH_WRITE_0_SCRATCH__MASK			0x00700000
1616 #define CP_SCRATCH_WRITE_0_SCRATCH__SHIFT			20
1617 static inline uint32_t CP_SCRATCH_WRITE_0_SCRATCH(uint32_t val)
1618 {
1619 	return ((val) << CP_SCRATCH_WRITE_0_SCRATCH__SHIFT) & CP_SCRATCH_WRITE_0_SCRATCH__MASK;
1620 }
1621 
1622 #define REG_CP_MEM_WRITE_0					0x00000000
1623 #define CP_MEM_WRITE_0_ADDR_LO__MASK				0xffffffff
1624 #define CP_MEM_WRITE_0_ADDR_LO__SHIFT				0
1625 static inline uint32_t CP_MEM_WRITE_0_ADDR_LO(uint32_t val)
1626 {
1627 	return ((val) << CP_MEM_WRITE_0_ADDR_LO__SHIFT) & CP_MEM_WRITE_0_ADDR_LO__MASK;
1628 }
1629 
1630 #define REG_CP_MEM_WRITE_1					0x00000001
1631 #define CP_MEM_WRITE_1_ADDR_HI__MASK				0xffffffff
1632 #define CP_MEM_WRITE_1_ADDR_HI__SHIFT				0
1633 static inline uint32_t CP_MEM_WRITE_1_ADDR_HI(uint32_t val)
1634 {
1635 	return ((val) << CP_MEM_WRITE_1_ADDR_HI__SHIFT) & CP_MEM_WRITE_1_ADDR_HI__MASK;
1636 }
1637 
1638 #define REG_CP_COND_WRITE_0					0x00000000
1639 #define CP_COND_WRITE_0_FUNCTION__MASK				0x00000007
1640 #define CP_COND_WRITE_0_FUNCTION__SHIFT				0
1641 static inline uint32_t CP_COND_WRITE_0_FUNCTION(enum cp_cond_function val)
1642 {
1643 	return ((val) << CP_COND_WRITE_0_FUNCTION__SHIFT) & CP_COND_WRITE_0_FUNCTION__MASK;
1644 }
1645 #define CP_COND_WRITE_0_POLL_MEMORY				0x00000010
1646 #define CP_COND_WRITE_0_WRITE_MEMORY				0x00000100
1647 
1648 #define REG_CP_COND_WRITE_1					0x00000001
1649 #define CP_COND_WRITE_1_POLL_ADDR__MASK				0xffffffff
1650 #define CP_COND_WRITE_1_POLL_ADDR__SHIFT			0
1651 static inline uint32_t CP_COND_WRITE_1_POLL_ADDR(uint32_t val)
1652 {
1653 	return ((val) << CP_COND_WRITE_1_POLL_ADDR__SHIFT) & CP_COND_WRITE_1_POLL_ADDR__MASK;
1654 }
1655 
1656 #define REG_CP_COND_WRITE_2					0x00000002
1657 #define CP_COND_WRITE_2_REF__MASK				0xffffffff
1658 #define CP_COND_WRITE_2_REF__SHIFT				0
1659 static inline uint32_t CP_COND_WRITE_2_REF(uint32_t val)
1660 {
1661 	return ((val) << CP_COND_WRITE_2_REF__SHIFT) & CP_COND_WRITE_2_REF__MASK;
1662 }
1663 
1664 #define REG_CP_COND_WRITE_3					0x00000003
1665 #define CP_COND_WRITE_3_MASK__MASK				0xffffffff
1666 #define CP_COND_WRITE_3_MASK__SHIFT				0
1667 static inline uint32_t CP_COND_WRITE_3_MASK(uint32_t val)
1668 {
1669 	return ((val) << CP_COND_WRITE_3_MASK__SHIFT) & CP_COND_WRITE_3_MASK__MASK;
1670 }
1671 
1672 #define REG_CP_COND_WRITE_4					0x00000004
1673 #define CP_COND_WRITE_4_WRITE_ADDR__MASK			0xffffffff
1674 #define CP_COND_WRITE_4_WRITE_ADDR__SHIFT			0
1675 static inline uint32_t CP_COND_WRITE_4_WRITE_ADDR(uint32_t val)
1676 {
1677 	return ((val) << CP_COND_WRITE_4_WRITE_ADDR__SHIFT) & CP_COND_WRITE_4_WRITE_ADDR__MASK;
1678 }
1679 
1680 #define REG_CP_COND_WRITE_5					0x00000005
1681 #define CP_COND_WRITE_5_WRITE_DATA__MASK			0xffffffff
1682 #define CP_COND_WRITE_5_WRITE_DATA__SHIFT			0
1683 static inline uint32_t CP_COND_WRITE_5_WRITE_DATA(uint32_t val)
1684 {
1685 	return ((val) << CP_COND_WRITE_5_WRITE_DATA__SHIFT) & CP_COND_WRITE_5_WRITE_DATA__MASK;
1686 }
1687 
1688 #define REG_CP_COND_WRITE5_0					0x00000000
1689 #define CP_COND_WRITE5_0_FUNCTION__MASK				0x00000007
1690 #define CP_COND_WRITE5_0_FUNCTION__SHIFT			0
1691 static inline uint32_t CP_COND_WRITE5_0_FUNCTION(enum cp_cond_function val)
1692 {
1693 	return ((val) << CP_COND_WRITE5_0_FUNCTION__SHIFT) & CP_COND_WRITE5_0_FUNCTION__MASK;
1694 }
1695 #define CP_COND_WRITE5_0_SIGNED_COMPARE				0x00000008
1696 #define CP_COND_WRITE5_0_POLL_MEMORY				0x00000010
1697 #define CP_COND_WRITE5_0_POLL_SCRATCH				0x00000020
1698 #define CP_COND_WRITE5_0_WRITE_MEMORY				0x00000100
1699 
1700 #define REG_CP_COND_WRITE5_1					0x00000001
1701 #define CP_COND_WRITE5_1_POLL_ADDR_LO__MASK			0xffffffff
1702 #define CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT			0
1703 static inline uint32_t CP_COND_WRITE5_1_POLL_ADDR_LO(uint32_t val)
1704 {
1705 	return ((val) << CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT) & CP_COND_WRITE5_1_POLL_ADDR_LO__MASK;
1706 }
1707 
1708 #define REG_CP_COND_WRITE5_2					0x00000002
1709 #define CP_COND_WRITE5_2_POLL_ADDR_HI__MASK			0xffffffff
1710 #define CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT			0
1711 static inline uint32_t CP_COND_WRITE5_2_POLL_ADDR_HI(uint32_t val)
1712 {
1713 	return ((val) << CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT) & CP_COND_WRITE5_2_POLL_ADDR_HI__MASK;
1714 }
1715 
1716 #define REG_CP_COND_WRITE5_3					0x00000003
1717 #define CP_COND_WRITE5_3_REF__MASK				0xffffffff
1718 #define CP_COND_WRITE5_3_REF__SHIFT				0
1719 static inline uint32_t CP_COND_WRITE5_3_REF(uint32_t val)
1720 {
1721 	return ((val) << CP_COND_WRITE5_3_REF__SHIFT) & CP_COND_WRITE5_3_REF__MASK;
1722 }
1723 
1724 #define REG_CP_COND_WRITE5_4					0x00000004
1725 #define CP_COND_WRITE5_4_MASK__MASK				0xffffffff
1726 #define CP_COND_WRITE5_4_MASK__SHIFT				0
1727 static inline uint32_t CP_COND_WRITE5_4_MASK(uint32_t val)
1728 {
1729 	return ((val) << CP_COND_WRITE5_4_MASK__SHIFT) & CP_COND_WRITE5_4_MASK__MASK;
1730 }
1731 
1732 #define REG_CP_COND_WRITE5_5					0x00000005
1733 #define CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK			0xffffffff
1734 #define CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT			0
1735 static inline uint32_t CP_COND_WRITE5_5_WRITE_ADDR_LO(uint32_t val)
1736 {
1737 	return ((val) << CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT) & CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK;
1738 }
1739 
1740 #define REG_CP_COND_WRITE5_6					0x00000006
1741 #define CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK			0xffffffff
1742 #define CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT			0
1743 static inline uint32_t CP_COND_WRITE5_6_WRITE_ADDR_HI(uint32_t val)
1744 {
1745 	return ((val) << CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT) & CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK;
1746 }
1747 
1748 #define REG_CP_COND_WRITE5_7					0x00000007
1749 #define CP_COND_WRITE5_7_WRITE_DATA__MASK			0xffffffff
1750 #define CP_COND_WRITE5_7_WRITE_DATA__SHIFT			0
1751 static inline uint32_t CP_COND_WRITE5_7_WRITE_DATA(uint32_t val)
1752 {
1753 	return ((val) << CP_COND_WRITE5_7_WRITE_DATA__SHIFT) & CP_COND_WRITE5_7_WRITE_DATA__MASK;
1754 }
1755 
1756 #define REG_CP_WAIT_MEM_GTE_0					0x00000000
1757 #define CP_WAIT_MEM_GTE_0_RESERVED__MASK			0xffffffff
1758 #define CP_WAIT_MEM_GTE_0_RESERVED__SHIFT			0
1759 static inline uint32_t CP_WAIT_MEM_GTE_0_RESERVED(uint32_t val)
1760 {
1761 	return ((val) << CP_WAIT_MEM_GTE_0_RESERVED__SHIFT) & CP_WAIT_MEM_GTE_0_RESERVED__MASK;
1762 }
1763 
1764 #define REG_CP_WAIT_MEM_GTE_1					0x00000001
1765 #define CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__MASK			0xffffffff
1766 #define CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__SHIFT			0
1767 static inline uint32_t CP_WAIT_MEM_GTE_1_POLL_ADDR_LO(uint32_t val)
1768 {
1769 	return ((val) << CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__SHIFT) & CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__MASK;
1770 }
1771 
1772 #define REG_CP_WAIT_MEM_GTE_2					0x00000002
1773 #define CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__MASK			0xffffffff
1774 #define CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__SHIFT			0
1775 static inline uint32_t CP_WAIT_MEM_GTE_2_POLL_ADDR_HI(uint32_t val)
1776 {
1777 	return ((val) << CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__SHIFT) & CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__MASK;
1778 }
1779 
1780 #define REG_CP_WAIT_MEM_GTE_3					0x00000003
1781 #define CP_WAIT_MEM_GTE_3_REF__MASK				0xffffffff
1782 #define CP_WAIT_MEM_GTE_3_REF__SHIFT				0
1783 static inline uint32_t CP_WAIT_MEM_GTE_3_REF(uint32_t val)
1784 {
1785 	return ((val) << CP_WAIT_MEM_GTE_3_REF__SHIFT) & CP_WAIT_MEM_GTE_3_REF__MASK;
1786 }
1787 
1788 #define REG_CP_WAIT_REG_MEM_0					0x00000000
1789 #define CP_WAIT_REG_MEM_0_FUNCTION__MASK			0x00000007
1790 #define CP_WAIT_REG_MEM_0_FUNCTION__SHIFT			0
1791 static inline uint32_t CP_WAIT_REG_MEM_0_FUNCTION(enum cp_cond_function val)
1792 {
1793 	return ((val) << CP_WAIT_REG_MEM_0_FUNCTION__SHIFT) & CP_WAIT_REG_MEM_0_FUNCTION__MASK;
1794 }
1795 #define CP_WAIT_REG_MEM_0_SIGNED_COMPARE			0x00000008
1796 #define CP_WAIT_REG_MEM_0_POLL_MEMORY				0x00000010
1797 #define CP_WAIT_REG_MEM_0_POLL_SCRATCH				0x00000020
1798 #define CP_WAIT_REG_MEM_0_WRITE_MEMORY				0x00000100
1799 
1800 #define REG_CP_WAIT_REG_MEM_1					0x00000001
1801 #define CP_WAIT_REG_MEM_1_POLL_ADDR_LO__MASK			0xffffffff
1802 #define CP_WAIT_REG_MEM_1_POLL_ADDR_LO__SHIFT			0
1803 static inline uint32_t CP_WAIT_REG_MEM_1_POLL_ADDR_LO(uint32_t val)
1804 {
1805 	return ((val) << CP_WAIT_REG_MEM_1_POLL_ADDR_LO__SHIFT) & CP_WAIT_REG_MEM_1_POLL_ADDR_LO__MASK;
1806 }
1807 
1808 #define REG_CP_WAIT_REG_MEM_2					0x00000002
1809 #define CP_WAIT_REG_MEM_2_POLL_ADDR_HI__MASK			0xffffffff
1810 #define CP_WAIT_REG_MEM_2_POLL_ADDR_HI__SHIFT			0
1811 static inline uint32_t CP_WAIT_REG_MEM_2_POLL_ADDR_HI(uint32_t val)
1812 {
1813 	return ((val) << CP_WAIT_REG_MEM_2_POLL_ADDR_HI__SHIFT) & CP_WAIT_REG_MEM_2_POLL_ADDR_HI__MASK;
1814 }
1815 
1816 #define REG_CP_WAIT_REG_MEM_3					0x00000003
1817 #define CP_WAIT_REG_MEM_3_REF__MASK				0xffffffff
1818 #define CP_WAIT_REG_MEM_3_REF__SHIFT				0
1819 static inline uint32_t CP_WAIT_REG_MEM_3_REF(uint32_t val)
1820 {
1821 	return ((val) << CP_WAIT_REG_MEM_3_REF__SHIFT) & CP_WAIT_REG_MEM_3_REF__MASK;
1822 }
1823 
1824 #define REG_CP_WAIT_REG_MEM_4					0x00000004
1825 #define CP_WAIT_REG_MEM_4_MASK__MASK				0xffffffff
1826 #define CP_WAIT_REG_MEM_4_MASK__SHIFT				0
1827 static inline uint32_t CP_WAIT_REG_MEM_4_MASK(uint32_t val)
1828 {
1829 	return ((val) << CP_WAIT_REG_MEM_4_MASK__SHIFT) & CP_WAIT_REG_MEM_4_MASK__MASK;
1830 }
1831 
1832 #define REG_CP_WAIT_REG_MEM_5					0x00000005
1833 #define CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__MASK		0xffffffff
1834 #define CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__SHIFT		0
1835 static inline uint32_t CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(uint32_t val)
1836 {
1837 	return ((val) << CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__SHIFT) & CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__MASK;
1838 }
1839 
1840 #define REG_CP_WAIT_TWO_REGS_0					0x00000000
1841 #define CP_WAIT_TWO_REGS_0_REG0__MASK				0x0003ffff
1842 #define CP_WAIT_TWO_REGS_0_REG0__SHIFT				0
1843 static inline uint32_t CP_WAIT_TWO_REGS_0_REG0(uint32_t val)
1844 {
1845 	return ((val) << CP_WAIT_TWO_REGS_0_REG0__SHIFT) & CP_WAIT_TWO_REGS_0_REG0__MASK;
1846 }
1847 
1848 #define REG_CP_WAIT_TWO_REGS_1					0x00000001
1849 #define CP_WAIT_TWO_REGS_1_REG1__MASK				0x0003ffff
1850 #define CP_WAIT_TWO_REGS_1_REG1__SHIFT				0
1851 static inline uint32_t CP_WAIT_TWO_REGS_1_REG1(uint32_t val)
1852 {
1853 	return ((val) << CP_WAIT_TWO_REGS_1_REG1__SHIFT) & CP_WAIT_TWO_REGS_1_REG1__MASK;
1854 }
1855 
1856 #define REG_CP_WAIT_TWO_REGS_2					0x00000002
1857 #define CP_WAIT_TWO_REGS_2_REF__MASK				0xffffffff
1858 #define CP_WAIT_TWO_REGS_2_REF__SHIFT				0
1859 static inline uint32_t CP_WAIT_TWO_REGS_2_REF(uint32_t val)
1860 {
1861 	return ((val) << CP_WAIT_TWO_REGS_2_REF__SHIFT) & CP_WAIT_TWO_REGS_2_REF__MASK;
1862 }
1863 
1864 #define REG_CP_DISPATCH_COMPUTE_0				0x00000000
1865 
1866 #define REG_CP_DISPATCH_COMPUTE_1				0x00000001
1867 #define CP_DISPATCH_COMPUTE_1_X__MASK				0xffffffff
1868 #define CP_DISPATCH_COMPUTE_1_X__SHIFT				0
1869 static inline uint32_t CP_DISPATCH_COMPUTE_1_X(uint32_t val)
1870 {
1871 	return ((val) << CP_DISPATCH_COMPUTE_1_X__SHIFT) & CP_DISPATCH_COMPUTE_1_X__MASK;
1872 }
1873 
1874 #define REG_CP_DISPATCH_COMPUTE_2				0x00000002
1875 #define CP_DISPATCH_COMPUTE_2_Y__MASK				0xffffffff
1876 #define CP_DISPATCH_COMPUTE_2_Y__SHIFT				0
1877 static inline uint32_t CP_DISPATCH_COMPUTE_2_Y(uint32_t val)
1878 {
1879 	return ((val) << CP_DISPATCH_COMPUTE_2_Y__SHIFT) & CP_DISPATCH_COMPUTE_2_Y__MASK;
1880 }
1881 
1882 #define REG_CP_DISPATCH_COMPUTE_3				0x00000003
1883 #define CP_DISPATCH_COMPUTE_3_Z__MASK				0xffffffff
1884 #define CP_DISPATCH_COMPUTE_3_Z__SHIFT				0
1885 static inline uint32_t CP_DISPATCH_COMPUTE_3_Z(uint32_t val)
1886 {
1887 	return ((val) << CP_DISPATCH_COMPUTE_3_Z__SHIFT) & CP_DISPATCH_COMPUTE_3_Z__MASK;
1888 }
1889 
1890 #define REG_CP_SET_RENDER_MODE_0				0x00000000
1891 #define CP_SET_RENDER_MODE_0_MODE__MASK				0x000001ff
1892 #define CP_SET_RENDER_MODE_0_MODE__SHIFT			0
1893 static inline uint32_t CP_SET_RENDER_MODE_0_MODE(enum render_mode_cmd val)
1894 {
1895 	return ((val) << CP_SET_RENDER_MODE_0_MODE__SHIFT) & CP_SET_RENDER_MODE_0_MODE__MASK;
1896 }
1897 
1898 #define REG_CP_SET_RENDER_MODE_1				0x00000001
1899 #define CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK			0xffffffff
1900 #define CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT			0
1901 static inline uint32_t CP_SET_RENDER_MODE_1_ADDR_0_LO(uint32_t val)
1902 {
1903 	return ((val) << CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT) & CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK;
1904 }
1905 
1906 #define REG_CP_SET_RENDER_MODE_2				0x00000002
1907 #define CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK			0xffffffff
1908 #define CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT			0
1909 static inline uint32_t CP_SET_RENDER_MODE_2_ADDR_0_HI(uint32_t val)
1910 {
1911 	return ((val) << CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT) & CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK;
1912 }
1913 
1914 #define REG_CP_SET_RENDER_MODE_3				0x00000003
1915 #define CP_SET_RENDER_MODE_3_VSC_ENABLE				0x00000008
1916 #define CP_SET_RENDER_MODE_3_GMEM_ENABLE			0x00000010
1917 
1918 #define REG_CP_SET_RENDER_MODE_4				0x00000004
1919 
1920 #define REG_CP_SET_RENDER_MODE_5				0x00000005
1921 #define CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK			0xffffffff
1922 #define CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT			0
1923 static inline uint32_t CP_SET_RENDER_MODE_5_ADDR_1_LEN(uint32_t val)
1924 {
1925 	return ((val) << CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT) & CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK;
1926 }
1927 
1928 #define REG_CP_SET_RENDER_MODE_6				0x00000006
1929 #define CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK			0xffffffff
1930 #define CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT			0
1931 static inline uint32_t CP_SET_RENDER_MODE_6_ADDR_1_LO(uint32_t val)
1932 {
1933 	return ((val) << CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT) & CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK;
1934 }
1935 
1936 #define REG_CP_SET_RENDER_MODE_7				0x00000007
1937 #define CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK			0xffffffff
1938 #define CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT			0
1939 static inline uint32_t CP_SET_RENDER_MODE_7_ADDR_1_HI(uint32_t val)
1940 {
1941 	return ((val) << CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT) & CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK;
1942 }
1943 
1944 #define REG_CP_COMPUTE_CHECKPOINT_0				0x00000000
1945 #define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK			0xffffffff
1946 #define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT		0
1947 static inline uint32_t CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO(uint32_t val)
1948 {
1949 	return ((val) << CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK;
1950 }
1951 
1952 #define REG_CP_COMPUTE_CHECKPOINT_1				0x00000001
1953 #define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK			0xffffffff
1954 #define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT		0
1955 static inline uint32_t CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI(uint32_t val)
1956 {
1957 	return ((val) << CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK;
1958 }
1959 
1960 #define REG_CP_COMPUTE_CHECKPOINT_2				0x00000002
1961 
1962 #define REG_CP_COMPUTE_CHECKPOINT_3				0x00000003
1963 #define CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__MASK		0xffffffff
1964 #define CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__SHIFT		0
1965 static inline uint32_t CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN(uint32_t val)
1966 {
1967 	return ((val) << CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__SHIFT) & CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__MASK;
1968 }
1969 
1970 #define REG_CP_COMPUTE_CHECKPOINT_4				0x00000004
1971 
1972 #define REG_CP_COMPUTE_CHECKPOINT_5				0x00000005
1973 #define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK			0xffffffff
1974 #define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT		0
1975 static inline uint32_t CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO(uint32_t val)
1976 {
1977 	return ((val) << CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK;
1978 }
1979 
1980 #define REG_CP_COMPUTE_CHECKPOINT_6				0x00000006
1981 #define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK			0xffffffff
1982 #define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT		0
1983 static inline uint32_t CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI(uint32_t val)
1984 {
1985 	return ((val) << CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK;
1986 }
1987 
1988 #define REG_CP_COMPUTE_CHECKPOINT_7				0x00000007
1989 
1990 #define REG_CP_PERFCOUNTER_ACTION_0				0x00000000
1991 
1992 #define REG_CP_PERFCOUNTER_ACTION_1				0x00000001
1993 #define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK			0xffffffff
1994 #define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT		0
1995 static inline uint32_t CP_PERFCOUNTER_ACTION_1_ADDR_0_LO(uint32_t val)
1996 {
1997 	return ((val) << CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT) & CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK;
1998 }
1999 
2000 #define REG_CP_PERFCOUNTER_ACTION_2				0x00000002
2001 #define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK			0xffffffff
2002 #define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT		0
2003 static inline uint32_t CP_PERFCOUNTER_ACTION_2_ADDR_0_HI(uint32_t val)
2004 {
2005 	return ((val) << CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT) & CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK;
2006 }
2007 
2008 #define REG_CP_EVENT_WRITE_0					0x00000000
2009 #define CP_EVENT_WRITE_0_EVENT__MASK				0x000000ff
2010 #define CP_EVENT_WRITE_0_EVENT__SHIFT				0
2011 static inline uint32_t CP_EVENT_WRITE_0_EVENT(enum vgt_event_type val)
2012 {
2013 	return ((val) << CP_EVENT_WRITE_0_EVENT__SHIFT) & CP_EVENT_WRITE_0_EVENT__MASK;
2014 }
2015 #define CP_EVENT_WRITE_0_TIMESTAMP				0x40000000
2016 #define CP_EVENT_WRITE_0_IRQ					0x80000000
2017 
2018 #define REG_CP_EVENT_WRITE_1					0x00000001
2019 #define CP_EVENT_WRITE_1_ADDR_0_LO__MASK			0xffffffff
2020 #define CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT			0
2021 static inline uint32_t CP_EVENT_WRITE_1_ADDR_0_LO(uint32_t val)
2022 {
2023 	return ((val) << CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT) & CP_EVENT_WRITE_1_ADDR_0_LO__MASK;
2024 }
2025 
2026 #define REG_CP_EVENT_WRITE_2					0x00000002
2027 #define CP_EVENT_WRITE_2_ADDR_0_HI__MASK			0xffffffff
2028 #define CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT			0
2029 static inline uint32_t CP_EVENT_WRITE_2_ADDR_0_HI(uint32_t val)
2030 {
2031 	return ((val) << CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT) & CP_EVENT_WRITE_2_ADDR_0_HI__MASK;
2032 }
2033 
2034 #define REG_CP_EVENT_WRITE_3					0x00000003
2035 
2036 #define REG_CP_BLIT_0						0x00000000
2037 #define CP_BLIT_0_OP__MASK					0x0000000f
2038 #define CP_BLIT_0_OP__SHIFT					0
2039 static inline uint32_t CP_BLIT_0_OP(enum cp_blit_cmd val)
2040 {
2041 	return ((val) << CP_BLIT_0_OP__SHIFT) & CP_BLIT_0_OP__MASK;
2042 }
2043 
2044 #define REG_CP_BLIT_1						0x00000001
2045 #define CP_BLIT_1_SRC_X1__MASK					0x00003fff
2046 #define CP_BLIT_1_SRC_X1__SHIFT					0
2047 static inline uint32_t CP_BLIT_1_SRC_X1(uint32_t val)
2048 {
2049 	return ((val) << CP_BLIT_1_SRC_X1__SHIFT) & CP_BLIT_1_SRC_X1__MASK;
2050 }
2051 #define CP_BLIT_1_SRC_Y1__MASK					0x3fff0000
2052 #define CP_BLIT_1_SRC_Y1__SHIFT					16
2053 static inline uint32_t CP_BLIT_1_SRC_Y1(uint32_t val)
2054 {
2055 	return ((val) << CP_BLIT_1_SRC_Y1__SHIFT) & CP_BLIT_1_SRC_Y1__MASK;
2056 }
2057 
2058 #define REG_CP_BLIT_2						0x00000002
2059 #define CP_BLIT_2_SRC_X2__MASK					0x00003fff
2060 #define CP_BLIT_2_SRC_X2__SHIFT					0
2061 static inline uint32_t CP_BLIT_2_SRC_X2(uint32_t val)
2062 {
2063 	return ((val) << CP_BLIT_2_SRC_X2__SHIFT) & CP_BLIT_2_SRC_X2__MASK;
2064 }
2065 #define CP_BLIT_2_SRC_Y2__MASK					0x3fff0000
2066 #define CP_BLIT_2_SRC_Y2__SHIFT					16
2067 static inline uint32_t CP_BLIT_2_SRC_Y2(uint32_t val)
2068 {
2069 	return ((val) << CP_BLIT_2_SRC_Y2__SHIFT) & CP_BLIT_2_SRC_Y2__MASK;
2070 }
2071 
2072 #define REG_CP_BLIT_3						0x00000003
2073 #define CP_BLIT_3_DST_X1__MASK					0x00003fff
2074 #define CP_BLIT_3_DST_X1__SHIFT					0
2075 static inline uint32_t CP_BLIT_3_DST_X1(uint32_t val)
2076 {
2077 	return ((val) << CP_BLIT_3_DST_X1__SHIFT) & CP_BLIT_3_DST_X1__MASK;
2078 }
2079 #define CP_BLIT_3_DST_Y1__MASK					0x3fff0000
2080 #define CP_BLIT_3_DST_Y1__SHIFT					16
2081 static inline uint32_t CP_BLIT_3_DST_Y1(uint32_t val)
2082 {
2083 	return ((val) << CP_BLIT_3_DST_Y1__SHIFT) & CP_BLIT_3_DST_Y1__MASK;
2084 }
2085 
2086 #define REG_CP_BLIT_4						0x00000004
2087 #define CP_BLIT_4_DST_X2__MASK					0x00003fff
2088 #define CP_BLIT_4_DST_X2__SHIFT					0
2089 static inline uint32_t CP_BLIT_4_DST_X2(uint32_t val)
2090 {
2091 	return ((val) << CP_BLIT_4_DST_X2__SHIFT) & CP_BLIT_4_DST_X2__MASK;
2092 }
2093 #define CP_BLIT_4_DST_Y2__MASK					0x3fff0000
2094 #define CP_BLIT_4_DST_Y2__SHIFT					16
2095 static inline uint32_t CP_BLIT_4_DST_Y2(uint32_t val)
2096 {
2097 	return ((val) << CP_BLIT_4_DST_Y2__SHIFT) & CP_BLIT_4_DST_Y2__MASK;
2098 }
2099 
2100 #define REG_CP_EXEC_CS_0					0x00000000
2101 
2102 #define REG_CP_EXEC_CS_1					0x00000001
2103 #define CP_EXEC_CS_1_NGROUPS_X__MASK				0xffffffff
2104 #define CP_EXEC_CS_1_NGROUPS_X__SHIFT				0
2105 static inline uint32_t CP_EXEC_CS_1_NGROUPS_X(uint32_t val)
2106 {
2107 	return ((val) << CP_EXEC_CS_1_NGROUPS_X__SHIFT) & CP_EXEC_CS_1_NGROUPS_X__MASK;
2108 }
2109 
2110 #define REG_CP_EXEC_CS_2					0x00000002
2111 #define CP_EXEC_CS_2_NGROUPS_Y__MASK				0xffffffff
2112 #define CP_EXEC_CS_2_NGROUPS_Y__SHIFT				0
2113 static inline uint32_t CP_EXEC_CS_2_NGROUPS_Y(uint32_t val)
2114 {
2115 	return ((val) << CP_EXEC_CS_2_NGROUPS_Y__SHIFT) & CP_EXEC_CS_2_NGROUPS_Y__MASK;
2116 }
2117 
2118 #define REG_CP_EXEC_CS_3					0x00000003
2119 #define CP_EXEC_CS_3_NGROUPS_Z__MASK				0xffffffff
2120 #define CP_EXEC_CS_3_NGROUPS_Z__SHIFT				0
2121 static inline uint32_t CP_EXEC_CS_3_NGROUPS_Z(uint32_t val)
2122 {
2123 	return ((val) << CP_EXEC_CS_3_NGROUPS_Z__SHIFT) & CP_EXEC_CS_3_NGROUPS_Z__MASK;
2124 }
2125 
2126 #define REG_A4XX_CP_EXEC_CS_INDIRECT_0				0x00000000
2127 
2128 
2129 #define REG_A4XX_CP_EXEC_CS_INDIRECT_1				0x00000001
2130 #define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK			0xffffffff
2131 #define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT			0
2132 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_1_ADDR(uint32_t val)
2133 {
2134 	return ((val) << A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK;
2135 }
2136 
2137 #define REG_A4XX_CP_EXEC_CS_INDIRECT_2				0x00000002
2138 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK		0x00000ffc
2139 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT		2
2140 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX(uint32_t val)
2141 {
2142 	return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK;
2143 }
2144 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK		0x003ff000
2145 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT		12
2146 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY(uint32_t val)
2147 {
2148 	return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK;
2149 }
2150 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK		0xffc00000
2151 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT		22
2152 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ(uint32_t val)
2153 {
2154 	return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK;
2155 }
2156 
2157 
2158 #define REG_A5XX_CP_EXEC_CS_INDIRECT_1				0x00000001
2159 #define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK		0xffffffff
2160 #define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT		0
2161 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO(uint32_t val)
2162 {
2163 	return ((val) << A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK;
2164 }
2165 
2166 #define REG_A5XX_CP_EXEC_CS_INDIRECT_2				0x00000002
2167 #define A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK		0xffffffff
2168 #define A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT		0
2169 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI(uint32_t val)
2170 {
2171 	return ((val) << A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK;
2172 }
2173 
2174 #define REG_A5XX_CP_EXEC_CS_INDIRECT_3				0x00000003
2175 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK		0x00000ffc
2176 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT		2
2177 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(uint32_t val)
2178 {
2179 	return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK;
2180 }
2181 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK		0x003ff000
2182 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT		12
2183 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(uint32_t val)
2184 {
2185 	return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK;
2186 }
2187 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK		0xffc00000
2188 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT		22
2189 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(uint32_t val)
2190 {
2191 	return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK;
2192 }
2193 
2194 #define REG_A6XX_CP_SET_MARKER_0				0x00000000
2195 #define A6XX_CP_SET_MARKER_0_MODE__MASK				0x000001ff
2196 #define A6XX_CP_SET_MARKER_0_MODE__SHIFT			0
2197 static inline uint32_t A6XX_CP_SET_MARKER_0_MODE(enum a6xx_marker val)
2198 {
2199 	return ((val) << A6XX_CP_SET_MARKER_0_MODE__SHIFT) & A6XX_CP_SET_MARKER_0_MODE__MASK;
2200 }
2201 #define A6XX_CP_SET_MARKER_0_MARKER__MASK			0x0000000f
2202 #define A6XX_CP_SET_MARKER_0_MARKER__SHIFT			0
2203 static inline uint32_t A6XX_CP_SET_MARKER_0_MARKER(enum a6xx_marker val)
2204 {
2205 	return ((val) << A6XX_CP_SET_MARKER_0_MARKER__SHIFT) & A6XX_CP_SET_MARKER_0_MARKER__MASK;
2206 }
2207 
2208 static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG_(uint32_t i0) { return 0x00000000 + 0x3*i0; }
2209 
2210 static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG__0(uint32_t i0) { return 0x00000000 + 0x3*i0; }
2211 #define A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK		0x00000007
2212 #define A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT		0
2213 static inline uint32_t A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG(enum pseudo_reg val)
2214 {
2215 	return ((val) << A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT) & A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK;
2216 }
2217 
2218 static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG__1(uint32_t i0) { return 0x00000001 + 0x3*i0; }
2219 #define A6XX_CP_SET_PSEUDO_REG__1_LO__MASK			0xffffffff
2220 #define A6XX_CP_SET_PSEUDO_REG__1_LO__SHIFT			0
2221 static inline uint32_t A6XX_CP_SET_PSEUDO_REG__1_LO(uint32_t val)
2222 {
2223 	return ((val) << A6XX_CP_SET_PSEUDO_REG__1_LO__SHIFT) & A6XX_CP_SET_PSEUDO_REG__1_LO__MASK;
2224 }
2225 
2226 static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG__2(uint32_t i0) { return 0x00000002 + 0x3*i0; }
2227 #define A6XX_CP_SET_PSEUDO_REG__2_HI__MASK			0xffffffff
2228 #define A6XX_CP_SET_PSEUDO_REG__2_HI__SHIFT			0
2229 static inline uint32_t A6XX_CP_SET_PSEUDO_REG__2_HI(uint32_t val)
2230 {
2231 	return ((val) << A6XX_CP_SET_PSEUDO_REG__2_HI__SHIFT) & A6XX_CP_SET_PSEUDO_REG__2_HI__MASK;
2232 }
2233 
2234 #define REG_A6XX_CP_REG_TEST_0					0x00000000
2235 #define A6XX_CP_REG_TEST_0_REG__MASK				0x0003ffff
2236 #define A6XX_CP_REG_TEST_0_REG__SHIFT				0
2237 static inline uint32_t A6XX_CP_REG_TEST_0_REG(uint32_t val)
2238 {
2239 	return ((val) << A6XX_CP_REG_TEST_0_REG__SHIFT) & A6XX_CP_REG_TEST_0_REG__MASK;
2240 }
2241 #define A6XX_CP_REG_TEST_0_BIT__MASK				0x01f00000
2242 #define A6XX_CP_REG_TEST_0_BIT__SHIFT				20
2243 static inline uint32_t A6XX_CP_REG_TEST_0_BIT(uint32_t val)
2244 {
2245 	return ((val) << A6XX_CP_REG_TEST_0_BIT__SHIFT) & A6XX_CP_REG_TEST_0_BIT__MASK;
2246 }
2247 #define A6XX_CP_REG_TEST_0_SKIP_WAIT_FOR_ME			0x02000000
2248 #define A6XX_CP_REG_TEST_0_PRED_BIT__MASK			0x7c000000
2249 #define A6XX_CP_REG_TEST_0_PRED_BIT__SHIFT			26
2250 static inline uint32_t A6XX_CP_REG_TEST_0_PRED_BIT(uint32_t val)
2251 {
2252 	return ((val) << A6XX_CP_REG_TEST_0_PRED_BIT__SHIFT) & A6XX_CP_REG_TEST_0_PRED_BIT__MASK;
2253 }
2254 #define A6XX_CP_REG_TEST_0_PRED_UPDATE				0x80000000
2255 
2256 #define REG_A6XX_CP_REG_TEST_PRED_MASK				0x00000001
2257 
2258 #define REG_A6XX_CP_REG_TEST_PRED_VAL				0x00000002
2259 
2260 #define REG_CP_COND_REG_EXEC_0					0x00000000
2261 #define CP_COND_REG_EXEC_0_REG0__MASK				0x0003ffff
2262 #define CP_COND_REG_EXEC_0_REG0__SHIFT				0
2263 static inline uint32_t CP_COND_REG_EXEC_0_REG0(uint32_t val)
2264 {
2265 	return ((val) << CP_COND_REG_EXEC_0_REG0__SHIFT) & CP_COND_REG_EXEC_0_REG0__MASK;
2266 }
2267 #define CP_COND_REG_EXEC_0_PRED_BIT__MASK			0x007c0000
2268 #define CP_COND_REG_EXEC_0_PRED_BIT__SHIFT			18
2269 static inline uint32_t CP_COND_REG_EXEC_0_PRED_BIT(uint32_t val)
2270 {
2271 	return ((val) << CP_COND_REG_EXEC_0_PRED_BIT__SHIFT) & CP_COND_REG_EXEC_0_PRED_BIT__MASK;
2272 }
2273 #define CP_COND_REG_EXEC_0_BINNING				0x02000000
2274 #define CP_COND_REG_EXEC_0_GMEM					0x04000000
2275 #define CP_COND_REG_EXEC_0_SYSMEM				0x08000000
2276 #define CP_COND_REG_EXEC_0_MODE__MASK				0xf0000000
2277 #define CP_COND_REG_EXEC_0_MODE__SHIFT				28
2278 static inline uint32_t CP_COND_REG_EXEC_0_MODE(enum compare_mode val)
2279 {
2280 	return ((val) << CP_COND_REG_EXEC_0_MODE__SHIFT) & CP_COND_REG_EXEC_0_MODE__MASK;
2281 }
2282 
2283 #define REG_CP_COND_REG_EXEC_1					0x00000001
2284 #define CP_COND_REG_EXEC_1_DWORDS__MASK				0xffffffff
2285 #define CP_COND_REG_EXEC_1_DWORDS__SHIFT			0
2286 static inline uint32_t CP_COND_REG_EXEC_1_DWORDS(uint32_t val)
2287 {
2288 	return ((val) << CP_COND_REG_EXEC_1_DWORDS__SHIFT) & CP_COND_REG_EXEC_1_DWORDS__MASK;
2289 }
2290 
2291 #define REG_CP_COND_EXEC_0					0x00000000
2292 #define CP_COND_EXEC_0_ADDR0_LO__MASK				0xffffffff
2293 #define CP_COND_EXEC_0_ADDR0_LO__SHIFT				0
2294 static inline uint32_t CP_COND_EXEC_0_ADDR0_LO(uint32_t val)
2295 {
2296 	return ((val) << CP_COND_EXEC_0_ADDR0_LO__SHIFT) & CP_COND_EXEC_0_ADDR0_LO__MASK;
2297 }
2298 
2299 #define REG_CP_COND_EXEC_1					0x00000001
2300 #define CP_COND_EXEC_1_ADDR0_HI__MASK				0xffffffff
2301 #define CP_COND_EXEC_1_ADDR0_HI__SHIFT				0
2302 static inline uint32_t CP_COND_EXEC_1_ADDR0_HI(uint32_t val)
2303 {
2304 	return ((val) << CP_COND_EXEC_1_ADDR0_HI__SHIFT) & CP_COND_EXEC_1_ADDR0_HI__MASK;
2305 }
2306 
2307 #define REG_CP_COND_EXEC_2					0x00000002
2308 #define CP_COND_EXEC_2_ADDR1_LO__MASK				0xffffffff
2309 #define CP_COND_EXEC_2_ADDR1_LO__SHIFT				0
2310 static inline uint32_t CP_COND_EXEC_2_ADDR1_LO(uint32_t val)
2311 {
2312 	return ((val) << CP_COND_EXEC_2_ADDR1_LO__SHIFT) & CP_COND_EXEC_2_ADDR1_LO__MASK;
2313 }
2314 
2315 #define REG_CP_COND_EXEC_3					0x00000003
2316 #define CP_COND_EXEC_3_ADDR1_HI__MASK				0xffffffff
2317 #define CP_COND_EXEC_3_ADDR1_HI__SHIFT				0
2318 static inline uint32_t CP_COND_EXEC_3_ADDR1_HI(uint32_t val)
2319 {
2320 	return ((val) << CP_COND_EXEC_3_ADDR1_HI__SHIFT) & CP_COND_EXEC_3_ADDR1_HI__MASK;
2321 }
2322 
2323 #define REG_CP_COND_EXEC_4					0x00000004
2324 #define CP_COND_EXEC_4_REF__MASK				0xffffffff
2325 #define CP_COND_EXEC_4_REF__SHIFT				0
2326 static inline uint32_t CP_COND_EXEC_4_REF(uint32_t val)
2327 {
2328 	return ((val) << CP_COND_EXEC_4_REF__SHIFT) & CP_COND_EXEC_4_REF__MASK;
2329 }
2330 
2331 #define REG_CP_COND_EXEC_5					0x00000005
2332 #define CP_COND_EXEC_5_DWORDS__MASK				0xffffffff
2333 #define CP_COND_EXEC_5_DWORDS__SHIFT				0
2334 static inline uint32_t CP_COND_EXEC_5_DWORDS(uint32_t val)
2335 {
2336 	return ((val) << CP_COND_EXEC_5_DWORDS__SHIFT) & CP_COND_EXEC_5_DWORDS__MASK;
2337 }
2338 
2339 #define REG_CP_SET_CTXSWITCH_IB_0				0x00000000
2340 #define CP_SET_CTXSWITCH_IB_0_ADDR_LO__MASK			0xffffffff
2341 #define CP_SET_CTXSWITCH_IB_0_ADDR_LO__SHIFT			0
2342 static inline uint32_t CP_SET_CTXSWITCH_IB_0_ADDR_LO(uint32_t val)
2343 {
2344 	return ((val) << CP_SET_CTXSWITCH_IB_0_ADDR_LO__SHIFT) & CP_SET_CTXSWITCH_IB_0_ADDR_LO__MASK;
2345 }
2346 
2347 #define REG_CP_SET_CTXSWITCH_IB_1				0x00000001
2348 #define CP_SET_CTXSWITCH_IB_1_ADDR_HI__MASK			0xffffffff
2349 #define CP_SET_CTXSWITCH_IB_1_ADDR_HI__SHIFT			0
2350 static inline uint32_t CP_SET_CTXSWITCH_IB_1_ADDR_HI(uint32_t val)
2351 {
2352 	return ((val) << CP_SET_CTXSWITCH_IB_1_ADDR_HI__SHIFT) & CP_SET_CTXSWITCH_IB_1_ADDR_HI__MASK;
2353 }
2354 
2355 #define REG_CP_SET_CTXSWITCH_IB_2				0x00000002
2356 #define CP_SET_CTXSWITCH_IB_2_DWORDS__MASK			0x000fffff
2357 #define CP_SET_CTXSWITCH_IB_2_DWORDS__SHIFT			0
2358 static inline uint32_t CP_SET_CTXSWITCH_IB_2_DWORDS(uint32_t val)
2359 {
2360 	return ((val) << CP_SET_CTXSWITCH_IB_2_DWORDS__SHIFT) & CP_SET_CTXSWITCH_IB_2_DWORDS__MASK;
2361 }
2362 #define CP_SET_CTXSWITCH_IB_2_TYPE__MASK			0x00300000
2363 #define CP_SET_CTXSWITCH_IB_2_TYPE__SHIFT			20
2364 static inline uint32_t CP_SET_CTXSWITCH_IB_2_TYPE(enum ctxswitch_ib val)
2365 {
2366 	return ((val) << CP_SET_CTXSWITCH_IB_2_TYPE__SHIFT) & CP_SET_CTXSWITCH_IB_2_TYPE__MASK;
2367 }
2368 
2369 #define REG_CP_REG_WRITE_0					0x00000000
2370 #define CP_REG_WRITE_0_TRACKER__MASK				0x0000000f
2371 #define CP_REG_WRITE_0_TRACKER__SHIFT				0
2372 static inline uint32_t CP_REG_WRITE_0_TRACKER(enum reg_tracker val)
2373 {
2374 	return ((val) << CP_REG_WRITE_0_TRACKER__SHIFT) & CP_REG_WRITE_0_TRACKER__MASK;
2375 }
2376 
2377 #define REG_CP_REG_WRITE_1					0x00000001
2378 
2379 #define REG_CP_REG_WRITE_2					0x00000002
2380 
2381 #define REG_CP_SMMU_TABLE_UPDATE_0				0x00000000
2382 #define CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__MASK			0xffffffff
2383 #define CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__SHIFT			0
2384 static inline uint32_t CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(uint32_t val)
2385 {
2386 	return ((val) << CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__SHIFT) & CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__MASK;
2387 }
2388 
2389 #define REG_CP_SMMU_TABLE_UPDATE_1				0x00000001
2390 #define CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__MASK			0x0000ffff
2391 #define CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__SHIFT			0
2392 static inline uint32_t CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(uint32_t val)
2393 {
2394 	return ((val) << CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__SHIFT) & CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__MASK;
2395 }
2396 #define CP_SMMU_TABLE_UPDATE_1_ASID__MASK			0xffff0000
2397 #define CP_SMMU_TABLE_UPDATE_1_ASID__SHIFT			16
2398 static inline uint32_t CP_SMMU_TABLE_UPDATE_1_ASID(uint32_t val)
2399 {
2400 	return ((val) << CP_SMMU_TABLE_UPDATE_1_ASID__SHIFT) & CP_SMMU_TABLE_UPDATE_1_ASID__MASK;
2401 }
2402 
2403 #define REG_CP_SMMU_TABLE_UPDATE_2				0x00000002
2404 #define CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__MASK			0xffffffff
2405 #define CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__SHIFT		0
2406 static inline uint32_t CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(uint32_t val)
2407 {
2408 	return ((val) << CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__SHIFT) & CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__MASK;
2409 }
2410 
2411 #define REG_CP_SMMU_TABLE_UPDATE_3				0x00000003
2412 #define CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__MASK		0xffffffff
2413 #define CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__SHIFT		0
2414 static inline uint32_t CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(uint32_t val)
2415 {
2416 	return ((val) << CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__SHIFT) & CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__MASK;
2417 }
2418 
2419 #define REG_CP_START_BIN_BIN_COUNT				0x00000000
2420 
2421 #define REG_CP_START_BIN_PREFIX_ADDR				0x00000001
2422 
2423 #define REG_CP_START_BIN_PREFIX_DWORDS				0x00000003
2424 
2425 #define REG_CP_START_BIN_BODY_DWORDS				0x00000004
2426 
2427 #define REG_CP_WAIT_TIMESTAMP_0					0x00000000
2428 
2429 #define REG_CP_WAIT_TIMESTAMP_ADDR				0x00000001
2430 
2431 #define REG_CP_WAIT_TIMESTAMP_TIMESTAMP				0x00000003
2432 
2433 #define REG_CP_THREAD_CONTROL_0					0x00000000
2434 #define CP_THREAD_CONTROL_0_THREAD__MASK			0x00000003
2435 #define CP_THREAD_CONTROL_0_THREAD__SHIFT			0
2436 static inline uint32_t CP_THREAD_CONTROL_0_THREAD(enum cp_thread val)
2437 {
2438 	return ((val) << CP_THREAD_CONTROL_0_THREAD__SHIFT) & CP_THREAD_CONTROL_0_THREAD__MASK;
2439 }
2440 #define CP_THREAD_CONTROL_0_CONCURRENT_BIN_DISABLE		0x08000000
2441 #define CP_THREAD_CONTROL_0_SYNC_THREADS			0x80000000
2442 
2443 
2444 #endif /* ADRENO_PM4_XML */
2445