1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 Red Hat 4 * Author: Rob Clark <robdclark@gmail.com> 5 * 6 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 7 */ 8 9 #include <linux/ascii85.h> 10 #include <linux/interconnect.h> 11 #include <linux/qcom_scm.h> 12 #include <linux/kernel.h> 13 #include <linux/of_address.h> 14 #include <linux/pm_opp.h> 15 #include <linux/slab.h> 16 #include <linux/soc/qcom/mdt_loader.h> 17 #include "adreno_gpu.h" 18 #include "msm_gem.h" 19 #include "msm_mmu.h" 20 21 static bool zap_available = true; 22 23 static int zap_shader_load_mdt(struct msm_gpu *gpu, const char *fwname, 24 u32 pasid) 25 { 26 struct device *dev = &gpu->pdev->dev; 27 const struct firmware *fw; 28 struct device_node *np, *mem_np; 29 struct resource r; 30 phys_addr_t mem_phys; 31 ssize_t mem_size; 32 void *mem_region = NULL; 33 int ret; 34 35 if (!IS_ENABLED(CONFIG_ARCH_QCOM)) { 36 zap_available = false; 37 return -EINVAL; 38 } 39 40 np = of_get_child_by_name(dev->of_node, "zap-shader"); 41 if (!np) { 42 zap_available = false; 43 return -ENODEV; 44 } 45 46 mem_np = of_parse_phandle(np, "memory-region", 0); 47 of_node_put(np); 48 if (!mem_np) { 49 zap_available = false; 50 return -EINVAL; 51 } 52 53 ret = of_address_to_resource(mem_np, 0, &r); 54 of_node_put(mem_np); 55 if (ret) 56 return ret; 57 58 mem_phys = r.start; 59 60 /* Request the MDT file for the firmware */ 61 fw = adreno_request_fw(to_adreno_gpu(gpu), fwname); 62 if (IS_ERR(fw)) { 63 DRM_DEV_ERROR(dev, "Unable to load %s\n", fwname); 64 return PTR_ERR(fw); 65 } 66 67 /* Figure out how much memory we need */ 68 mem_size = qcom_mdt_get_size(fw); 69 if (mem_size < 0) { 70 ret = mem_size; 71 goto out; 72 } 73 74 if (mem_size > resource_size(&r)) { 75 DRM_DEV_ERROR(dev, 76 "memory region is too small to load the MDT\n"); 77 ret = -E2BIG; 78 goto out; 79 } 80 81 /* Allocate memory for the firmware image */ 82 mem_region = memremap(mem_phys, mem_size, MEMREMAP_WC); 83 if (!mem_region) { 84 ret = -ENOMEM; 85 goto out; 86 } 87 88 /* 89 * Load the rest of the MDT 90 * 91 * Note that we could be dealing with two different paths, since 92 * with upstream linux-firmware it would be in a qcom/ subdir.. 93 * adreno_request_fw() handles this, but qcom_mdt_load() does 94 * not. But since we've already gotten through adreno_request_fw() 95 * we know which of the two cases it is: 96 */ 97 if (to_adreno_gpu(gpu)->fwloc == FW_LOCATION_LEGACY) { 98 ret = qcom_mdt_load(dev, fw, fwname, pasid, 99 mem_region, mem_phys, mem_size, NULL); 100 } else { 101 char *newname; 102 103 newname = kasprintf(GFP_KERNEL, "qcom/%s", fwname); 104 105 ret = qcom_mdt_load(dev, fw, newname, pasid, 106 mem_region, mem_phys, mem_size, NULL); 107 kfree(newname); 108 } 109 if (ret) 110 goto out; 111 112 /* Send the image to the secure world */ 113 ret = qcom_scm_pas_auth_and_reset(pasid); 114 115 /* 116 * If the scm call returns -EOPNOTSUPP we assume that this target 117 * doesn't need/support the zap shader so quietly fail 118 */ 119 if (ret == -EOPNOTSUPP) 120 zap_available = false; 121 else if (ret) 122 DRM_DEV_ERROR(dev, "Unable to authorize the image\n"); 123 124 out: 125 if (mem_region) 126 memunmap(mem_region); 127 128 release_firmware(fw); 129 130 return ret; 131 } 132 133 int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid) 134 { 135 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 136 struct platform_device *pdev = gpu->pdev; 137 138 /* Short cut if we determine the zap shader isn't available/needed */ 139 if (!zap_available) 140 return -ENODEV; 141 142 /* We need SCM to be able to load the firmware */ 143 if (!qcom_scm_is_available()) { 144 DRM_DEV_ERROR(&pdev->dev, "SCM is not available\n"); 145 return -EPROBE_DEFER; 146 } 147 148 /* Each GPU has a target specific zap shader firmware name to use */ 149 if (!adreno_gpu->info->zapfw) { 150 zap_available = false; 151 DRM_DEV_ERROR(&pdev->dev, 152 "Zap shader firmware file not specified for this target\n"); 153 return -ENODEV; 154 } 155 156 return zap_shader_load_mdt(gpu, adreno_gpu->info->zapfw, pasid); 157 } 158 159 int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value) 160 { 161 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 162 163 switch (param) { 164 case MSM_PARAM_GPU_ID: 165 *value = adreno_gpu->info->revn; 166 return 0; 167 case MSM_PARAM_GMEM_SIZE: 168 *value = adreno_gpu->gmem; 169 return 0; 170 case MSM_PARAM_GMEM_BASE: 171 *value = 0x100000; 172 return 0; 173 case MSM_PARAM_CHIP_ID: 174 *value = adreno_gpu->rev.patchid | 175 (adreno_gpu->rev.minor << 8) | 176 (adreno_gpu->rev.major << 16) | 177 (adreno_gpu->rev.core << 24); 178 return 0; 179 case MSM_PARAM_MAX_FREQ: 180 *value = adreno_gpu->base.fast_rate; 181 return 0; 182 case MSM_PARAM_TIMESTAMP: 183 if (adreno_gpu->funcs->get_timestamp) { 184 int ret; 185 186 pm_runtime_get_sync(&gpu->pdev->dev); 187 ret = adreno_gpu->funcs->get_timestamp(gpu, value); 188 pm_runtime_put_autosuspend(&gpu->pdev->dev); 189 190 return ret; 191 } 192 return -EINVAL; 193 case MSM_PARAM_NR_RINGS: 194 *value = gpu->nr_rings; 195 return 0; 196 case MSM_PARAM_PP_PGTABLE: 197 *value = 0; 198 return 0; 199 case MSM_PARAM_FAULTS: 200 *value = gpu->global_faults; 201 return 0; 202 default: 203 DBG("%s: invalid param: %u", gpu->name, param); 204 return -EINVAL; 205 } 206 } 207 208 const struct firmware * 209 adreno_request_fw(struct adreno_gpu *adreno_gpu, const char *fwname) 210 { 211 struct drm_device *drm = adreno_gpu->base.dev; 212 const struct firmware *fw = NULL; 213 char *newname; 214 int ret; 215 216 newname = kasprintf(GFP_KERNEL, "qcom/%s", fwname); 217 if (!newname) 218 return ERR_PTR(-ENOMEM); 219 220 /* 221 * Try first to load from qcom/$fwfile using a direct load (to avoid 222 * a potential timeout waiting for usermode helper) 223 */ 224 if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) || 225 (adreno_gpu->fwloc == FW_LOCATION_NEW)) { 226 227 ret = request_firmware_direct(&fw, newname, drm->dev); 228 if (!ret) { 229 DRM_DEV_INFO(drm->dev, "loaded %s from new location\n", 230 newname); 231 adreno_gpu->fwloc = FW_LOCATION_NEW; 232 goto out; 233 } else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) { 234 DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n", 235 newname, ret); 236 fw = ERR_PTR(ret); 237 goto out; 238 } 239 } 240 241 /* 242 * Then try the legacy location without qcom/ prefix 243 */ 244 if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) || 245 (adreno_gpu->fwloc == FW_LOCATION_LEGACY)) { 246 247 ret = request_firmware_direct(&fw, fwname, drm->dev); 248 if (!ret) { 249 DRM_DEV_INFO(drm->dev, "loaded %s from legacy location\n", 250 newname); 251 adreno_gpu->fwloc = FW_LOCATION_LEGACY; 252 goto out; 253 } else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) { 254 DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n", 255 fwname, ret); 256 fw = ERR_PTR(ret); 257 goto out; 258 } 259 } 260 261 /* 262 * Finally fall back to request_firmware() for cases where the 263 * usermode helper is needed (I think mainly android) 264 */ 265 if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) || 266 (adreno_gpu->fwloc == FW_LOCATION_HELPER)) { 267 268 ret = request_firmware(&fw, newname, drm->dev); 269 if (!ret) { 270 DRM_DEV_INFO(drm->dev, "loaded %s with helper\n", 271 newname); 272 adreno_gpu->fwloc = FW_LOCATION_HELPER; 273 goto out; 274 } else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) { 275 DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n", 276 newname, ret); 277 fw = ERR_PTR(ret); 278 goto out; 279 } 280 } 281 282 DRM_DEV_ERROR(drm->dev, "failed to load %s\n", fwname); 283 fw = ERR_PTR(-ENOENT); 284 out: 285 kfree(newname); 286 return fw; 287 } 288 289 int adreno_load_fw(struct adreno_gpu *adreno_gpu) 290 { 291 int i; 292 293 for (i = 0; i < ARRAY_SIZE(adreno_gpu->info->fw); i++) { 294 const struct firmware *fw; 295 296 if (!adreno_gpu->info->fw[i]) 297 continue; 298 299 /* Skip if the firmware has already been loaded */ 300 if (adreno_gpu->fw[i]) 301 continue; 302 303 fw = adreno_request_fw(adreno_gpu, adreno_gpu->info->fw[i]); 304 if (IS_ERR(fw)) 305 return PTR_ERR(fw); 306 307 adreno_gpu->fw[i] = fw; 308 } 309 310 return 0; 311 } 312 313 struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu, 314 const struct firmware *fw, u64 *iova) 315 { 316 struct drm_gem_object *bo; 317 void *ptr; 318 319 ptr = msm_gem_kernel_new_locked(gpu->dev, fw->size - 4, 320 MSM_BO_UNCACHED | MSM_BO_GPU_READONLY, gpu->aspace, &bo, iova); 321 322 if (IS_ERR(ptr)) 323 return ERR_CAST(ptr); 324 325 memcpy(ptr, &fw->data[4], fw->size - 4); 326 327 msm_gem_put_vaddr(bo); 328 329 return bo; 330 } 331 332 int adreno_hw_init(struct msm_gpu *gpu) 333 { 334 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 335 int ret, i; 336 337 DBG("%s", gpu->name); 338 339 ret = adreno_load_fw(adreno_gpu); 340 if (ret) 341 return ret; 342 343 for (i = 0; i < gpu->nr_rings; i++) { 344 struct msm_ringbuffer *ring = gpu->rb[i]; 345 346 if (!ring) 347 continue; 348 349 ring->cur = ring->start; 350 ring->next = ring->start; 351 352 /* reset completed fence seqno: */ 353 ring->memptrs->fence = ring->seqno; 354 ring->memptrs->rptr = 0; 355 } 356 357 /* 358 * Setup REG_CP_RB_CNTL. The same value is used across targets (with 359 * the excpetion of A430 that disables the RPTR shadow) - the cacluation 360 * for the ringbuffer size and block size is moved to msm_gpu.h for the 361 * pre-processor to deal with and the A430 variant is ORed in here 362 */ 363 adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_CNTL, 364 MSM_GPU_RB_CNTL_DEFAULT | 365 (adreno_is_a430(adreno_gpu) ? AXXX_CP_RB_CNTL_NO_UPDATE : 0)); 366 367 /* Setup ringbuffer address - use ringbuffer[0] for GPU init */ 368 adreno_gpu_write64(adreno_gpu, REG_ADRENO_CP_RB_BASE, 369 REG_ADRENO_CP_RB_BASE_HI, gpu->rb[0]->iova); 370 371 if (!adreno_is_a430(adreno_gpu)) { 372 adreno_gpu_write64(adreno_gpu, REG_ADRENO_CP_RB_RPTR_ADDR, 373 REG_ADRENO_CP_RB_RPTR_ADDR_HI, 374 rbmemptr(gpu->rb[0], rptr)); 375 } 376 377 return 0; 378 } 379 380 /* Use this helper to read rptr, since a430 doesn't update rptr in memory */ 381 static uint32_t get_rptr(struct adreno_gpu *adreno_gpu, 382 struct msm_ringbuffer *ring) 383 { 384 if (adreno_is_a430(adreno_gpu)) 385 return ring->memptrs->rptr = adreno_gpu_read( 386 adreno_gpu, REG_ADRENO_CP_RB_RPTR); 387 else 388 return ring->memptrs->rptr; 389 } 390 391 struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu) 392 { 393 return gpu->rb[0]; 394 } 395 396 void adreno_recover(struct msm_gpu *gpu) 397 { 398 struct drm_device *dev = gpu->dev; 399 int ret; 400 401 // XXX pm-runtime?? we *need* the device to be off after this 402 // so maybe continuing to call ->pm_suspend/resume() is better? 403 404 gpu->funcs->pm_suspend(gpu); 405 gpu->funcs->pm_resume(gpu); 406 407 ret = msm_gpu_hw_init(gpu); 408 if (ret) { 409 DRM_DEV_ERROR(dev->dev, "gpu hw init failed: %d\n", ret); 410 /* hmm, oh well? */ 411 } 412 } 413 414 void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, 415 struct msm_file_private *ctx) 416 { 417 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 418 struct msm_drm_private *priv = gpu->dev->dev_private; 419 struct msm_ringbuffer *ring = submit->ring; 420 unsigned i; 421 422 for (i = 0; i < submit->nr_cmds; i++) { 423 switch (submit->cmd[i].type) { 424 case MSM_SUBMIT_CMD_IB_TARGET_BUF: 425 /* ignore IB-targets */ 426 break; 427 case MSM_SUBMIT_CMD_CTX_RESTORE_BUF: 428 /* ignore if there has not been a ctx switch: */ 429 if (priv->lastctx == ctx) 430 break; 431 case MSM_SUBMIT_CMD_BUF: 432 OUT_PKT3(ring, adreno_is_a430(adreno_gpu) ? 433 CP_INDIRECT_BUFFER_PFE : CP_INDIRECT_BUFFER_PFD, 2); 434 OUT_RING(ring, lower_32_bits(submit->cmd[i].iova)); 435 OUT_RING(ring, submit->cmd[i].size); 436 OUT_PKT2(ring); 437 break; 438 } 439 } 440 441 OUT_PKT0(ring, REG_AXXX_CP_SCRATCH_REG2, 1); 442 OUT_RING(ring, submit->seqno); 443 444 if (adreno_is_a3xx(adreno_gpu) || adreno_is_a4xx(adreno_gpu)) { 445 /* Flush HLSQ lazy updates to make sure there is nothing 446 * pending for indirect loads after the timestamp has 447 * passed: 448 */ 449 OUT_PKT3(ring, CP_EVENT_WRITE, 1); 450 OUT_RING(ring, HLSQ_FLUSH); 451 } 452 453 /* wait for idle before cache flush/interrupt */ 454 OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1); 455 OUT_RING(ring, 0x00000000); 456 457 if (!adreno_is_a2xx(adreno_gpu)) { 458 /* BIT(31) of CACHE_FLUSH_TS triggers CACHE_FLUSH_TS IRQ from GPU */ 459 OUT_PKT3(ring, CP_EVENT_WRITE, 3); 460 OUT_RING(ring, CACHE_FLUSH_TS | BIT(31)); 461 OUT_RING(ring, rbmemptr(ring, fence)); 462 OUT_RING(ring, submit->seqno); 463 } else { 464 /* BIT(31) means something else on a2xx */ 465 OUT_PKT3(ring, CP_EVENT_WRITE, 3); 466 OUT_RING(ring, CACHE_FLUSH_TS); 467 OUT_RING(ring, rbmemptr(ring, fence)); 468 OUT_RING(ring, submit->seqno); 469 OUT_PKT3(ring, CP_INTERRUPT, 1); 470 OUT_RING(ring, 0x80000000); 471 } 472 473 #if 0 474 if (adreno_is_a3xx(adreno_gpu)) { 475 /* Dummy set-constant to trigger context rollover */ 476 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 477 OUT_RING(ring, CP_REG(REG_A3XX_HLSQ_CL_KERNEL_GROUP_X_REG)); 478 OUT_RING(ring, 0x00000000); 479 } 480 #endif 481 482 gpu->funcs->flush(gpu, ring); 483 } 484 485 void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 486 { 487 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 488 uint32_t wptr; 489 490 /* Copy the shadow to the actual register */ 491 ring->cur = ring->next; 492 493 /* 494 * Mask wptr value that we calculate to fit in the HW range. This is 495 * to account for the possibility that the last command fit exactly into 496 * the ringbuffer and rb->next hasn't wrapped to zero yet 497 */ 498 wptr = get_wptr(ring); 499 500 /* ensure writes to ringbuffer have hit system memory: */ 501 mb(); 502 503 adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_WPTR, wptr); 504 } 505 506 bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 507 { 508 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 509 uint32_t wptr = get_wptr(ring); 510 511 /* wait for CP to drain ringbuffer: */ 512 if (!spin_until(get_rptr(adreno_gpu, ring) == wptr)) 513 return true; 514 515 /* TODO maybe we need to reset GPU here to recover from hang? */ 516 DRM_ERROR("%s: timeout waiting to drain ringbuffer %d rptr/wptr = %X/%X\n", 517 gpu->name, ring->id, get_rptr(adreno_gpu, ring), wptr); 518 519 return false; 520 } 521 522 int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state) 523 { 524 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 525 int i, count = 0; 526 527 kref_init(&state->ref); 528 529 ktime_get_real_ts64(&state->time); 530 531 for (i = 0; i < gpu->nr_rings; i++) { 532 int size = 0, j; 533 534 state->ring[i].fence = gpu->rb[i]->memptrs->fence; 535 state->ring[i].iova = gpu->rb[i]->iova; 536 state->ring[i].seqno = gpu->rb[i]->seqno; 537 state->ring[i].rptr = get_rptr(adreno_gpu, gpu->rb[i]); 538 state->ring[i].wptr = get_wptr(gpu->rb[i]); 539 540 /* Copy at least 'wptr' dwords of the data */ 541 size = state->ring[i].wptr; 542 543 /* After wptr find the last non zero dword to save space */ 544 for (j = state->ring[i].wptr; j < MSM_GPU_RINGBUFFER_SZ >> 2; j++) 545 if (gpu->rb[i]->start[j]) 546 size = j + 1; 547 548 if (size) { 549 state->ring[i].data = kvmalloc(size << 2, GFP_KERNEL); 550 if (state->ring[i].data) { 551 memcpy(state->ring[i].data, gpu->rb[i]->start, size << 2); 552 state->ring[i].data_size = size << 2; 553 } 554 } 555 } 556 557 /* Some targets prefer to collect their own registers */ 558 if (!adreno_gpu->registers) 559 return 0; 560 561 /* Count the number of registers */ 562 for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) 563 count += adreno_gpu->registers[i + 1] - 564 adreno_gpu->registers[i] + 1; 565 566 state->registers = kcalloc(count * 2, sizeof(u32), GFP_KERNEL); 567 if (state->registers) { 568 int pos = 0; 569 570 for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) { 571 u32 start = adreno_gpu->registers[i]; 572 u32 end = adreno_gpu->registers[i + 1]; 573 u32 addr; 574 575 for (addr = start; addr <= end; addr++) { 576 state->registers[pos++] = addr; 577 state->registers[pos++] = gpu_read(gpu, addr); 578 } 579 } 580 581 state->nr_registers = count; 582 } 583 584 return 0; 585 } 586 587 void adreno_gpu_state_destroy(struct msm_gpu_state *state) 588 { 589 int i; 590 591 for (i = 0; i < ARRAY_SIZE(state->ring); i++) 592 kvfree(state->ring[i].data); 593 594 for (i = 0; state->bos && i < state->nr_bos; i++) 595 kvfree(state->bos[i].data); 596 597 kfree(state->bos); 598 kfree(state->comm); 599 kfree(state->cmd); 600 kfree(state->registers); 601 } 602 603 static void adreno_gpu_state_kref_destroy(struct kref *kref) 604 { 605 struct msm_gpu_state *state = container_of(kref, 606 struct msm_gpu_state, ref); 607 608 adreno_gpu_state_destroy(state); 609 kfree(state); 610 } 611 612 int adreno_gpu_state_put(struct msm_gpu_state *state) 613 { 614 if (IS_ERR_OR_NULL(state)) 615 return 1; 616 617 return kref_put(&state->ref, adreno_gpu_state_kref_destroy); 618 } 619 620 #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP) 621 622 static char *adreno_gpu_ascii85_encode(u32 *src, size_t len) 623 { 624 void *buf; 625 size_t buf_itr = 0, buffer_size; 626 char out[ASCII85_BUFSZ]; 627 long l; 628 int i; 629 630 if (!src || !len) 631 return NULL; 632 633 l = ascii85_encode_len(len); 634 635 /* 636 * Ascii85 outputs either a 5 byte string or a 1 byte string. So we 637 * account for the worst case of 5 bytes per dword plus the 1 for '\0' 638 */ 639 buffer_size = (l * 5) + 1; 640 641 buf = kvmalloc(buffer_size, GFP_KERNEL); 642 if (!buf) 643 return NULL; 644 645 for (i = 0; i < l; i++) 646 buf_itr += snprintf(buf + buf_itr, buffer_size - buf_itr, "%s", 647 ascii85_encode(src[i], out)); 648 649 return buf; 650 } 651 652 /* len is expected to be in bytes */ 653 static void adreno_show_object(struct drm_printer *p, void **ptr, int len, 654 bool *encoded) 655 { 656 if (!*ptr || !len) 657 return; 658 659 if (!*encoded) { 660 long datalen, i; 661 u32 *buf = *ptr; 662 663 /* 664 * Only dump the non-zero part of the buffer - rarely will 665 * any data completely fill the entire allocated size of 666 * the buffer. 667 */ 668 for (datalen = 0, i = 0; i < len >> 2; i++) 669 if (buf[i]) 670 datalen = ((i + 1) << 2); 671 672 /* 673 * If we reach here, then the originally captured binary buffer 674 * will be replaced with the ascii85 encoded string 675 */ 676 *ptr = adreno_gpu_ascii85_encode(buf, datalen); 677 678 kvfree(buf); 679 680 *encoded = true; 681 } 682 683 if (!*ptr) 684 return; 685 686 drm_puts(p, " data: !!ascii85 |\n"); 687 drm_puts(p, " "); 688 689 drm_puts(p, *ptr); 690 691 drm_puts(p, "\n"); 692 } 693 694 void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state, 695 struct drm_printer *p) 696 { 697 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 698 int i; 699 700 if (IS_ERR_OR_NULL(state)) 701 return; 702 703 drm_printf(p, "revision: %d (%d.%d.%d.%d)\n", 704 adreno_gpu->info->revn, adreno_gpu->rev.core, 705 adreno_gpu->rev.major, adreno_gpu->rev.minor, 706 adreno_gpu->rev.patchid); 707 708 drm_printf(p, "rbbm-status: 0x%08x\n", state->rbbm_status); 709 710 drm_puts(p, "ringbuffer:\n"); 711 712 for (i = 0; i < gpu->nr_rings; i++) { 713 drm_printf(p, " - id: %d\n", i); 714 drm_printf(p, " iova: 0x%016llx\n", state->ring[i].iova); 715 drm_printf(p, " last-fence: %d\n", state->ring[i].seqno); 716 drm_printf(p, " retired-fence: %d\n", state->ring[i].fence); 717 drm_printf(p, " rptr: %d\n", state->ring[i].rptr); 718 drm_printf(p, " wptr: %d\n", state->ring[i].wptr); 719 drm_printf(p, " size: %d\n", MSM_GPU_RINGBUFFER_SZ); 720 721 adreno_show_object(p, &state->ring[i].data, 722 state->ring[i].data_size, &state->ring[i].encoded); 723 } 724 725 if (state->bos) { 726 drm_puts(p, "bos:\n"); 727 728 for (i = 0; i < state->nr_bos; i++) { 729 drm_printf(p, " - iova: 0x%016llx\n", 730 state->bos[i].iova); 731 drm_printf(p, " size: %zd\n", state->bos[i].size); 732 733 adreno_show_object(p, &state->bos[i].data, 734 state->bos[i].size, &state->bos[i].encoded); 735 } 736 } 737 738 if (state->nr_registers) { 739 drm_puts(p, "registers:\n"); 740 741 for (i = 0; i < state->nr_registers; i++) { 742 drm_printf(p, " - { offset: 0x%04x, value: 0x%08x }\n", 743 state->registers[i * 2] << 2, 744 state->registers[(i * 2) + 1]); 745 } 746 } 747 } 748 #endif 749 750 /* Dump common gpu status and scratch registers on any hang, to make 751 * the hangcheck logs more useful. The scratch registers seem always 752 * safe to read when GPU has hung (unlike some other regs, depending 753 * on how the GPU hung), and they are useful to match up to cmdstream 754 * dumps when debugging hangs: 755 */ 756 void adreno_dump_info(struct msm_gpu *gpu) 757 { 758 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 759 int i; 760 761 printk("revision: %d (%d.%d.%d.%d)\n", 762 adreno_gpu->info->revn, adreno_gpu->rev.core, 763 adreno_gpu->rev.major, adreno_gpu->rev.minor, 764 adreno_gpu->rev.patchid); 765 766 for (i = 0; i < gpu->nr_rings; i++) { 767 struct msm_ringbuffer *ring = gpu->rb[i]; 768 769 printk("rb %d: fence: %d/%d\n", i, 770 ring->memptrs->fence, 771 ring->seqno); 772 773 printk("rptr: %d\n", get_rptr(adreno_gpu, ring)); 774 printk("rb wptr: %d\n", get_wptr(ring)); 775 } 776 } 777 778 /* would be nice to not have to duplicate the _show() stuff with printk(): */ 779 void adreno_dump(struct msm_gpu *gpu) 780 { 781 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 782 int i; 783 784 if (!adreno_gpu->registers) 785 return; 786 787 /* dump these out in a form that can be parsed by demsm: */ 788 printk("IO:region %s 00000000 00020000\n", gpu->name); 789 for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) { 790 uint32_t start = adreno_gpu->registers[i]; 791 uint32_t end = adreno_gpu->registers[i+1]; 792 uint32_t addr; 793 794 for (addr = start; addr <= end; addr++) { 795 uint32_t val = gpu_read(gpu, addr); 796 printk("IO:R %08x %08x\n", addr<<2, val); 797 } 798 } 799 } 800 801 static uint32_t ring_freewords(struct msm_ringbuffer *ring) 802 { 803 struct adreno_gpu *adreno_gpu = to_adreno_gpu(ring->gpu); 804 uint32_t size = MSM_GPU_RINGBUFFER_SZ >> 2; 805 /* Use ring->next to calculate free size */ 806 uint32_t wptr = ring->next - ring->start; 807 uint32_t rptr = get_rptr(adreno_gpu, ring); 808 return (rptr + (size - 1) - wptr) % size; 809 } 810 811 void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords) 812 { 813 if (spin_until(ring_freewords(ring) >= ndwords)) 814 DRM_DEV_ERROR(ring->gpu->dev->dev, 815 "timeout waiting for space in ringbuffer %d\n", 816 ring->id); 817 } 818 819 /* Get legacy powerlevels from qcom,gpu-pwrlevels and populate the opp table */ 820 static int adreno_get_legacy_pwrlevels(struct device *dev) 821 { 822 struct device_node *child, *node; 823 int ret; 824 825 node = of_get_compatible_child(dev->of_node, "qcom,gpu-pwrlevels"); 826 if (!node) { 827 DRM_DEV_ERROR(dev, "Could not find the GPU powerlevels\n"); 828 return -ENXIO; 829 } 830 831 for_each_child_of_node(node, child) { 832 unsigned int val; 833 834 ret = of_property_read_u32(child, "qcom,gpu-freq", &val); 835 if (ret) 836 continue; 837 838 /* 839 * Skip the intentionally bogus clock value found at the bottom 840 * of most legacy frequency tables 841 */ 842 if (val != 27000000) 843 dev_pm_opp_add(dev, val, 0); 844 } 845 846 of_node_put(node); 847 848 return 0; 849 } 850 851 static int adreno_get_pwrlevels(struct device *dev, 852 struct msm_gpu *gpu) 853 { 854 unsigned long freq = ULONG_MAX; 855 struct dev_pm_opp *opp; 856 int ret; 857 858 gpu->fast_rate = 0; 859 860 /* You down with OPP? */ 861 if (!of_find_property(dev->of_node, "operating-points-v2", NULL)) 862 ret = adreno_get_legacy_pwrlevels(dev); 863 else { 864 ret = dev_pm_opp_of_add_table(dev); 865 if (ret) 866 DRM_DEV_ERROR(dev, "Unable to set the OPP table\n"); 867 } 868 869 if (!ret) { 870 /* Find the fastest defined rate */ 871 opp = dev_pm_opp_find_freq_floor(dev, &freq); 872 if (!IS_ERR(opp)) { 873 gpu->fast_rate = freq; 874 dev_pm_opp_put(opp); 875 } 876 } 877 878 if (!gpu->fast_rate) { 879 dev_warn(dev, 880 "Could not find a clock rate. Using a reasonable default\n"); 881 /* Pick a suitably safe clock speed for any target */ 882 gpu->fast_rate = 200000000; 883 } 884 885 DBG("fast_rate=%u, slow_rate=27000000", gpu->fast_rate); 886 887 /* Check for an interconnect path for the bus */ 888 gpu->icc_path = of_icc_get(dev, NULL); 889 if (IS_ERR(gpu->icc_path)) 890 gpu->icc_path = NULL; 891 892 return 0; 893 } 894 895 int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, 896 struct adreno_gpu *adreno_gpu, 897 const struct adreno_gpu_funcs *funcs, int nr_rings) 898 { 899 struct adreno_platform_config *config = pdev->dev.platform_data; 900 struct msm_gpu_config adreno_gpu_config = { 0 }; 901 struct msm_gpu *gpu = &adreno_gpu->base; 902 903 adreno_gpu->funcs = funcs; 904 adreno_gpu->info = adreno_info(config->rev); 905 adreno_gpu->gmem = adreno_gpu->info->gmem; 906 adreno_gpu->revn = adreno_gpu->info->revn; 907 adreno_gpu->rev = config->rev; 908 909 adreno_gpu_config.ioname = "kgsl_3d0_reg_memory"; 910 911 adreno_gpu_config.va_start = SZ_16M; 912 adreno_gpu_config.va_end = 0xffffffff; 913 /* maximum range of a2xx mmu */ 914 if (adreno_is_a2xx(adreno_gpu)) 915 adreno_gpu_config.va_end = SZ_16M + 0xfff * SZ_64K; 916 917 adreno_gpu_config.nr_rings = nr_rings; 918 919 adreno_get_pwrlevels(&pdev->dev, gpu); 920 921 pm_runtime_set_autosuspend_delay(&pdev->dev, 922 adreno_gpu->info->inactive_period); 923 pm_runtime_use_autosuspend(&pdev->dev); 924 pm_runtime_enable(&pdev->dev); 925 926 return msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base, 927 adreno_gpu->info->name, &adreno_gpu_config); 928 } 929 930 void adreno_gpu_cleanup(struct adreno_gpu *adreno_gpu) 931 { 932 struct msm_gpu *gpu = &adreno_gpu->base; 933 unsigned int i; 934 935 for (i = 0; i < ARRAY_SIZE(adreno_gpu->info->fw); i++) 936 release_firmware(adreno_gpu->fw[i]); 937 938 icc_put(gpu->icc_path); 939 940 msm_gpu_cleanup(&adreno_gpu->base); 941 } 942