1 /* 2 * Copyright (C) 2013 Red Hat 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License version 2 as published by 9 * the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include <linux/ascii85.h> 21 #include <linux/kernel.h> 22 #include <linux/pm_opp.h> 23 #include <linux/slab.h> 24 #include "adreno_gpu.h" 25 #include "msm_gem.h" 26 #include "msm_mmu.h" 27 28 int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value) 29 { 30 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 31 32 switch (param) { 33 case MSM_PARAM_GPU_ID: 34 *value = adreno_gpu->info->revn; 35 return 0; 36 case MSM_PARAM_GMEM_SIZE: 37 *value = adreno_gpu->gmem; 38 return 0; 39 case MSM_PARAM_GMEM_BASE: 40 *value = 0x100000; 41 return 0; 42 case MSM_PARAM_CHIP_ID: 43 *value = adreno_gpu->rev.patchid | 44 (adreno_gpu->rev.minor << 8) | 45 (adreno_gpu->rev.major << 16) | 46 (adreno_gpu->rev.core << 24); 47 return 0; 48 case MSM_PARAM_MAX_FREQ: 49 *value = adreno_gpu->base.fast_rate; 50 return 0; 51 case MSM_PARAM_TIMESTAMP: 52 if (adreno_gpu->funcs->get_timestamp) { 53 int ret; 54 55 pm_runtime_get_sync(&gpu->pdev->dev); 56 ret = adreno_gpu->funcs->get_timestamp(gpu, value); 57 pm_runtime_put_autosuspend(&gpu->pdev->dev); 58 59 return ret; 60 } 61 return -EINVAL; 62 case MSM_PARAM_NR_RINGS: 63 *value = gpu->nr_rings; 64 return 0; 65 default: 66 DBG("%s: invalid param: %u", gpu->name, param); 67 return -EINVAL; 68 } 69 } 70 71 const struct firmware * 72 adreno_request_fw(struct adreno_gpu *adreno_gpu, const char *fwname) 73 { 74 struct drm_device *drm = adreno_gpu->base.dev; 75 const struct firmware *fw = NULL; 76 char *newname; 77 int ret; 78 79 newname = kasprintf(GFP_KERNEL, "qcom/%s", fwname); 80 if (!newname) 81 return ERR_PTR(-ENOMEM); 82 83 /* 84 * Try first to load from qcom/$fwfile using a direct load (to avoid 85 * a potential timeout waiting for usermode helper) 86 */ 87 if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) || 88 (adreno_gpu->fwloc == FW_LOCATION_NEW)) { 89 90 ret = request_firmware_direct(&fw, newname, drm->dev); 91 if (!ret) { 92 DRM_DEV_INFO(drm->dev, "loaded %s from new location\n", 93 newname); 94 adreno_gpu->fwloc = FW_LOCATION_NEW; 95 goto out; 96 } else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) { 97 DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n", 98 newname, ret); 99 fw = ERR_PTR(ret); 100 goto out; 101 } 102 } 103 104 /* 105 * Then try the legacy location without qcom/ prefix 106 */ 107 if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) || 108 (adreno_gpu->fwloc == FW_LOCATION_LEGACY)) { 109 110 ret = request_firmware_direct(&fw, fwname, drm->dev); 111 if (!ret) { 112 DRM_DEV_INFO(drm->dev, "loaded %s from legacy location\n", 113 newname); 114 adreno_gpu->fwloc = FW_LOCATION_LEGACY; 115 goto out; 116 } else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) { 117 DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n", 118 fwname, ret); 119 fw = ERR_PTR(ret); 120 goto out; 121 } 122 } 123 124 /* 125 * Finally fall back to request_firmware() for cases where the 126 * usermode helper is needed (I think mainly android) 127 */ 128 if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) || 129 (adreno_gpu->fwloc == FW_LOCATION_HELPER)) { 130 131 ret = request_firmware(&fw, newname, drm->dev); 132 if (!ret) { 133 DRM_DEV_INFO(drm->dev, "loaded %s with helper\n", 134 newname); 135 adreno_gpu->fwloc = FW_LOCATION_HELPER; 136 goto out; 137 } else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) { 138 DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n", 139 newname, ret); 140 fw = ERR_PTR(ret); 141 goto out; 142 } 143 } 144 145 DRM_DEV_ERROR(drm->dev, "failed to load %s\n", fwname); 146 fw = ERR_PTR(-ENOENT); 147 out: 148 kfree(newname); 149 return fw; 150 } 151 152 int adreno_load_fw(struct adreno_gpu *adreno_gpu) 153 { 154 int i; 155 156 for (i = 0; i < ARRAY_SIZE(adreno_gpu->info->fw); i++) { 157 const struct firmware *fw; 158 159 if (!adreno_gpu->info->fw[i]) 160 continue; 161 162 /* Skip if the firmware has already been loaded */ 163 if (adreno_gpu->fw[i]) 164 continue; 165 166 fw = adreno_request_fw(adreno_gpu, adreno_gpu->info->fw[i]); 167 if (IS_ERR(fw)) 168 return PTR_ERR(fw); 169 170 adreno_gpu->fw[i] = fw; 171 } 172 173 return 0; 174 } 175 176 struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu, 177 const struct firmware *fw, u64 *iova) 178 { 179 struct drm_gem_object *bo; 180 void *ptr; 181 182 ptr = msm_gem_kernel_new_locked(gpu->dev, fw->size - 4, 183 MSM_BO_UNCACHED | MSM_BO_GPU_READONLY, gpu->aspace, &bo, iova); 184 185 if (IS_ERR(ptr)) 186 return ERR_CAST(ptr); 187 188 memcpy(ptr, &fw->data[4], fw->size - 4); 189 190 msm_gem_put_vaddr(bo); 191 192 return bo; 193 } 194 195 int adreno_hw_init(struct msm_gpu *gpu) 196 { 197 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 198 int ret, i; 199 200 DBG("%s", gpu->name); 201 202 ret = adreno_load_fw(adreno_gpu); 203 if (ret) 204 return ret; 205 206 for (i = 0; i < gpu->nr_rings; i++) { 207 struct msm_ringbuffer *ring = gpu->rb[i]; 208 209 if (!ring) 210 continue; 211 212 ring->cur = ring->start; 213 ring->next = ring->start; 214 215 /* reset completed fence seqno: */ 216 ring->memptrs->fence = ring->seqno; 217 ring->memptrs->rptr = 0; 218 } 219 220 /* 221 * Setup REG_CP_RB_CNTL. The same value is used across targets (with 222 * the excpetion of A430 that disables the RPTR shadow) - the cacluation 223 * for the ringbuffer size and block size is moved to msm_gpu.h for the 224 * pre-processor to deal with and the A430 variant is ORed in here 225 */ 226 adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_CNTL, 227 MSM_GPU_RB_CNTL_DEFAULT | 228 (adreno_is_a430(adreno_gpu) ? AXXX_CP_RB_CNTL_NO_UPDATE : 0)); 229 230 /* Setup ringbuffer address - use ringbuffer[0] for GPU init */ 231 adreno_gpu_write64(adreno_gpu, REG_ADRENO_CP_RB_BASE, 232 REG_ADRENO_CP_RB_BASE_HI, gpu->rb[0]->iova); 233 234 if (!adreno_is_a430(adreno_gpu)) { 235 adreno_gpu_write64(adreno_gpu, REG_ADRENO_CP_RB_RPTR_ADDR, 236 REG_ADRENO_CP_RB_RPTR_ADDR_HI, 237 rbmemptr(gpu->rb[0], rptr)); 238 } 239 240 return 0; 241 } 242 243 /* Use this helper to read rptr, since a430 doesn't update rptr in memory */ 244 static uint32_t get_rptr(struct adreno_gpu *adreno_gpu, 245 struct msm_ringbuffer *ring) 246 { 247 if (adreno_is_a430(adreno_gpu)) 248 return ring->memptrs->rptr = adreno_gpu_read( 249 adreno_gpu, REG_ADRENO_CP_RB_RPTR); 250 else 251 return ring->memptrs->rptr; 252 } 253 254 struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu) 255 { 256 return gpu->rb[0]; 257 } 258 259 void adreno_recover(struct msm_gpu *gpu) 260 { 261 struct drm_device *dev = gpu->dev; 262 int ret; 263 264 // XXX pm-runtime?? we *need* the device to be off after this 265 // so maybe continuing to call ->pm_suspend/resume() is better? 266 267 gpu->funcs->pm_suspend(gpu); 268 gpu->funcs->pm_resume(gpu); 269 270 ret = msm_gpu_hw_init(gpu); 271 if (ret) { 272 DRM_DEV_ERROR(dev->dev, "gpu hw init failed: %d\n", ret); 273 /* hmm, oh well? */ 274 } 275 } 276 277 void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, 278 struct msm_file_private *ctx) 279 { 280 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 281 struct msm_drm_private *priv = gpu->dev->dev_private; 282 struct msm_ringbuffer *ring = submit->ring; 283 unsigned i; 284 285 for (i = 0; i < submit->nr_cmds; i++) { 286 switch (submit->cmd[i].type) { 287 case MSM_SUBMIT_CMD_IB_TARGET_BUF: 288 /* ignore IB-targets */ 289 break; 290 case MSM_SUBMIT_CMD_CTX_RESTORE_BUF: 291 /* ignore if there has not been a ctx switch: */ 292 if (priv->lastctx == ctx) 293 break; 294 case MSM_SUBMIT_CMD_BUF: 295 OUT_PKT3(ring, adreno_is_a430(adreno_gpu) ? 296 CP_INDIRECT_BUFFER_PFE : CP_INDIRECT_BUFFER_PFD, 2); 297 OUT_RING(ring, lower_32_bits(submit->cmd[i].iova)); 298 OUT_RING(ring, submit->cmd[i].size); 299 OUT_PKT2(ring); 300 break; 301 } 302 } 303 304 OUT_PKT0(ring, REG_AXXX_CP_SCRATCH_REG2, 1); 305 OUT_RING(ring, submit->seqno); 306 307 if (adreno_is_a3xx(adreno_gpu) || adreno_is_a4xx(adreno_gpu)) { 308 /* Flush HLSQ lazy updates to make sure there is nothing 309 * pending for indirect loads after the timestamp has 310 * passed: 311 */ 312 OUT_PKT3(ring, CP_EVENT_WRITE, 1); 313 OUT_RING(ring, HLSQ_FLUSH); 314 } 315 316 /* wait for idle before cache flush/interrupt */ 317 OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1); 318 OUT_RING(ring, 0x00000000); 319 320 if (!adreno_is_a2xx(adreno_gpu)) { 321 /* BIT(31) of CACHE_FLUSH_TS triggers CACHE_FLUSH_TS IRQ from GPU */ 322 OUT_PKT3(ring, CP_EVENT_WRITE, 3); 323 OUT_RING(ring, CACHE_FLUSH_TS | BIT(31)); 324 OUT_RING(ring, rbmemptr(ring, fence)); 325 OUT_RING(ring, submit->seqno); 326 } else { 327 /* BIT(31) means something else on a2xx */ 328 OUT_PKT3(ring, CP_EVENT_WRITE, 3); 329 OUT_RING(ring, CACHE_FLUSH_TS); 330 OUT_RING(ring, rbmemptr(ring, fence)); 331 OUT_RING(ring, submit->seqno); 332 OUT_PKT3(ring, CP_INTERRUPT, 1); 333 OUT_RING(ring, 0x80000000); 334 } 335 336 #if 0 337 if (adreno_is_a3xx(adreno_gpu)) { 338 /* Dummy set-constant to trigger context rollover */ 339 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 340 OUT_RING(ring, CP_REG(REG_A3XX_HLSQ_CL_KERNEL_GROUP_X_REG)); 341 OUT_RING(ring, 0x00000000); 342 } 343 #endif 344 345 gpu->funcs->flush(gpu, ring); 346 } 347 348 void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 349 { 350 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 351 uint32_t wptr; 352 353 /* Copy the shadow to the actual register */ 354 ring->cur = ring->next; 355 356 /* 357 * Mask wptr value that we calculate to fit in the HW range. This is 358 * to account for the possibility that the last command fit exactly into 359 * the ringbuffer and rb->next hasn't wrapped to zero yet 360 */ 361 wptr = get_wptr(ring); 362 363 /* ensure writes to ringbuffer have hit system memory: */ 364 mb(); 365 366 adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_WPTR, wptr); 367 } 368 369 bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 370 { 371 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 372 uint32_t wptr = get_wptr(ring); 373 374 /* wait for CP to drain ringbuffer: */ 375 if (!spin_until(get_rptr(adreno_gpu, ring) == wptr)) 376 return true; 377 378 /* TODO maybe we need to reset GPU here to recover from hang? */ 379 DRM_ERROR("%s: timeout waiting to drain ringbuffer %d rptr/wptr = %X/%X\n", 380 gpu->name, ring->id, get_rptr(adreno_gpu, ring), wptr); 381 382 return false; 383 } 384 385 int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state) 386 { 387 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 388 int i, count = 0; 389 390 kref_init(&state->ref); 391 392 ktime_get_real_ts64(&state->time); 393 394 for (i = 0; i < gpu->nr_rings; i++) { 395 int size = 0, j; 396 397 state->ring[i].fence = gpu->rb[i]->memptrs->fence; 398 state->ring[i].iova = gpu->rb[i]->iova; 399 state->ring[i].seqno = gpu->rb[i]->seqno; 400 state->ring[i].rptr = get_rptr(adreno_gpu, gpu->rb[i]); 401 state->ring[i].wptr = get_wptr(gpu->rb[i]); 402 403 /* Copy at least 'wptr' dwords of the data */ 404 size = state->ring[i].wptr; 405 406 /* After wptr find the last non zero dword to save space */ 407 for (j = state->ring[i].wptr; j < MSM_GPU_RINGBUFFER_SZ >> 2; j++) 408 if (gpu->rb[i]->start[j]) 409 size = j + 1; 410 411 if (size) { 412 state->ring[i].data = kvmalloc(size << 2, GFP_KERNEL); 413 if (state->ring[i].data) { 414 memcpy(state->ring[i].data, gpu->rb[i]->start, size << 2); 415 state->ring[i].data_size = size << 2; 416 } 417 } 418 } 419 420 /* Some targets prefer to collect their own registers */ 421 if (!adreno_gpu->registers) 422 return 0; 423 424 /* Count the number of registers */ 425 for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) 426 count += adreno_gpu->registers[i + 1] - 427 adreno_gpu->registers[i] + 1; 428 429 state->registers = kcalloc(count * 2, sizeof(u32), GFP_KERNEL); 430 if (state->registers) { 431 int pos = 0; 432 433 for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) { 434 u32 start = adreno_gpu->registers[i]; 435 u32 end = adreno_gpu->registers[i + 1]; 436 u32 addr; 437 438 for (addr = start; addr <= end; addr++) { 439 state->registers[pos++] = addr; 440 state->registers[pos++] = gpu_read(gpu, addr); 441 } 442 } 443 444 state->nr_registers = count; 445 } 446 447 return 0; 448 } 449 450 void adreno_gpu_state_destroy(struct msm_gpu_state *state) 451 { 452 int i; 453 454 for (i = 0; i < ARRAY_SIZE(state->ring); i++) 455 kvfree(state->ring[i].data); 456 457 for (i = 0; state->bos && i < state->nr_bos; i++) 458 kvfree(state->bos[i].data); 459 460 kfree(state->bos); 461 kfree(state->comm); 462 kfree(state->cmd); 463 kfree(state->registers); 464 } 465 466 static void adreno_gpu_state_kref_destroy(struct kref *kref) 467 { 468 struct msm_gpu_state *state = container_of(kref, 469 struct msm_gpu_state, ref); 470 471 adreno_gpu_state_destroy(state); 472 kfree(state); 473 } 474 475 int adreno_gpu_state_put(struct msm_gpu_state *state) 476 { 477 if (IS_ERR_OR_NULL(state)) 478 return 1; 479 480 return kref_put(&state->ref, adreno_gpu_state_kref_destroy); 481 } 482 483 #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP) 484 485 static char *adreno_gpu_ascii85_encode(u32 *src, size_t len) 486 { 487 void *buf; 488 size_t buf_itr = 0, buffer_size; 489 char out[ASCII85_BUFSZ]; 490 long l; 491 int i; 492 493 if (!src || !len) 494 return NULL; 495 496 l = ascii85_encode_len(len); 497 498 /* 499 * Ascii85 outputs either a 5 byte string or a 1 byte string. So we 500 * account for the worst case of 5 bytes per dword plus the 1 for '\0' 501 */ 502 buffer_size = (l * 5) + 1; 503 504 buf = kvmalloc(buffer_size, GFP_KERNEL); 505 if (!buf) 506 return NULL; 507 508 for (i = 0; i < l; i++) 509 buf_itr += snprintf(buf + buf_itr, buffer_size - buf_itr, "%s", 510 ascii85_encode(src[i], out)); 511 512 return buf; 513 } 514 515 /* len is expected to be in bytes */ 516 static void adreno_show_object(struct drm_printer *p, void **ptr, int len, 517 bool *encoded) 518 { 519 if (!*ptr || !len) 520 return; 521 522 if (!*encoded) { 523 long datalen, i; 524 u32 *buf = *ptr; 525 526 /* 527 * Only dump the non-zero part of the buffer - rarely will 528 * any data completely fill the entire allocated size of 529 * the buffer. 530 */ 531 for (datalen = 0, i = 0; i < len >> 2; i++) 532 if (buf[i]) 533 datalen = ((i + 1) << 2); 534 535 /* 536 * If we reach here, then the originally captured binary buffer 537 * will be replaced with the ascii85 encoded string 538 */ 539 *ptr = adreno_gpu_ascii85_encode(buf, datalen); 540 541 kvfree(buf); 542 543 *encoded = true; 544 } 545 546 if (!*ptr) 547 return; 548 549 drm_puts(p, " data: !!ascii85 |\n"); 550 drm_puts(p, " "); 551 552 drm_puts(p, *ptr); 553 554 drm_puts(p, "\n"); 555 } 556 557 void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state, 558 struct drm_printer *p) 559 { 560 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 561 int i; 562 563 if (IS_ERR_OR_NULL(state)) 564 return; 565 566 drm_printf(p, "revision: %d (%d.%d.%d.%d)\n", 567 adreno_gpu->info->revn, adreno_gpu->rev.core, 568 adreno_gpu->rev.major, adreno_gpu->rev.minor, 569 adreno_gpu->rev.patchid); 570 571 drm_printf(p, "rbbm-status: 0x%08x\n", state->rbbm_status); 572 573 drm_puts(p, "ringbuffer:\n"); 574 575 for (i = 0; i < gpu->nr_rings; i++) { 576 drm_printf(p, " - id: %d\n", i); 577 drm_printf(p, " iova: 0x%016llx\n", state->ring[i].iova); 578 drm_printf(p, " last-fence: %d\n", state->ring[i].seqno); 579 drm_printf(p, " retired-fence: %d\n", state->ring[i].fence); 580 drm_printf(p, " rptr: %d\n", state->ring[i].rptr); 581 drm_printf(p, " wptr: %d\n", state->ring[i].wptr); 582 drm_printf(p, " size: %d\n", MSM_GPU_RINGBUFFER_SZ); 583 584 adreno_show_object(p, &state->ring[i].data, 585 state->ring[i].data_size, &state->ring[i].encoded); 586 } 587 588 if (state->bos) { 589 drm_puts(p, "bos:\n"); 590 591 for (i = 0; i < state->nr_bos; i++) { 592 drm_printf(p, " - iova: 0x%016llx\n", 593 state->bos[i].iova); 594 drm_printf(p, " size: %zd\n", state->bos[i].size); 595 596 adreno_show_object(p, &state->bos[i].data, 597 state->bos[i].size, &state->bos[i].encoded); 598 } 599 } 600 601 if (state->nr_registers) { 602 drm_puts(p, "registers:\n"); 603 604 for (i = 0; i < state->nr_registers; i++) { 605 drm_printf(p, " - { offset: 0x%04x, value: 0x%08x }\n", 606 state->registers[i * 2] << 2, 607 state->registers[(i * 2) + 1]); 608 } 609 } 610 } 611 #endif 612 613 /* Dump common gpu status and scratch registers on any hang, to make 614 * the hangcheck logs more useful. The scratch registers seem always 615 * safe to read when GPU has hung (unlike some other regs, depending 616 * on how the GPU hung), and they are useful to match up to cmdstream 617 * dumps when debugging hangs: 618 */ 619 void adreno_dump_info(struct msm_gpu *gpu) 620 { 621 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 622 int i; 623 624 printk("revision: %d (%d.%d.%d.%d)\n", 625 adreno_gpu->info->revn, adreno_gpu->rev.core, 626 adreno_gpu->rev.major, adreno_gpu->rev.minor, 627 adreno_gpu->rev.patchid); 628 629 for (i = 0; i < gpu->nr_rings; i++) { 630 struct msm_ringbuffer *ring = gpu->rb[i]; 631 632 printk("rb %d: fence: %d/%d\n", i, 633 ring->memptrs->fence, 634 ring->seqno); 635 636 printk("rptr: %d\n", get_rptr(adreno_gpu, ring)); 637 printk("rb wptr: %d\n", get_wptr(ring)); 638 } 639 } 640 641 /* would be nice to not have to duplicate the _show() stuff with printk(): */ 642 void adreno_dump(struct msm_gpu *gpu) 643 { 644 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 645 int i; 646 647 if (!adreno_gpu->registers) 648 return; 649 650 /* dump these out in a form that can be parsed by demsm: */ 651 printk("IO:region %s 00000000 00020000\n", gpu->name); 652 for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) { 653 uint32_t start = adreno_gpu->registers[i]; 654 uint32_t end = adreno_gpu->registers[i+1]; 655 uint32_t addr; 656 657 for (addr = start; addr <= end; addr++) { 658 uint32_t val = gpu_read(gpu, addr); 659 printk("IO:R %08x %08x\n", addr<<2, val); 660 } 661 } 662 } 663 664 static uint32_t ring_freewords(struct msm_ringbuffer *ring) 665 { 666 struct adreno_gpu *adreno_gpu = to_adreno_gpu(ring->gpu); 667 uint32_t size = MSM_GPU_RINGBUFFER_SZ >> 2; 668 /* Use ring->next to calculate free size */ 669 uint32_t wptr = ring->next - ring->start; 670 uint32_t rptr = get_rptr(adreno_gpu, ring); 671 return (rptr + (size - 1) - wptr) % size; 672 } 673 674 void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords) 675 { 676 if (spin_until(ring_freewords(ring) >= ndwords)) 677 DRM_DEV_ERROR(ring->gpu->dev->dev, 678 "timeout waiting for space in ringbuffer %d\n", 679 ring->id); 680 } 681 682 /* Get legacy powerlevels from qcom,gpu-pwrlevels and populate the opp table */ 683 static int adreno_get_legacy_pwrlevels(struct device *dev) 684 { 685 struct device_node *child, *node; 686 int ret; 687 688 node = of_get_compatible_child(dev->of_node, "qcom,gpu-pwrlevels"); 689 if (!node) { 690 DRM_DEV_ERROR(dev, "Could not find the GPU powerlevels\n"); 691 return -ENXIO; 692 } 693 694 for_each_child_of_node(node, child) { 695 unsigned int val; 696 697 ret = of_property_read_u32(child, "qcom,gpu-freq", &val); 698 if (ret) 699 continue; 700 701 /* 702 * Skip the intentionally bogus clock value found at the bottom 703 * of most legacy frequency tables 704 */ 705 if (val != 27000000) 706 dev_pm_opp_add(dev, val, 0); 707 } 708 709 of_node_put(node); 710 711 return 0; 712 } 713 714 static int adreno_get_pwrlevels(struct device *dev, 715 struct msm_gpu *gpu) 716 { 717 unsigned long freq = ULONG_MAX; 718 struct dev_pm_opp *opp; 719 int ret; 720 721 gpu->fast_rate = 0; 722 723 /* You down with OPP? */ 724 if (!of_find_property(dev->of_node, "operating-points-v2", NULL)) 725 ret = adreno_get_legacy_pwrlevels(dev); 726 else { 727 ret = dev_pm_opp_of_add_table(dev); 728 if (ret) 729 DRM_DEV_ERROR(dev, "Unable to set the OPP table\n"); 730 } 731 732 if (!ret) { 733 /* Find the fastest defined rate */ 734 opp = dev_pm_opp_find_freq_floor(dev, &freq); 735 if (!IS_ERR(opp)) { 736 gpu->fast_rate = freq; 737 dev_pm_opp_put(opp); 738 } 739 } 740 741 if (!gpu->fast_rate) { 742 dev_warn(dev, 743 "Could not find a clock rate. Using a reasonable default\n"); 744 /* Pick a suitably safe clock speed for any target */ 745 gpu->fast_rate = 200000000; 746 } 747 748 DBG("fast_rate=%u, slow_rate=27000000", gpu->fast_rate); 749 750 return 0; 751 } 752 753 int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, 754 struct adreno_gpu *adreno_gpu, 755 const struct adreno_gpu_funcs *funcs, int nr_rings) 756 { 757 struct adreno_platform_config *config = pdev->dev.platform_data; 758 struct msm_gpu_config adreno_gpu_config = { 0 }; 759 struct msm_gpu *gpu = &adreno_gpu->base; 760 761 adreno_gpu->funcs = funcs; 762 adreno_gpu->info = adreno_info(config->rev); 763 adreno_gpu->gmem = adreno_gpu->info->gmem; 764 adreno_gpu->revn = adreno_gpu->info->revn; 765 adreno_gpu->rev = config->rev; 766 767 adreno_gpu_config.ioname = "kgsl_3d0_reg_memory"; 768 adreno_gpu_config.irqname = "kgsl_3d0_irq"; 769 770 adreno_gpu_config.va_start = SZ_16M; 771 adreno_gpu_config.va_end = 0xffffffff; 772 /* maximum range of a2xx mmu */ 773 if (adreno_is_a2xx(adreno_gpu)) 774 adreno_gpu_config.va_end = SZ_16M + 0xfff * SZ_64K; 775 776 adreno_gpu_config.nr_rings = nr_rings; 777 778 adreno_get_pwrlevels(&pdev->dev, gpu); 779 780 pm_runtime_set_autosuspend_delay(&pdev->dev, 781 adreno_gpu->info->inactive_period); 782 pm_runtime_use_autosuspend(&pdev->dev); 783 pm_runtime_enable(&pdev->dev); 784 785 return msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base, 786 adreno_gpu->info->name, &adreno_gpu_config); 787 } 788 789 void adreno_gpu_cleanup(struct adreno_gpu *adreno_gpu) 790 { 791 unsigned int i; 792 793 for (i = 0; i < ARRAY_SIZE(adreno_gpu->info->fw); i++) 794 release_firmware(adreno_gpu->fw[i]); 795 796 msm_gpu_cleanup(&adreno_gpu->base); 797 } 798