1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 Red Hat 4 * Author: Rob Clark <robdclark@gmail.com> 5 * 6 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 7 */ 8 9 #include <linux/ascii85.h> 10 #include <linux/interconnect.h> 11 #include <linux/qcom_scm.h> 12 #include <linux/kernel.h> 13 #include <linux/of_address.h> 14 #include <linux/pm_opp.h> 15 #include <linux/slab.h> 16 #include <linux/soc/qcom/mdt_loader.h> 17 #include "adreno_gpu.h" 18 #include "msm_gem.h" 19 #include "msm_mmu.h" 20 21 static bool zap_available = true; 22 23 static int zap_shader_load_mdt(struct msm_gpu *gpu, const char *fwname, 24 u32 pasid) 25 { 26 struct device *dev = &gpu->pdev->dev; 27 const struct firmware *fw; 28 struct device_node *np, *mem_np; 29 struct resource r; 30 phys_addr_t mem_phys; 31 ssize_t mem_size; 32 void *mem_region = NULL; 33 int ret; 34 35 if (!IS_ENABLED(CONFIG_ARCH_QCOM)) { 36 zap_available = false; 37 return -EINVAL; 38 } 39 40 np = of_get_child_by_name(dev->of_node, "zap-shader"); 41 if (!np) { 42 zap_available = false; 43 return -ENODEV; 44 } 45 46 mem_np = of_parse_phandle(np, "memory-region", 0); 47 of_node_put(np); 48 if (!mem_np) { 49 zap_available = false; 50 return -EINVAL; 51 } 52 53 ret = of_address_to_resource(mem_np, 0, &r); 54 of_node_put(mem_np); 55 if (ret) 56 return ret; 57 58 mem_phys = r.start; 59 mem_size = resource_size(&r); 60 61 /* Request the MDT file for the firmware */ 62 fw = adreno_request_fw(to_adreno_gpu(gpu), fwname); 63 if (IS_ERR(fw)) { 64 DRM_DEV_ERROR(dev, "Unable to load %s\n", fwname); 65 return PTR_ERR(fw); 66 } 67 68 /* Figure out how much memory we need */ 69 mem_size = qcom_mdt_get_size(fw); 70 if (mem_size < 0) { 71 ret = mem_size; 72 goto out; 73 } 74 75 /* Allocate memory for the firmware image */ 76 mem_region = memremap(mem_phys, mem_size, MEMREMAP_WC); 77 if (!mem_region) { 78 ret = -ENOMEM; 79 goto out; 80 } 81 82 /* 83 * Load the rest of the MDT 84 * 85 * Note that we could be dealing with two different paths, since 86 * with upstream linux-firmware it would be in a qcom/ subdir.. 87 * adreno_request_fw() handles this, but qcom_mdt_load() does 88 * not. But since we've already gotten through adreno_request_fw() 89 * we know which of the two cases it is: 90 */ 91 if (to_adreno_gpu(gpu)->fwloc == FW_LOCATION_LEGACY) { 92 ret = qcom_mdt_load(dev, fw, fwname, pasid, 93 mem_region, mem_phys, mem_size, NULL); 94 } else { 95 char *newname; 96 97 newname = kasprintf(GFP_KERNEL, "qcom/%s", fwname); 98 99 ret = qcom_mdt_load(dev, fw, newname, pasid, 100 mem_region, mem_phys, mem_size, NULL); 101 kfree(newname); 102 } 103 if (ret) 104 goto out; 105 106 /* Send the image to the secure world */ 107 ret = qcom_scm_pas_auth_and_reset(pasid); 108 109 /* 110 * If the scm call returns -EOPNOTSUPP we assume that this target 111 * doesn't need/support the zap shader so quietly fail 112 */ 113 if (ret == -EOPNOTSUPP) 114 zap_available = false; 115 else if (ret) 116 DRM_DEV_ERROR(dev, "Unable to authorize the image\n"); 117 118 out: 119 if (mem_region) 120 memunmap(mem_region); 121 122 release_firmware(fw); 123 124 return ret; 125 } 126 127 int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid) 128 { 129 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 130 struct platform_device *pdev = gpu->pdev; 131 132 /* Short cut if we determine the zap shader isn't available/needed */ 133 if (!zap_available) 134 return -ENODEV; 135 136 /* We need SCM to be able to load the firmware */ 137 if (!qcom_scm_is_available()) { 138 DRM_DEV_ERROR(&pdev->dev, "SCM is not available\n"); 139 return -EPROBE_DEFER; 140 } 141 142 /* Each GPU has a target specific zap shader firmware name to use */ 143 if (!adreno_gpu->info->zapfw) { 144 zap_available = false; 145 DRM_DEV_ERROR(&pdev->dev, 146 "Zap shader firmware file not specified for this target\n"); 147 return -ENODEV; 148 } 149 150 return zap_shader_load_mdt(gpu, adreno_gpu->info->zapfw, pasid); 151 } 152 153 int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value) 154 { 155 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 156 157 switch (param) { 158 case MSM_PARAM_GPU_ID: 159 *value = adreno_gpu->info->revn; 160 return 0; 161 case MSM_PARAM_GMEM_SIZE: 162 *value = adreno_gpu->gmem; 163 return 0; 164 case MSM_PARAM_GMEM_BASE: 165 *value = 0x100000; 166 return 0; 167 case MSM_PARAM_CHIP_ID: 168 *value = adreno_gpu->rev.patchid | 169 (adreno_gpu->rev.minor << 8) | 170 (adreno_gpu->rev.major << 16) | 171 (adreno_gpu->rev.core << 24); 172 return 0; 173 case MSM_PARAM_MAX_FREQ: 174 *value = adreno_gpu->base.fast_rate; 175 return 0; 176 case MSM_PARAM_TIMESTAMP: 177 if (adreno_gpu->funcs->get_timestamp) { 178 int ret; 179 180 pm_runtime_get_sync(&gpu->pdev->dev); 181 ret = adreno_gpu->funcs->get_timestamp(gpu, value); 182 pm_runtime_put_autosuspend(&gpu->pdev->dev); 183 184 return ret; 185 } 186 return -EINVAL; 187 case MSM_PARAM_NR_RINGS: 188 *value = gpu->nr_rings; 189 return 0; 190 case MSM_PARAM_PP_PGTABLE: 191 *value = 0; 192 return 0; 193 case MSM_PARAM_FAULTS: 194 *value = gpu->global_faults; 195 return 0; 196 default: 197 DBG("%s: invalid param: %u", gpu->name, param); 198 return -EINVAL; 199 } 200 } 201 202 const struct firmware * 203 adreno_request_fw(struct adreno_gpu *adreno_gpu, const char *fwname) 204 { 205 struct drm_device *drm = adreno_gpu->base.dev; 206 const struct firmware *fw = NULL; 207 char *newname; 208 int ret; 209 210 newname = kasprintf(GFP_KERNEL, "qcom/%s", fwname); 211 if (!newname) 212 return ERR_PTR(-ENOMEM); 213 214 /* 215 * Try first to load from qcom/$fwfile using a direct load (to avoid 216 * a potential timeout waiting for usermode helper) 217 */ 218 if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) || 219 (adreno_gpu->fwloc == FW_LOCATION_NEW)) { 220 221 ret = request_firmware_direct(&fw, newname, drm->dev); 222 if (!ret) { 223 DRM_DEV_INFO(drm->dev, "loaded %s from new location\n", 224 newname); 225 adreno_gpu->fwloc = FW_LOCATION_NEW; 226 goto out; 227 } else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) { 228 DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n", 229 newname, ret); 230 fw = ERR_PTR(ret); 231 goto out; 232 } 233 } 234 235 /* 236 * Then try the legacy location without qcom/ prefix 237 */ 238 if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) || 239 (adreno_gpu->fwloc == FW_LOCATION_LEGACY)) { 240 241 ret = request_firmware_direct(&fw, fwname, drm->dev); 242 if (!ret) { 243 DRM_DEV_INFO(drm->dev, "loaded %s from legacy location\n", 244 newname); 245 adreno_gpu->fwloc = FW_LOCATION_LEGACY; 246 goto out; 247 } else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) { 248 DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n", 249 fwname, ret); 250 fw = ERR_PTR(ret); 251 goto out; 252 } 253 } 254 255 /* 256 * Finally fall back to request_firmware() for cases where the 257 * usermode helper is needed (I think mainly android) 258 */ 259 if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) || 260 (adreno_gpu->fwloc == FW_LOCATION_HELPER)) { 261 262 ret = request_firmware(&fw, newname, drm->dev); 263 if (!ret) { 264 DRM_DEV_INFO(drm->dev, "loaded %s with helper\n", 265 newname); 266 adreno_gpu->fwloc = FW_LOCATION_HELPER; 267 goto out; 268 } else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) { 269 DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n", 270 newname, ret); 271 fw = ERR_PTR(ret); 272 goto out; 273 } 274 } 275 276 DRM_DEV_ERROR(drm->dev, "failed to load %s\n", fwname); 277 fw = ERR_PTR(-ENOENT); 278 out: 279 kfree(newname); 280 return fw; 281 } 282 283 int adreno_load_fw(struct adreno_gpu *adreno_gpu) 284 { 285 int i; 286 287 for (i = 0; i < ARRAY_SIZE(adreno_gpu->info->fw); i++) { 288 const struct firmware *fw; 289 290 if (!adreno_gpu->info->fw[i]) 291 continue; 292 293 /* Skip if the firmware has already been loaded */ 294 if (adreno_gpu->fw[i]) 295 continue; 296 297 fw = adreno_request_fw(adreno_gpu, adreno_gpu->info->fw[i]); 298 if (IS_ERR(fw)) 299 return PTR_ERR(fw); 300 301 adreno_gpu->fw[i] = fw; 302 } 303 304 return 0; 305 } 306 307 struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu, 308 const struct firmware *fw, u64 *iova) 309 { 310 struct drm_gem_object *bo; 311 void *ptr; 312 313 ptr = msm_gem_kernel_new_locked(gpu->dev, fw->size - 4, 314 MSM_BO_UNCACHED | MSM_BO_GPU_READONLY, gpu->aspace, &bo, iova); 315 316 if (IS_ERR(ptr)) 317 return ERR_CAST(ptr); 318 319 memcpy(ptr, &fw->data[4], fw->size - 4); 320 321 msm_gem_put_vaddr(bo); 322 323 return bo; 324 } 325 326 int adreno_hw_init(struct msm_gpu *gpu) 327 { 328 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 329 int ret, i; 330 331 DBG("%s", gpu->name); 332 333 ret = adreno_load_fw(adreno_gpu); 334 if (ret) 335 return ret; 336 337 for (i = 0; i < gpu->nr_rings; i++) { 338 struct msm_ringbuffer *ring = gpu->rb[i]; 339 340 if (!ring) 341 continue; 342 343 ring->cur = ring->start; 344 ring->next = ring->start; 345 346 /* reset completed fence seqno: */ 347 ring->memptrs->fence = ring->seqno; 348 ring->memptrs->rptr = 0; 349 } 350 351 /* 352 * Setup REG_CP_RB_CNTL. The same value is used across targets (with 353 * the excpetion of A430 that disables the RPTR shadow) - the cacluation 354 * for the ringbuffer size and block size is moved to msm_gpu.h for the 355 * pre-processor to deal with and the A430 variant is ORed in here 356 */ 357 adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_CNTL, 358 MSM_GPU_RB_CNTL_DEFAULT | 359 (adreno_is_a430(adreno_gpu) ? AXXX_CP_RB_CNTL_NO_UPDATE : 0)); 360 361 /* Setup ringbuffer address - use ringbuffer[0] for GPU init */ 362 adreno_gpu_write64(adreno_gpu, REG_ADRENO_CP_RB_BASE, 363 REG_ADRENO_CP_RB_BASE_HI, gpu->rb[0]->iova); 364 365 if (!adreno_is_a430(adreno_gpu)) { 366 adreno_gpu_write64(adreno_gpu, REG_ADRENO_CP_RB_RPTR_ADDR, 367 REG_ADRENO_CP_RB_RPTR_ADDR_HI, 368 rbmemptr(gpu->rb[0], rptr)); 369 } 370 371 return 0; 372 } 373 374 /* Use this helper to read rptr, since a430 doesn't update rptr in memory */ 375 static uint32_t get_rptr(struct adreno_gpu *adreno_gpu, 376 struct msm_ringbuffer *ring) 377 { 378 if (adreno_is_a430(adreno_gpu)) 379 return ring->memptrs->rptr = adreno_gpu_read( 380 adreno_gpu, REG_ADRENO_CP_RB_RPTR); 381 else 382 return ring->memptrs->rptr; 383 } 384 385 struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu) 386 { 387 return gpu->rb[0]; 388 } 389 390 void adreno_recover(struct msm_gpu *gpu) 391 { 392 struct drm_device *dev = gpu->dev; 393 int ret; 394 395 // XXX pm-runtime?? we *need* the device to be off after this 396 // so maybe continuing to call ->pm_suspend/resume() is better? 397 398 gpu->funcs->pm_suspend(gpu); 399 gpu->funcs->pm_resume(gpu); 400 401 ret = msm_gpu_hw_init(gpu); 402 if (ret) { 403 DRM_DEV_ERROR(dev->dev, "gpu hw init failed: %d\n", ret); 404 /* hmm, oh well? */ 405 } 406 } 407 408 void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, 409 struct msm_file_private *ctx) 410 { 411 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 412 struct msm_drm_private *priv = gpu->dev->dev_private; 413 struct msm_ringbuffer *ring = submit->ring; 414 unsigned i; 415 416 for (i = 0; i < submit->nr_cmds; i++) { 417 switch (submit->cmd[i].type) { 418 case MSM_SUBMIT_CMD_IB_TARGET_BUF: 419 /* ignore IB-targets */ 420 break; 421 case MSM_SUBMIT_CMD_CTX_RESTORE_BUF: 422 /* ignore if there has not been a ctx switch: */ 423 if (priv->lastctx == ctx) 424 break; 425 case MSM_SUBMIT_CMD_BUF: 426 OUT_PKT3(ring, adreno_is_a430(adreno_gpu) ? 427 CP_INDIRECT_BUFFER_PFE : CP_INDIRECT_BUFFER_PFD, 2); 428 OUT_RING(ring, lower_32_bits(submit->cmd[i].iova)); 429 OUT_RING(ring, submit->cmd[i].size); 430 OUT_PKT2(ring); 431 break; 432 } 433 } 434 435 OUT_PKT0(ring, REG_AXXX_CP_SCRATCH_REG2, 1); 436 OUT_RING(ring, submit->seqno); 437 438 if (adreno_is_a3xx(adreno_gpu) || adreno_is_a4xx(adreno_gpu)) { 439 /* Flush HLSQ lazy updates to make sure there is nothing 440 * pending for indirect loads after the timestamp has 441 * passed: 442 */ 443 OUT_PKT3(ring, CP_EVENT_WRITE, 1); 444 OUT_RING(ring, HLSQ_FLUSH); 445 } 446 447 /* wait for idle before cache flush/interrupt */ 448 OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1); 449 OUT_RING(ring, 0x00000000); 450 451 if (!adreno_is_a2xx(adreno_gpu)) { 452 /* BIT(31) of CACHE_FLUSH_TS triggers CACHE_FLUSH_TS IRQ from GPU */ 453 OUT_PKT3(ring, CP_EVENT_WRITE, 3); 454 OUT_RING(ring, CACHE_FLUSH_TS | BIT(31)); 455 OUT_RING(ring, rbmemptr(ring, fence)); 456 OUT_RING(ring, submit->seqno); 457 } else { 458 /* BIT(31) means something else on a2xx */ 459 OUT_PKT3(ring, CP_EVENT_WRITE, 3); 460 OUT_RING(ring, CACHE_FLUSH_TS); 461 OUT_RING(ring, rbmemptr(ring, fence)); 462 OUT_RING(ring, submit->seqno); 463 OUT_PKT3(ring, CP_INTERRUPT, 1); 464 OUT_RING(ring, 0x80000000); 465 } 466 467 #if 0 468 if (adreno_is_a3xx(adreno_gpu)) { 469 /* Dummy set-constant to trigger context rollover */ 470 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 471 OUT_RING(ring, CP_REG(REG_A3XX_HLSQ_CL_KERNEL_GROUP_X_REG)); 472 OUT_RING(ring, 0x00000000); 473 } 474 #endif 475 476 gpu->funcs->flush(gpu, ring); 477 } 478 479 void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 480 { 481 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 482 uint32_t wptr; 483 484 /* Copy the shadow to the actual register */ 485 ring->cur = ring->next; 486 487 /* 488 * Mask wptr value that we calculate to fit in the HW range. This is 489 * to account for the possibility that the last command fit exactly into 490 * the ringbuffer and rb->next hasn't wrapped to zero yet 491 */ 492 wptr = get_wptr(ring); 493 494 /* ensure writes to ringbuffer have hit system memory: */ 495 mb(); 496 497 adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_WPTR, wptr); 498 } 499 500 bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 501 { 502 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 503 uint32_t wptr = get_wptr(ring); 504 505 /* wait for CP to drain ringbuffer: */ 506 if (!spin_until(get_rptr(adreno_gpu, ring) == wptr)) 507 return true; 508 509 /* TODO maybe we need to reset GPU here to recover from hang? */ 510 DRM_ERROR("%s: timeout waiting to drain ringbuffer %d rptr/wptr = %X/%X\n", 511 gpu->name, ring->id, get_rptr(adreno_gpu, ring), wptr); 512 513 return false; 514 } 515 516 int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state) 517 { 518 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 519 int i, count = 0; 520 521 kref_init(&state->ref); 522 523 ktime_get_real_ts64(&state->time); 524 525 for (i = 0; i < gpu->nr_rings; i++) { 526 int size = 0, j; 527 528 state->ring[i].fence = gpu->rb[i]->memptrs->fence; 529 state->ring[i].iova = gpu->rb[i]->iova; 530 state->ring[i].seqno = gpu->rb[i]->seqno; 531 state->ring[i].rptr = get_rptr(adreno_gpu, gpu->rb[i]); 532 state->ring[i].wptr = get_wptr(gpu->rb[i]); 533 534 /* Copy at least 'wptr' dwords of the data */ 535 size = state->ring[i].wptr; 536 537 /* After wptr find the last non zero dword to save space */ 538 for (j = state->ring[i].wptr; j < MSM_GPU_RINGBUFFER_SZ >> 2; j++) 539 if (gpu->rb[i]->start[j]) 540 size = j + 1; 541 542 if (size) { 543 state->ring[i].data = kvmalloc(size << 2, GFP_KERNEL); 544 if (state->ring[i].data) { 545 memcpy(state->ring[i].data, gpu->rb[i]->start, size << 2); 546 state->ring[i].data_size = size << 2; 547 } 548 } 549 } 550 551 /* Some targets prefer to collect their own registers */ 552 if (!adreno_gpu->registers) 553 return 0; 554 555 /* Count the number of registers */ 556 for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) 557 count += adreno_gpu->registers[i + 1] - 558 adreno_gpu->registers[i] + 1; 559 560 state->registers = kcalloc(count * 2, sizeof(u32), GFP_KERNEL); 561 if (state->registers) { 562 int pos = 0; 563 564 for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) { 565 u32 start = adreno_gpu->registers[i]; 566 u32 end = adreno_gpu->registers[i + 1]; 567 u32 addr; 568 569 for (addr = start; addr <= end; addr++) { 570 state->registers[pos++] = addr; 571 state->registers[pos++] = gpu_read(gpu, addr); 572 } 573 } 574 575 state->nr_registers = count; 576 } 577 578 return 0; 579 } 580 581 void adreno_gpu_state_destroy(struct msm_gpu_state *state) 582 { 583 int i; 584 585 for (i = 0; i < ARRAY_SIZE(state->ring); i++) 586 kvfree(state->ring[i].data); 587 588 for (i = 0; state->bos && i < state->nr_bos; i++) 589 kvfree(state->bos[i].data); 590 591 kfree(state->bos); 592 kfree(state->comm); 593 kfree(state->cmd); 594 kfree(state->registers); 595 } 596 597 static void adreno_gpu_state_kref_destroy(struct kref *kref) 598 { 599 struct msm_gpu_state *state = container_of(kref, 600 struct msm_gpu_state, ref); 601 602 adreno_gpu_state_destroy(state); 603 kfree(state); 604 } 605 606 int adreno_gpu_state_put(struct msm_gpu_state *state) 607 { 608 if (IS_ERR_OR_NULL(state)) 609 return 1; 610 611 return kref_put(&state->ref, adreno_gpu_state_kref_destroy); 612 } 613 614 #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP) 615 616 static char *adreno_gpu_ascii85_encode(u32 *src, size_t len) 617 { 618 void *buf; 619 size_t buf_itr = 0, buffer_size; 620 char out[ASCII85_BUFSZ]; 621 long l; 622 int i; 623 624 if (!src || !len) 625 return NULL; 626 627 l = ascii85_encode_len(len); 628 629 /* 630 * Ascii85 outputs either a 5 byte string or a 1 byte string. So we 631 * account for the worst case of 5 bytes per dword plus the 1 for '\0' 632 */ 633 buffer_size = (l * 5) + 1; 634 635 buf = kvmalloc(buffer_size, GFP_KERNEL); 636 if (!buf) 637 return NULL; 638 639 for (i = 0; i < l; i++) 640 buf_itr += snprintf(buf + buf_itr, buffer_size - buf_itr, "%s", 641 ascii85_encode(src[i], out)); 642 643 return buf; 644 } 645 646 /* len is expected to be in bytes */ 647 static void adreno_show_object(struct drm_printer *p, void **ptr, int len, 648 bool *encoded) 649 { 650 if (!*ptr || !len) 651 return; 652 653 if (!*encoded) { 654 long datalen, i; 655 u32 *buf = *ptr; 656 657 /* 658 * Only dump the non-zero part of the buffer - rarely will 659 * any data completely fill the entire allocated size of 660 * the buffer. 661 */ 662 for (datalen = 0, i = 0; i < len >> 2; i++) 663 if (buf[i]) 664 datalen = ((i + 1) << 2); 665 666 /* 667 * If we reach here, then the originally captured binary buffer 668 * will be replaced with the ascii85 encoded string 669 */ 670 *ptr = adreno_gpu_ascii85_encode(buf, datalen); 671 672 kvfree(buf); 673 674 *encoded = true; 675 } 676 677 if (!*ptr) 678 return; 679 680 drm_puts(p, " data: !!ascii85 |\n"); 681 drm_puts(p, " "); 682 683 drm_puts(p, *ptr); 684 685 drm_puts(p, "\n"); 686 } 687 688 void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state, 689 struct drm_printer *p) 690 { 691 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 692 int i; 693 694 if (IS_ERR_OR_NULL(state)) 695 return; 696 697 drm_printf(p, "revision: %d (%d.%d.%d.%d)\n", 698 adreno_gpu->info->revn, adreno_gpu->rev.core, 699 adreno_gpu->rev.major, adreno_gpu->rev.minor, 700 adreno_gpu->rev.patchid); 701 702 drm_printf(p, "rbbm-status: 0x%08x\n", state->rbbm_status); 703 704 drm_puts(p, "ringbuffer:\n"); 705 706 for (i = 0; i < gpu->nr_rings; i++) { 707 drm_printf(p, " - id: %d\n", i); 708 drm_printf(p, " iova: 0x%016llx\n", state->ring[i].iova); 709 drm_printf(p, " last-fence: %d\n", state->ring[i].seqno); 710 drm_printf(p, " retired-fence: %d\n", state->ring[i].fence); 711 drm_printf(p, " rptr: %d\n", state->ring[i].rptr); 712 drm_printf(p, " wptr: %d\n", state->ring[i].wptr); 713 drm_printf(p, " size: %d\n", MSM_GPU_RINGBUFFER_SZ); 714 715 adreno_show_object(p, &state->ring[i].data, 716 state->ring[i].data_size, &state->ring[i].encoded); 717 } 718 719 if (state->bos) { 720 drm_puts(p, "bos:\n"); 721 722 for (i = 0; i < state->nr_bos; i++) { 723 drm_printf(p, " - iova: 0x%016llx\n", 724 state->bos[i].iova); 725 drm_printf(p, " size: %zd\n", state->bos[i].size); 726 727 adreno_show_object(p, &state->bos[i].data, 728 state->bos[i].size, &state->bos[i].encoded); 729 } 730 } 731 732 if (state->nr_registers) { 733 drm_puts(p, "registers:\n"); 734 735 for (i = 0; i < state->nr_registers; i++) { 736 drm_printf(p, " - { offset: 0x%04x, value: 0x%08x }\n", 737 state->registers[i * 2] << 2, 738 state->registers[(i * 2) + 1]); 739 } 740 } 741 } 742 #endif 743 744 /* Dump common gpu status and scratch registers on any hang, to make 745 * the hangcheck logs more useful. The scratch registers seem always 746 * safe to read when GPU has hung (unlike some other regs, depending 747 * on how the GPU hung), and they are useful to match up to cmdstream 748 * dumps when debugging hangs: 749 */ 750 void adreno_dump_info(struct msm_gpu *gpu) 751 { 752 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 753 int i; 754 755 printk("revision: %d (%d.%d.%d.%d)\n", 756 adreno_gpu->info->revn, adreno_gpu->rev.core, 757 adreno_gpu->rev.major, adreno_gpu->rev.minor, 758 adreno_gpu->rev.patchid); 759 760 for (i = 0; i < gpu->nr_rings; i++) { 761 struct msm_ringbuffer *ring = gpu->rb[i]; 762 763 printk("rb %d: fence: %d/%d\n", i, 764 ring->memptrs->fence, 765 ring->seqno); 766 767 printk("rptr: %d\n", get_rptr(adreno_gpu, ring)); 768 printk("rb wptr: %d\n", get_wptr(ring)); 769 } 770 } 771 772 /* would be nice to not have to duplicate the _show() stuff with printk(): */ 773 void adreno_dump(struct msm_gpu *gpu) 774 { 775 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 776 int i; 777 778 if (!adreno_gpu->registers) 779 return; 780 781 /* dump these out in a form that can be parsed by demsm: */ 782 printk("IO:region %s 00000000 00020000\n", gpu->name); 783 for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) { 784 uint32_t start = adreno_gpu->registers[i]; 785 uint32_t end = adreno_gpu->registers[i+1]; 786 uint32_t addr; 787 788 for (addr = start; addr <= end; addr++) { 789 uint32_t val = gpu_read(gpu, addr); 790 printk("IO:R %08x %08x\n", addr<<2, val); 791 } 792 } 793 } 794 795 static uint32_t ring_freewords(struct msm_ringbuffer *ring) 796 { 797 struct adreno_gpu *adreno_gpu = to_adreno_gpu(ring->gpu); 798 uint32_t size = MSM_GPU_RINGBUFFER_SZ >> 2; 799 /* Use ring->next to calculate free size */ 800 uint32_t wptr = ring->next - ring->start; 801 uint32_t rptr = get_rptr(adreno_gpu, ring); 802 return (rptr + (size - 1) - wptr) % size; 803 } 804 805 void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords) 806 { 807 if (spin_until(ring_freewords(ring) >= ndwords)) 808 DRM_DEV_ERROR(ring->gpu->dev->dev, 809 "timeout waiting for space in ringbuffer %d\n", 810 ring->id); 811 } 812 813 /* Get legacy powerlevels from qcom,gpu-pwrlevels and populate the opp table */ 814 static int adreno_get_legacy_pwrlevels(struct device *dev) 815 { 816 struct device_node *child, *node; 817 int ret; 818 819 node = of_get_compatible_child(dev->of_node, "qcom,gpu-pwrlevels"); 820 if (!node) { 821 DRM_DEV_ERROR(dev, "Could not find the GPU powerlevels\n"); 822 return -ENXIO; 823 } 824 825 for_each_child_of_node(node, child) { 826 unsigned int val; 827 828 ret = of_property_read_u32(child, "qcom,gpu-freq", &val); 829 if (ret) 830 continue; 831 832 /* 833 * Skip the intentionally bogus clock value found at the bottom 834 * of most legacy frequency tables 835 */ 836 if (val != 27000000) 837 dev_pm_opp_add(dev, val, 0); 838 } 839 840 of_node_put(node); 841 842 return 0; 843 } 844 845 static int adreno_get_pwrlevels(struct device *dev, 846 struct msm_gpu *gpu) 847 { 848 unsigned long freq = ULONG_MAX; 849 struct dev_pm_opp *opp; 850 int ret; 851 852 gpu->fast_rate = 0; 853 854 /* You down with OPP? */ 855 if (!of_find_property(dev->of_node, "operating-points-v2", NULL)) 856 ret = adreno_get_legacy_pwrlevels(dev); 857 else { 858 ret = dev_pm_opp_of_add_table(dev); 859 if (ret) 860 DRM_DEV_ERROR(dev, "Unable to set the OPP table\n"); 861 } 862 863 if (!ret) { 864 /* Find the fastest defined rate */ 865 opp = dev_pm_opp_find_freq_floor(dev, &freq); 866 if (!IS_ERR(opp)) { 867 gpu->fast_rate = freq; 868 dev_pm_opp_put(opp); 869 } 870 } 871 872 if (!gpu->fast_rate) { 873 dev_warn(dev, 874 "Could not find a clock rate. Using a reasonable default\n"); 875 /* Pick a suitably safe clock speed for any target */ 876 gpu->fast_rate = 200000000; 877 } 878 879 DBG("fast_rate=%u, slow_rate=27000000", gpu->fast_rate); 880 881 /* Check for an interconnect path for the bus */ 882 gpu->icc_path = of_icc_get(dev, NULL); 883 if (IS_ERR(gpu->icc_path)) 884 gpu->icc_path = NULL; 885 886 return 0; 887 } 888 889 int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, 890 struct adreno_gpu *adreno_gpu, 891 const struct adreno_gpu_funcs *funcs, int nr_rings) 892 { 893 struct adreno_platform_config *config = pdev->dev.platform_data; 894 struct msm_gpu_config adreno_gpu_config = { 0 }; 895 struct msm_gpu *gpu = &adreno_gpu->base; 896 897 adreno_gpu->funcs = funcs; 898 adreno_gpu->info = adreno_info(config->rev); 899 adreno_gpu->gmem = adreno_gpu->info->gmem; 900 adreno_gpu->revn = adreno_gpu->info->revn; 901 adreno_gpu->rev = config->rev; 902 903 adreno_gpu_config.ioname = "kgsl_3d0_reg_memory"; 904 905 adreno_gpu_config.va_start = SZ_16M; 906 adreno_gpu_config.va_end = 0xffffffff; 907 /* maximum range of a2xx mmu */ 908 if (adreno_is_a2xx(adreno_gpu)) 909 adreno_gpu_config.va_end = SZ_16M + 0xfff * SZ_64K; 910 911 adreno_gpu_config.nr_rings = nr_rings; 912 913 adreno_get_pwrlevels(&pdev->dev, gpu); 914 915 pm_runtime_set_autosuspend_delay(&pdev->dev, 916 adreno_gpu->info->inactive_period); 917 pm_runtime_use_autosuspend(&pdev->dev); 918 pm_runtime_enable(&pdev->dev); 919 920 return msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base, 921 adreno_gpu->info->name, &adreno_gpu_config); 922 } 923 924 void adreno_gpu_cleanup(struct adreno_gpu *adreno_gpu) 925 { 926 struct msm_gpu *gpu = &adreno_gpu->base; 927 unsigned int i; 928 929 for (i = 0; i < ARRAY_SIZE(adreno_gpu->info->fw); i++) 930 release_firmware(adreno_gpu->fw[i]); 931 932 icc_put(gpu->icc_path); 933 934 msm_gpu_cleanup(&adreno_gpu->base); 935 } 936