1 /* 2 * Copyright (C) 2013 Red Hat 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License version 2 as published by 9 * the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include <linux/ascii85.h> 21 #include <linux/interconnect.h> 22 #include <linux/kernel.h> 23 #include <linux/pm_opp.h> 24 #include <linux/slab.h> 25 #include "adreno_gpu.h" 26 #include "msm_gem.h" 27 #include "msm_mmu.h" 28 29 int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value) 30 { 31 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 32 33 switch (param) { 34 case MSM_PARAM_GPU_ID: 35 *value = adreno_gpu->info->revn; 36 return 0; 37 case MSM_PARAM_GMEM_SIZE: 38 *value = adreno_gpu->gmem; 39 return 0; 40 case MSM_PARAM_GMEM_BASE: 41 *value = 0x100000; 42 return 0; 43 case MSM_PARAM_CHIP_ID: 44 *value = adreno_gpu->rev.patchid | 45 (adreno_gpu->rev.minor << 8) | 46 (adreno_gpu->rev.major << 16) | 47 (adreno_gpu->rev.core << 24); 48 return 0; 49 case MSM_PARAM_MAX_FREQ: 50 *value = adreno_gpu->base.fast_rate; 51 return 0; 52 case MSM_PARAM_TIMESTAMP: 53 if (adreno_gpu->funcs->get_timestamp) { 54 int ret; 55 56 pm_runtime_get_sync(&gpu->pdev->dev); 57 ret = adreno_gpu->funcs->get_timestamp(gpu, value); 58 pm_runtime_put_autosuspend(&gpu->pdev->dev); 59 60 return ret; 61 } 62 return -EINVAL; 63 case MSM_PARAM_NR_RINGS: 64 *value = gpu->nr_rings; 65 return 0; 66 default: 67 DBG("%s: invalid param: %u", gpu->name, param); 68 return -EINVAL; 69 } 70 } 71 72 const struct firmware * 73 adreno_request_fw(struct adreno_gpu *adreno_gpu, const char *fwname) 74 { 75 struct drm_device *drm = adreno_gpu->base.dev; 76 const struct firmware *fw = NULL; 77 char *newname; 78 int ret; 79 80 newname = kasprintf(GFP_KERNEL, "qcom/%s", fwname); 81 if (!newname) 82 return ERR_PTR(-ENOMEM); 83 84 /* 85 * Try first to load from qcom/$fwfile using a direct load (to avoid 86 * a potential timeout waiting for usermode helper) 87 */ 88 if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) || 89 (adreno_gpu->fwloc == FW_LOCATION_NEW)) { 90 91 ret = request_firmware_direct(&fw, newname, drm->dev); 92 if (!ret) { 93 DRM_DEV_INFO(drm->dev, "loaded %s from new location\n", 94 newname); 95 adreno_gpu->fwloc = FW_LOCATION_NEW; 96 goto out; 97 } else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) { 98 DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n", 99 newname, ret); 100 fw = ERR_PTR(ret); 101 goto out; 102 } 103 } 104 105 /* 106 * Then try the legacy location without qcom/ prefix 107 */ 108 if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) || 109 (adreno_gpu->fwloc == FW_LOCATION_LEGACY)) { 110 111 ret = request_firmware_direct(&fw, fwname, drm->dev); 112 if (!ret) { 113 DRM_DEV_INFO(drm->dev, "loaded %s from legacy location\n", 114 newname); 115 adreno_gpu->fwloc = FW_LOCATION_LEGACY; 116 goto out; 117 } else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) { 118 DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n", 119 fwname, ret); 120 fw = ERR_PTR(ret); 121 goto out; 122 } 123 } 124 125 /* 126 * Finally fall back to request_firmware() for cases where the 127 * usermode helper is needed (I think mainly android) 128 */ 129 if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) || 130 (adreno_gpu->fwloc == FW_LOCATION_HELPER)) { 131 132 ret = request_firmware(&fw, newname, drm->dev); 133 if (!ret) { 134 DRM_DEV_INFO(drm->dev, "loaded %s with helper\n", 135 newname); 136 adreno_gpu->fwloc = FW_LOCATION_HELPER; 137 goto out; 138 } else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) { 139 DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n", 140 newname, ret); 141 fw = ERR_PTR(ret); 142 goto out; 143 } 144 } 145 146 DRM_DEV_ERROR(drm->dev, "failed to load %s\n", fwname); 147 fw = ERR_PTR(-ENOENT); 148 out: 149 kfree(newname); 150 return fw; 151 } 152 153 int adreno_load_fw(struct adreno_gpu *adreno_gpu) 154 { 155 int i; 156 157 for (i = 0; i < ARRAY_SIZE(adreno_gpu->info->fw); i++) { 158 const struct firmware *fw; 159 160 if (!adreno_gpu->info->fw[i]) 161 continue; 162 163 /* Skip if the firmware has already been loaded */ 164 if (adreno_gpu->fw[i]) 165 continue; 166 167 fw = adreno_request_fw(adreno_gpu, adreno_gpu->info->fw[i]); 168 if (IS_ERR(fw)) 169 return PTR_ERR(fw); 170 171 adreno_gpu->fw[i] = fw; 172 } 173 174 return 0; 175 } 176 177 struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu, 178 const struct firmware *fw, u64 *iova) 179 { 180 struct drm_gem_object *bo; 181 void *ptr; 182 183 ptr = msm_gem_kernel_new_locked(gpu->dev, fw->size - 4, 184 MSM_BO_UNCACHED | MSM_BO_GPU_READONLY, gpu->aspace, &bo, iova); 185 186 if (IS_ERR(ptr)) 187 return ERR_CAST(ptr); 188 189 memcpy(ptr, &fw->data[4], fw->size - 4); 190 191 msm_gem_put_vaddr(bo); 192 193 return bo; 194 } 195 196 int adreno_hw_init(struct msm_gpu *gpu) 197 { 198 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 199 int ret, i; 200 201 DBG("%s", gpu->name); 202 203 ret = adreno_load_fw(adreno_gpu); 204 if (ret) 205 return ret; 206 207 for (i = 0; i < gpu->nr_rings; i++) { 208 struct msm_ringbuffer *ring = gpu->rb[i]; 209 210 if (!ring) 211 continue; 212 213 ring->cur = ring->start; 214 ring->next = ring->start; 215 216 /* reset completed fence seqno: */ 217 ring->memptrs->fence = ring->seqno; 218 ring->memptrs->rptr = 0; 219 } 220 221 /* 222 * Setup REG_CP_RB_CNTL. The same value is used across targets (with 223 * the excpetion of A430 that disables the RPTR shadow) - the cacluation 224 * for the ringbuffer size and block size is moved to msm_gpu.h for the 225 * pre-processor to deal with and the A430 variant is ORed in here 226 */ 227 adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_CNTL, 228 MSM_GPU_RB_CNTL_DEFAULT | 229 (adreno_is_a430(adreno_gpu) ? AXXX_CP_RB_CNTL_NO_UPDATE : 0)); 230 231 /* Setup ringbuffer address - use ringbuffer[0] for GPU init */ 232 adreno_gpu_write64(adreno_gpu, REG_ADRENO_CP_RB_BASE, 233 REG_ADRENO_CP_RB_BASE_HI, gpu->rb[0]->iova); 234 235 if (!adreno_is_a430(adreno_gpu)) { 236 adreno_gpu_write64(adreno_gpu, REG_ADRENO_CP_RB_RPTR_ADDR, 237 REG_ADRENO_CP_RB_RPTR_ADDR_HI, 238 rbmemptr(gpu->rb[0], rptr)); 239 } 240 241 return 0; 242 } 243 244 /* Use this helper to read rptr, since a430 doesn't update rptr in memory */ 245 static uint32_t get_rptr(struct adreno_gpu *adreno_gpu, 246 struct msm_ringbuffer *ring) 247 { 248 if (adreno_is_a430(adreno_gpu)) 249 return ring->memptrs->rptr = adreno_gpu_read( 250 adreno_gpu, REG_ADRENO_CP_RB_RPTR); 251 else 252 return ring->memptrs->rptr; 253 } 254 255 struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu) 256 { 257 return gpu->rb[0]; 258 } 259 260 void adreno_recover(struct msm_gpu *gpu) 261 { 262 struct drm_device *dev = gpu->dev; 263 int ret; 264 265 // XXX pm-runtime?? we *need* the device to be off after this 266 // so maybe continuing to call ->pm_suspend/resume() is better? 267 268 gpu->funcs->pm_suspend(gpu); 269 gpu->funcs->pm_resume(gpu); 270 271 ret = msm_gpu_hw_init(gpu); 272 if (ret) { 273 DRM_DEV_ERROR(dev->dev, "gpu hw init failed: %d\n", ret); 274 /* hmm, oh well? */ 275 } 276 } 277 278 void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, 279 struct msm_file_private *ctx) 280 { 281 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 282 struct msm_drm_private *priv = gpu->dev->dev_private; 283 struct msm_ringbuffer *ring = submit->ring; 284 unsigned i; 285 286 for (i = 0; i < submit->nr_cmds; i++) { 287 switch (submit->cmd[i].type) { 288 case MSM_SUBMIT_CMD_IB_TARGET_BUF: 289 /* ignore IB-targets */ 290 break; 291 case MSM_SUBMIT_CMD_CTX_RESTORE_BUF: 292 /* ignore if there has not been a ctx switch: */ 293 if (priv->lastctx == ctx) 294 break; 295 case MSM_SUBMIT_CMD_BUF: 296 OUT_PKT3(ring, adreno_is_a430(adreno_gpu) ? 297 CP_INDIRECT_BUFFER_PFE : CP_INDIRECT_BUFFER_PFD, 2); 298 OUT_RING(ring, lower_32_bits(submit->cmd[i].iova)); 299 OUT_RING(ring, submit->cmd[i].size); 300 OUT_PKT2(ring); 301 break; 302 } 303 } 304 305 OUT_PKT0(ring, REG_AXXX_CP_SCRATCH_REG2, 1); 306 OUT_RING(ring, submit->seqno); 307 308 if (adreno_is_a3xx(adreno_gpu) || adreno_is_a4xx(adreno_gpu)) { 309 /* Flush HLSQ lazy updates to make sure there is nothing 310 * pending for indirect loads after the timestamp has 311 * passed: 312 */ 313 OUT_PKT3(ring, CP_EVENT_WRITE, 1); 314 OUT_RING(ring, HLSQ_FLUSH); 315 } 316 317 /* wait for idle before cache flush/interrupt */ 318 OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1); 319 OUT_RING(ring, 0x00000000); 320 321 if (!adreno_is_a2xx(adreno_gpu)) { 322 /* BIT(31) of CACHE_FLUSH_TS triggers CACHE_FLUSH_TS IRQ from GPU */ 323 OUT_PKT3(ring, CP_EVENT_WRITE, 3); 324 OUT_RING(ring, CACHE_FLUSH_TS | BIT(31)); 325 OUT_RING(ring, rbmemptr(ring, fence)); 326 OUT_RING(ring, submit->seqno); 327 } else { 328 /* BIT(31) means something else on a2xx */ 329 OUT_PKT3(ring, CP_EVENT_WRITE, 3); 330 OUT_RING(ring, CACHE_FLUSH_TS); 331 OUT_RING(ring, rbmemptr(ring, fence)); 332 OUT_RING(ring, submit->seqno); 333 OUT_PKT3(ring, CP_INTERRUPT, 1); 334 OUT_RING(ring, 0x80000000); 335 } 336 337 #if 0 338 if (adreno_is_a3xx(adreno_gpu)) { 339 /* Dummy set-constant to trigger context rollover */ 340 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 341 OUT_RING(ring, CP_REG(REG_A3XX_HLSQ_CL_KERNEL_GROUP_X_REG)); 342 OUT_RING(ring, 0x00000000); 343 } 344 #endif 345 346 gpu->funcs->flush(gpu, ring); 347 } 348 349 void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 350 { 351 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 352 uint32_t wptr; 353 354 /* Copy the shadow to the actual register */ 355 ring->cur = ring->next; 356 357 /* 358 * Mask wptr value that we calculate to fit in the HW range. This is 359 * to account for the possibility that the last command fit exactly into 360 * the ringbuffer and rb->next hasn't wrapped to zero yet 361 */ 362 wptr = get_wptr(ring); 363 364 /* ensure writes to ringbuffer have hit system memory: */ 365 mb(); 366 367 adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_WPTR, wptr); 368 } 369 370 bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 371 { 372 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 373 uint32_t wptr = get_wptr(ring); 374 375 /* wait for CP to drain ringbuffer: */ 376 if (!spin_until(get_rptr(adreno_gpu, ring) == wptr)) 377 return true; 378 379 /* TODO maybe we need to reset GPU here to recover from hang? */ 380 DRM_ERROR("%s: timeout waiting to drain ringbuffer %d rptr/wptr = %X/%X\n", 381 gpu->name, ring->id, get_rptr(adreno_gpu, ring), wptr); 382 383 return false; 384 } 385 386 int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state) 387 { 388 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 389 int i, count = 0; 390 391 kref_init(&state->ref); 392 393 ktime_get_real_ts64(&state->time); 394 395 for (i = 0; i < gpu->nr_rings; i++) { 396 int size = 0, j; 397 398 state->ring[i].fence = gpu->rb[i]->memptrs->fence; 399 state->ring[i].iova = gpu->rb[i]->iova; 400 state->ring[i].seqno = gpu->rb[i]->seqno; 401 state->ring[i].rptr = get_rptr(adreno_gpu, gpu->rb[i]); 402 state->ring[i].wptr = get_wptr(gpu->rb[i]); 403 404 /* Copy at least 'wptr' dwords of the data */ 405 size = state->ring[i].wptr; 406 407 /* After wptr find the last non zero dword to save space */ 408 for (j = state->ring[i].wptr; j < MSM_GPU_RINGBUFFER_SZ >> 2; j++) 409 if (gpu->rb[i]->start[j]) 410 size = j + 1; 411 412 if (size) { 413 state->ring[i].data = kvmalloc(size << 2, GFP_KERNEL); 414 if (state->ring[i].data) { 415 memcpy(state->ring[i].data, gpu->rb[i]->start, size << 2); 416 state->ring[i].data_size = size << 2; 417 } 418 } 419 } 420 421 /* Some targets prefer to collect their own registers */ 422 if (!adreno_gpu->registers) 423 return 0; 424 425 /* Count the number of registers */ 426 for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) 427 count += adreno_gpu->registers[i + 1] - 428 adreno_gpu->registers[i] + 1; 429 430 state->registers = kcalloc(count * 2, sizeof(u32), GFP_KERNEL); 431 if (state->registers) { 432 int pos = 0; 433 434 for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) { 435 u32 start = adreno_gpu->registers[i]; 436 u32 end = adreno_gpu->registers[i + 1]; 437 u32 addr; 438 439 for (addr = start; addr <= end; addr++) { 440 state->registers[pos++] = addr; 441 state->registers[pos++] = gpu_read(gpu, addr); 442 } 443 } 444 445 state->nr_registers = count; 446 } 447 448 return 0; 449 } 450 451 void adreno_gpu_state_destroy(struct msm_gpu_state *state) 452 { 453 int i; 454 455 for (i = 0; i < ARRAY_SIZE(state->ring); i++) 456 kvfree(state->ring[i].data); 457 458 for (i = 0; state->bos && i < state->nr_bos; i++) 459 kvfree(state->bos[i].data); 460 461 kfree(state->bos); 462 kfree(state->comm); 463 kfree(state->cmd); 464 kfree(state->registers); 465 } 466 467 static void adreno_gpu_state_kref_destroy(struct kref *kref) 468 { 469 struct msm_gpu_state *state = container_of(kref, 470 struct msm_gpu_state, ref); 471 472 adreno_gpu_state_destroy(state); 473 kfree(state); 474 } 475 476 int adreno_gpu_state_put(struct msm_gpu_state *state) 477 { 478 if (IS_ERR_OR_NULL(state)) 479 return 1; 480 481 return kref_put(&state->ref, adreno_gpu_state_kref_destroy); 482 } 483 484 #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP) 485 486 static char *adreno_gpu_ascii85_encode(u32 *src, size_t len) 487 { 488 void *buf; 489 size_t buf_itr = 0, buffer_size; 490 char out[ASCII85_BUFSZ]; 491 long l; 492 int i; 493 494 if (!src || !len) 495 return NULL; 496 497 l = ascii85_encode_len(len); 498 499 /* 500 * Ascii85 outputs either a 5 byte string or a 1 byte string. So we 501 * account for the worst case of 5 bytes per dword plus the 1 for '\0' 502 */ 503 buffer_size = (l * 5) + 1; 504 505 buf = kvmalloc(buffer_size, GFP_KERNEL); 506 if (!buf) 507 return NULL; 508 509 for (i = 0; i < l; i++) 510 buf_itr += snprintf(buf + buf_itr, buffer_size - buf_itr, "%s", 511 ascii85_encode(src[i], out)); 512 513 return buf; 514 } 515 516 /* len is expected to be in bytes */ 517 static void adreno_show_object(struct drm_printer *p, void **ptr, int len, 518 bool *encoded) 519 { 520 if (!*ptr || !len) 521 return; 522 523 if (!*encoded) { 524 long datalen, i; 525 u32 *buf = *ptr; 526 527 /* 528 * Only dump the non-zero part of the buffer - rarely will 529 * any data completely fill the entire allocated size of 530 * the buffer. 531 */ 532 for (datalen = 0, i = 0; i < len >> 2; i++) 533 if (buf[i]) 534 datalen = ((i + 1) << 2); 535 536 /* 537 * If we reach here, then the originally captured binary buffer 538 * will be replaced with the ascii85 encoded string 539 */ 540 *ptr = adreno_gpu_ascii85_encode(buf, datalen); 541 542 kvfree(buf); 543 544 *encoded = true; 545 } 546 547 if (!*ptr) 548 return; 549 550 drm_puts(p, " data: !!ascii85 |\n"); 551 drm_puts(p, " "); 552 553 drm_puts(p, *ptr); 554 555 drm_puts(p, "\n"); 556 } 557 558 void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state, 559 struct drm_printer *p) 560 { 561 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 562 int i; 563 564 if (IS_ERR_OR_NULL(state)) 565 return; 566 567 drm_printf(p, "revision: %d (%d.%d.%d.%d)\n", 568 adreno_gpu->info->revn, adreno_gpu->rev.core, 569 adreno_gpu->rev.major, adreno_gpu->rev.minor, 570 adreno_gpu->rev.patchid); 571 572 drm_printf(p, "rbbm-status: 0x%08x\n", state->rbbm_status); 573 574 drm_puts(p, "ringbuffer:\n"); 575 576 for (i = 0; i < gpu->nr_rings; i++) { 577 drm_printf(p, " - id: %d\n", i); 578 drm_printf(p, " iova: 0x%016llx\n", state->ring[i].iova); 579 drm_printf(p, " last-fence: %d\n", state->ring[i].seqno); 580 drm_printf(p, " retired-fence: %d\n", state->ring[i].fence); 581 drm_printf(p, " rptr: %d\n", state->ring[i].rptr); 582 drm_printf(p, " wptr: %d\n", state->ring[i].wptr); 583 drm_printf(p, " size: %d\n", MSM_GPU_RINGBUFFER_SZ); 584 585 adreno_show_object(p, &state->ring[i].data, 586 state->ring[i].data_size, &state->ring[i].encoded); 587 } 588 589 if (state->bos) { 590 drm_puts(p, "bos:\n"); 591 592 for (i = 0; i < state->nr_bos; i++) { 593 drm_printf(p, " - iova: 0x%016llx\n", 594 state->bos[i].iova); 595 drm_printf(p, " size: %zd\n", state->bos[i].size); 596 597 adreno_show_object(p, &state->bos[i].data, 598 state->bos[i].size, &state->bos[i].encoded); 599 } 600 } 601 602 if (state->nr_registers) { 603 drm_puts(p, "registers:\n"); 604 605 for (i = 0; i < state->nr_registers; i++) { 606 drm_printf(p, " - { offset: 0x%04x, value: 0x%08x }\n", 607 state->registers[i * 2] << 2, 608 state->registers[(i * 2) + 1]); 609 } 610 } 611 } 612 #endif 613 614 /* Dump common gpu status and scratch registers on any hang, to make 615 * the hangcheck logs more useful. The scratch registers seem always 616 * safe to read when GPU has hung (unlike some other regs, depending 617 * on how the GPU hung), and they are useful to match up to cmdstream 618 * dumps when debugging hangs: 619 */ 620 void adreno_dump_info(struct msm_gpu *gpu) 621 { 622 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 623 int i; 624 625 printk("revision: %d (%d.%d.%d.%d)\n", 626 adreno_gpu->info->revn, adreno_gpu->rev.core, 627 adreno_gpu->rev.major, adreno_gpu->rev.minor, 628 adreno_gpu->rev.patchid); 629 630 for (i = 0; i < gpu->nr_rings; i++) { 631 struct msm_ringbuffer *ring = gpu->rb[i]; 632 633 printk("rb %d: fence: %d/%d\n", i, 634 ring->memptrs->fence, 635 ring->seqno); 636 637 printk("rptr: %d\n", get_rptr(adreno_gpu, ring)); 638 printk("rb wptr: %d\n", get_wptr(ring)); 639 } 640 } 641 642 /* would be nice to not have to duplicate the _show() stuff with printk(): */ 643 void adreno_dump(struct msm_gpu *gpu) 644 { 645 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 646 int i; 647 648 if (!adreno_gpu->registers) 649 return; 650 651 /* dump these out in a form that can be parsed by demsm: */ 652 printk("IO:region %s 00000000 00020000\n", gpu->name); 653 for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) { 654 uint32_t start = adreno_gpu->registers[i]; 655 uint32_t end = adreno_gpu->registers[i+1]; 656 uint32_t addr; 657 658 for (addr = start; addr <= end; addr++) { 659 uint32_t val = gpu_read(gpu, addr); 660 printk("IO:R %08x %08x\n", addr<<2, val); 661 } 662 } 663 } 664 665 static uint32_t ring_freewords(struct msm_ringbuffer *ring) 666 { 667 struct adreno_gpu *adreno_gpu = to_adreno_gpu(ring->gpu); 668 uint32_t size = MSM_GPU_RINGBUFFER_SZ >> 2; 669 /* Use ring->next to calculate free size */ 670 uint32_t wptr = ring->next - ring->start; 671 uint32_t rptr = get_rptr(adreno_gpu, ring); 672 return (rptr + (size - 1) - wptr) % size; 673 } 674 675 void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords) 676 { 677 if (spin_until(ring_freewords(ring) >= ndwords)) 678 DRM_DEV_ERROR(ring->gpu->dev->dev, 679 "timeout waiting for space in ringbuffer %d\n", 680 ring->id); 681 } 682 683 /* Get legacy powerlevels from qcom,gpu-pwrlevels and populate the opp table */ 684 static int adreno_get_legacy_pwrlevels(struct device *dev) 685 { 686 struct device_node *child, *node; 687 int ret; 688 689 node = of_get_compatible_child(dev->of_node, "qcom,gpu-pwrlevels"); 690 if (!node) { 691 DRM_DEV_ERROR(dev, "Could not find the GPU powerlevels\n"); 692 return -ENXIO; 693 } 694 695 for_each_child_of_node(node, child) { 696 unsigned int val; 697 698 ret = of_property_read_u32(child, "qcom,gpu-freq", &val); 699 if (ret) 700 continue; 701 702 /* 703 * Skip the intentionally bogus clock value found at the bottom 704 * of most legacy frequency tables 705 */ 706 if (val != 27000000) 707 dev_pm_opp_add(dev, val, 0); 708 } 709 710 of_node_put(node); 711 712 return 0; 713 } 714 715 static int adreno_get_pwrlevels(struct device *dev, 716 struct msm_gpu *gpu) 717 { 718 unsigned long freq = ULONG_MAX; 719 struct dev_pm_opp *opp; 720 int ret; 721 722 gpu->fast_rate = 0; 723 724 /* You down with OPP? */ 725 if (!of_find_property(dev->of_node, "operating-points-v2", NULL)) 726 ret = adreno_get_legacy_pwrlevels(dev); 727 else { 728 ret = dev_pm_opp_of_add_table(dev); 729 if (ret) 730 DRM_DEV_ERROR(dev, "Unable to set the OPP table\n"); 731 } 732 733 if (!ret) { 734 /* Find the fastest defined rate */ 735 opp = dev_pm_opp_find_freq_floor(dev, &freq); 736 if (!IS_ERR(opp)) { 737 gpu->fast_rate = freq; 738 dev_pm_opp_put(opp); 739 } 740 } 741 742 if (!gpu->fast_rate) { 743 dev_warn(dev, 744 "Could not find a clock rate. Using a reasonable default\n"); 745 /* Pick a suitably safe clock speed for any target */ 746 gpu->fast_rate = 200000000; 747 } 748 749 DBG("fast_rate=%u, slow_rate=27000000", gpu->fast_rate); 750 751 /* Check for an interconnect path for the bus */ 752 gpu->icc_path = of_icc_get(dev, NULL); 753 if (IS_ERR(gpu->icc_path)) 754 gpu->icc_path = NULL; 755 756 return 0; 757 } 758 759 int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, 760 struct adreno_gpu *adreno_gpu, 761 const struct adreno_gpu_funcs *funcs, int nr_rings) 762 { 763 struct adreno_platform_config *config = pdev->dev.platform_data; 764 struct msm_gpu_config adreno_gpu_config = { 0 }; 765 struct msm_gpu *gpu = &adreno_gpu->base; 766 767 adreno_gpu->funcs = funcs; 768 adreno_gpu->info = adreno_info(config->rev); 769 adreno_gpu->gmem = adreno_gpu->info->gmem; 770 adreno_gpu->revn = adreno_gpu->info->revn; 771 adreno_gpu->rev = config->rev; 772 773 adreno_gpu_config.ioname = "kgsl_3d0_reg_memory"; 774 775 adreno_gpu_config.va_start = SZ_16M; 776 adreno_gpu_config.va_end = 0xffffffff; 777 /* maximum range of a2xx mmu */ 778 if (adreno_is_a2xx(adreno_gpu)) 779 adreno_gpu_config.va_end = SZ_16M + 0xfff * SZ_64K; 780 781 adreno_gpu_config.nr_rings = nr_rings; 782 783 adreno_get_pwrlevels(&pdev->dev, gpu); 784 785 pm_runtime_set_autosuspend_delay(&pdev->dev, 786 adreno_gpu->info->inactive_period); 787 pm_runtime_use_autosuspend(&pdev->dev); 788 pm_runtime_enable(&pdev->dev); 789 790 return msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base, 791 adreno_gpu->info->name, &adreno_gpu_config); 792 } 793 794 void adreno_gpu_cleanup(struct adreno_gpu *adreno_gpu) 795 { 796 struct msm_gpu *gpu = &adreno_gpu->base; 797 unsigned int i; 798 799 for (i = 0; i < ARRAY_SIZE(adreno_gpu->info->fw); i++) 800 release_firmware(adreno_gpu->fw[i]); 801 802 icc_put(gpu->icc_path); 803 804 msm_gpu_cleanup(&adreno_gpu->base); 805 } 806