1 /* 2 * Copyright (C) 2013 Red Hat 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License version 2 as published by 9 * the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include <linux/ascii85.h> 21 #include <linux/interconnect.h> 22 #include <linux/qcom_scm.h> 23 #include <linux/kernel.h> 24 #include <linux/of_address.h> 25 #include <linux/pm_opp.h> 26 #include <linux/slab.h> 27 #include <linux/soc/qcom/mdt_loader.h> 28 #include "adreno_gpu.h" 29 #include "msm_gem.h" 30 #include "msm_mmu.h" 31 32 static bool zap_available = true; 33 34 static int zap_shader_load_mdt(struct msm_gpu *gpu, const char *fwname, 35 u32 pasid) 36 { 37 struct device *dev = &gpu->pdev->dev; 38 const struct firmware *fw; 39 struct device_node *np, *mem_np; 40 struct resource r; 41 phys_addr_t mem_phys; 42 ssize_t mem_size; 43 void *mem_region = NULL; 44 int ret; 45 46 if (!IS_ENABLED(CONFIG_ARCH_QCOM)) { 47 zap_available = false; 48 return -EINVAL; 49 } 50 51 np = of_get_child_by_name(dev->of_node, "zap-shader"); 52 if (!np) { 53 zap_available = false; 54 return -ENODEV; 55 } 56 57 mem_np = of_parse_phandle(np, "memory-region", 0); 58 of_node_put(np); 59 if (!mem_np) { 60 zap_available = false; 61 return -EINVAL; 62 } 63 64 ret = of_address_to_resource(mem_np, 0, &r); 65 of_node_put(mem_np); 66 if (ret) 67 return ret; 68 69 mem_phys = r.start; 70 mem_size = resource_size(&r); 71 72 /* Request the MDT file for the firmware */ 73 fw = adreno_request_fw(to_adreno_gpu(gpu), fwname); 74 if (IS_ERR(fw)) { 75 DRM_DEV_ERROR(dev, "Unable to load %s\n", fwname); 76 return PTR_ERR(fw); 77 } 78 79 /* Figure out how much memory we need */ 80 mem_size = qcom_mdt_get_size(fw); 81 if (mem_size < 0) { 82 ret = mem_size; 83 goto out; 84 } 85 86 /* Allocate memory for the firmware image */ 87 mem_region = memremap(mem_phys, mem_size, MEMREMAP_WC); 88 if (!mem_region) { 89 ret = -ENOMEM; 90 goto out; 91 } 92 93 /* 94 * Load the rest of the MDT 95 * 96 * Note that we could be dealing with two different paths, since 97 * with upstream linux-firmware it would be in a qcom/ subdir.. 98 * adreno_request_fw() handles this, but qcom_mdt_load() does 99 * not. But since we've already gotten through adreno_request_fw() 100 * we know which of the two cases it is: 101 */ 102 if (to_adreno_gpu(gpu)->fwloc == FW_LOCATION_LEGACY) { 103 ret = qcom_mdt_load(dev, fw, fwname, pasid, 104 mem_region, mem_phys, mem_size, NULL); 105 } else { 106 char *newname; 107 108 newname = kasprintf(GFP_KERNEL, "qcom/%s", fwname); 109 110 ret = qcom_mdt_load(dev, fw, newname, pasid, 111 mem_region, mem_phys, mem_size, NULL); 112 kfree(newname); 113 } 114 if (ret) 115 goto out; 116 117 /* Send the image to the secure world */ 118 ret = qcom_scm_pas_auth_and_reset(pasid); 119 120 /* 121 * If the scm call returns -EOPNOTSUPP we assume that this target 122 * doesn't need/support the zap shader so quietly fail 123 */ 124 if (ret == -EOPNOTSUPP) 125 zap_available = false; 126 else if (ret) 127 DRM_DEV_ERROR(dev, "Unable to authorize the image\n"); 128 129 out: 130 if (mem_region) 131 memunmap(mem_region); 132 133 release_firmware(fw); 134 135 return ret; 136 } 137 138 int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid) 139 { 140 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 141 struct platform_device *pdev = gpu->pdev; 142 143 /* Short cut if we determine the zap shader isn't available/needed */ 144 if (!zap_available) 145 return -ENODEV; 146 147 /* We need SCM to be able to load the firmware */ 148 if (!qcom_scm_is_available()) { 149 DRM_DEV_ERROR(&pdev->dev, "SCM is not available\n"); 150 return -EPROBE_DEFER; 151 } 152 153 /* Each GPU has a target specific zap shader firmware name to use */ 154 if (!adreno_gpu->info->zapfw) { 155 zap_available = false; 156 DRM_DEV_ERROR(&pdev->dev, 157 "Zap shader firmware file not specified for this target\n"); 158 return -ENODEV; 159 } 160 161 return zap_shader_load_mdt(gpu, adreno_gpu->info->zapfw, pasid); 162 } 163 164 int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value) 165 { 166 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 167 168 switch (param) { 169 case MSM_PARAM_GPU_ID: 170 *value = adreno_gpu->info->revn; 171 return 0; 172 case MSM_PARAM_GMEM_SIZE: 173 *value = adreno_gpu->gmem; 174 return 0; 175 case MSM_PARAM_GMEM_BASE: 176 *value = 0x100000; 177 return 0; 178 case MSM_PARAM_CHIP_ID: 179 *value = adreno_gpu->rev.patchid | 180 (adreno_gpu->rev.minor << 8) | 181 (adreno_gpu->rev.major << 16) | 182 (adreno_gpu->rev.core << 24); 183 return 0; 184 case MSM_PARAM_MAX_FREQ: 185 *value = adreno_gpu->base.fast_rate; 186 return 0; 187 case MSM_PARAM_TIMESTAMP: 188 if (adreno_gpu->funcs->get_timestamp) { 189 int ret; 190 191 pm_runtime_get_sync(&gpu->pdev->dev); 192 ret = adreno_gpu->funcs->get_timestamp(gpu, value); 193 pm_runtime_put_autosuspend(&gpu->pdev->dev); 194 195 return ret; 196 } 197 return -EINVAL; 198 case MSM_PARAM_NR_RINGS: 199 *value = gpu->nr_rings; 200 return 0; 201 case MSM_PARAM_PP_PGTABLE: 202 *value = 0; 203 return 0; 204 case MSM_PARAM_FAULTS: 205 *value = gpu->global_faults; 206 return 0; 207 default: 208 DBG("%s: invalid param: %u", gpu->name, param); 209 return -EINVAL; 210 } 211 } 212 213 const struct firmware * 214 adreno_request_fw(struct adreno_gpu *adreno_gpu, const char *fwname) 215 { 216 struct drm_device *drm = adreno_gpu->base.dev; 217 const struct firmware *fw = NULL; 218 char *newname; 219 int ret; 220 221 newname = kasprintf(GFP_KERNEL, "qcom/%s", fwname); 222 if (!newname) 223 return ERR_PTR(-ENOMEM); 224 225 /* 226 * Try first to load from qcom/$fwfile using a direct load (to avoid 227 * a potential timeout waiting for usermode helper) 228 */ 229 if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) || 230 (adreno_gpu->fwloc == FW_LOCATION_NEW)) { 231 232 ret = request_firmware_direct(&fw, newname, drm->dev); 233 if (!ret) { 234 DRM_DEV_INFO(drm->dev, "loaded %s from new location\n", 235 newname); 236 adreno_gpu->fwloc = FW_LOCATION_NEW; 237 goto out; 238 } else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) { 239 DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n", 240 newname, ret); 241 fw = ERR_PTR(ret); 242 goto out; 243 } 244 } 245 246 /* 247 * Then try the legacy location without qcom/ prefix 248 */ 249 if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) || 250 (adreno_gpu->fwloc == FW_LOCATION_LEGACY)) { 251 252 ret = request_firmware_direct(&fw, fwname, drm->dev); 253 if (!ret) { 254 DRM_DEV_INFO(drm->dev, "loaded %s from legacy location\n", 255 newname); 256 adreno_gpu->fwloc = FW_LOCATION_LEGACY; 257 goto out; 258 } else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) { 259 DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n", 260 fwname, ret); 261 fw = ERR_PTR(ret); 262 goto out; 263 } 264 } 265 266 /* 267 * Finally fall back to request_firmware() for cases where the 268 * usermode helper is needed (I think mainly android) 269 */ 270 if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) || 271 (adreno_gpu->fwloc == FW_LOCATION_HELPER)) { 272 273 ret = request_firmware(&fw, newname, drm->dev); 274 if (!ret) { 275 DRM_DEV_INFO(drm->dev, "loaded %s with helper\n", 276 newname); 277 adreno_gpu->fwloc = FW_LOCATION_HELPER; 278 goto out; 279 } else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) { 280 DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n", 281 newname, ret); 282 fw = ERR_PTR(ret); 283 goto out; 284 } 285 } 286 287 DRM_DEV_ERROR(drm->dev, "failed to load %s\n", fwname); 288 fw = ERR_PTR(-ENOENT); 289 out: 290 kfree(newname); 291 return fw; 292 } 293 294 int adreno_load_fw(struct adreno_gpu *adreno_gpu) 295 { 296 int i; 297 298 for (i = 0; i < ARRAY_SIZE(adreno_gpu->info->fw); i++) { 299 const struct firmware *fw; 300 301 if (!adreno_gpu->info->fw[i]) 302 continue; 303 304 /* Skip if the firmware has already been loaded */ 305 if (adreno_gpu->fw[i]) 306 continue; 307 308 fw = adreno_request_fw(adreno_gpu, adreno_gpu->info->fw[i]); 309 if (IS_ERR(fw)) 310 return PTR_ERR(fw); 311 312 adreno_gpu->fw[i] = fw; 313 } 314 315 return 0; 316 } 317 318 struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu, 319 const struct firmware *fw, u64 *iova) 320 { 321 struct drm_gem_object *bo; 322 void *ptr; 323 324 ptr = msm_gem_kernel_new_locked(gpu->dev, fw->size - 4, 325 MSM_BO_UNCACHED | MSM_BO_GPU_READONLY, gpu->aspace, &bo, iova); 326 327 if (IS_ERR(ptr)) 328 return ERR_CAST(ptr); 329 330 memcpy(ptr, &fw->data[4], fw->size - 4); 331 332 msm_gem_put_vaddr(bo); 333 334 return bo; 335 } 336 337 int adreno_hw_init(struct msm_gpu *gpu) 338 { 339 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 340 int ret, i; 341 342 DBG("%s", gpu->name); 343 344 ret = adreno_load_fw(adreno_gpu); 345 if (ret) 346 return ret; 347 348 for (i = 0; i < gpu->nr_rings; i++) { 349 struct msm_ringbuffer *ring = gpu->rb[i]; 350 351 if (!ring) 352 continue; 353 354 ring->cur = ring->start; 355 ring->next = ring->start; 356 357 /* reset completed fence seqno: */ 358 ring->memptrs->fence = ring->seqno; 359 ring->memptrs->rptr = 0; 360 } 361 362 /* 363 * Setup REG_CP_RB_CNTL. The same value is used across targets (with 364 * the excpetion of A430 that disables the RPTR shadow) - the cacluation 365 * for the ringbuffer size and block size is moved to msm_gpu.h for the 366 * pre-processor to deal with and the A430 variant is ORed in here 367 */ 368 adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_CNTL, 369 MSM_GPU_RB_CNTL_DEFAULT | 370 (adreno_is_a430(adreno_gpu) ? AXXX_CP_RB_CNTL_NO_UPDATE : 0)); 371 372 /* Setup ringbuffer address - use ringbuffer[0] for GPU init */ 373 adreno_gpu_write64(adreno_gpu, REG_ADRENO_CP_RB_BASE, 374 REG_ADRENO_CP_RB_BASE_HI, gpu->rb[0]->iova); 375 376 if (!adreno_is_a430(adreno_gpu)) { 377 adreno_gpu_write64(adreno_gpu, REG_ADRENO_CP_RB_RPTR_ADDR, 378 REG_ADRENO_CP_RB_RPTR_ADDR_HI, 379 rbmemptr(gpu->rb[0], rptr)); 380 } 381 382 return 0; 383 } 384 385 /* Use this helper to read rptr, since a430 doesn't update rptr in memory */ 386 static uint32_t get_rptr(struct adreno_gpu *adreno_gpu, 387 struct msm_ringbuffer *ring) 388 { 389 if (adreno_is_a430(adreno_gpu)) 390 return ring->memptrs->rptr = adreno_gpu_read( 391 adreno_gpu, REG_ADRENO_CP_RB_RPTR); 392 else 393 return ring->memptrs->rptr; 394 } 395 396 struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu) 397 { 398 return gpu->rb[0]; 399 } 400 401 void adreno_recover(struct msm_gpu *gpu) 402 { 403 struct drm_device *dev = gpu->dev; 404 int ret; 405 406 // XXX pm-runtime?? we *need* the device to be off after this 407 // so maybe continuing to call ->pm_suspend/resume() is better? 408 409 gpu->funcs->pm_suspend(gpu); 410 gpu->funcs->pm_resume(gpu); 411 412 ret = msm_gpu_hw_init(gpu); 413 if (ret) { 414 DRM_DEV_ERROR(dev->dev, "gpu hw init failed: %d\n", ret); 415 /* hmm, oh well? */ 416 } 417 } 418 419 void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, 420 struct msm_file_private *ctx) 421 { 422 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 423 struct msm_drm_private *priv = gpu->dev->dev_private; 424 struct msm_ringbuffer *ring = submit->ring; 425 unsigned i; 426 427 for (i = 0; i < submit->nr_cmds; i++) { 428 switch (submit->cmd[i].type) { 429 case MSM_SUBMIT_CMD_IB_TARGET_BUF: 430 /* ignore IB-targets */ 431 break; 432 case MSM_SUBMIT_CMD_CTX_RESTORE_BUF: 433 /* ignore if there has not been a ctx switch: */ 434 if (priv->lastctx == ctx) 435 break; 436 case MSM_SUBMIT_CMD_BUF: 437 OUT_PKT3(ring, adreno_is_a430(adreno_gpu) ? 438 CP_INDIRECT_BUFFER_PFE : CP_INDIRECT_BUFFER_PFD, 2); 439 OUT_RING(ring, lower_32_bits(submit->cmd[i].iova)); 440 OUT_RING(ring, submit->cmd[i].size); 441 OUT_PKT2(ring); 442 break; 443 } 444 } 445 446 OUT_PKT0(ring, REG_AXXX_CP_SCRATCH_REG2, 1); 447 OUT_RING(ring, submit->seqno); 448 449 if (adreno_is_a3xx(adreno_gpu) || adreno_is_a4xx(adreno_gpu)) { 450 /* Flush HLSQ lazy updates to make sure there is nothing 451 * pending for indirect loads after the timestamp has 452 * passed: 453 */ 454 OUT_PKT3(ring, CP_EVENT_WRITE, 1); 455 OUT_RING(ring, HLSQ_FLUSH); 456 } 457 458 /* wait for idle before cache flush/interrupt */ 459 OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1); 460 OUT_RING(ring, 0x00000000); 461 462 if (!adreno_is_a2xx(adreno_gpu)) { 463 /* BIT(31) of CACHE_FLUSH_TS triggers CACHE_FLUSH_TS IRQ from GPU */ 464 OUT_PKT3(ring, CP_EVENT_WRITE, 3); 465 OUT_RING(ring, CACHE_FLUSH_TS | BIT(31)); 466 OUT_RING(ring, rbmemptr(ring, fence)); 467 OUT_RING(ring, submit->seqno); 468 } else { 469 /* BIT(31) means something else on a2xx */ 470 OUT_PKT3(ring, CP_EVENT_WRITE, 3); 471 OUT_RING(ring, CACHE_FLUSH_TS); 472 OUT_RING(ring, rbmemptr(ring, fence)); 473 OUT_RING(ring, submit->seqno); 474 OUT_PKT3(ring, CP_INTERRUPT, 1); 475 OUT_RING(ring, 0x80000000); 476 } 477 478 #if 0 479 if (adreno_is_a3xx(adreno_gpu)) { 480 /* Dummy set-constant to trigger context rollover */ 481 OUT_PKT3(ring, CP_SET_CONSTANT, 2); 482 OUT_RING(ring, CP_REG(REG_A3XX_HLSQ_CL_KERNEL_GROUP_X_REG)); 483 OUT_RING(ring, 0x00000000); 484 } 485 #endif 486 487 gpu->funcs->flush(gpu, ring); 488 } 489 490 void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 491 { 492 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 493 uint32_t wptr; 494 495 /* Copy the shadow to the actual register */ 496 ring->cur = ring->next; 497 498 /* 499 * Mask wptr value that we calculate to fit in the HW range. This is 500 * to account for the possibility that the last command fit exactly into 501 * the ringbuffer and rb->next hasn't wrapped to zero yet 502 */ 503 wptr = get_wptr(ring); 504 505 /* ensure writes to ringbuffer have hit system memory: */ 506 mb(); 507 508 adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_WPTR, wptr); 509 } 510 511 bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 512 { 513 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 514 uint32_t wptr = get_wptr(ring); 515 516 /* wait for CP to drain ringbuffer: */ 517 if (!spin_until(get_rptr(adreno_gpu, ring) == wptr)) 518 return true; 519 520 /* TODO maybe we need to reset GPU here to recover from hang? */ 521 DRM_ERROR("%s: timeout waiting to drain ringbuffer %d rptr/wptr = %X/%X\n", 522 gpu->name, ring->id, get_rptr(adreno_gpu, ring), wptr); 523 524 return false; 525 } 526 527 int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state) 528 { 529 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 530 int i, count = 0; 531 532 kref_init(&state->ref); 533 534 ktime_get_real_ts64(&state->time); 535 536 for (i = 0; i < gpu->nr_rings; i++) { 537 int size = 0, j; 538 539 state->ring[i].fence = gpu->rb[i]->memptrs->fence; 540 state->ring[i].iova = gpu->rb[i]->iova; 541 state->ring[i].seqno = gpu->rb[i]->seqno; 542 state->ring[i].rptr = get_rptr(adreno_gpu, gpu->rb[i]); 543 state->ring[i].wptr = get_wptr(gpu->rb[i]); 544 545 /* Copy at least 'wptr' dwords of the data */ 546 size = state->ring[i].wptr; 547 548 /* After wptr find the last non zero dword to save space */ 549 for (j = state->ring[i].wptr; j < MSM_GPU_RINGBUFFER_SZ >> 2; j++) 550 if (gpu->rb[i]->start[j]) 551 size = j + 1; 552 553 if (size) { 554 state->ring[i].data = kvmalloc(size << 2, GFP_KERNEL); 555 if (state->ring[i].data) { 556 memcpy(state->ring[i].data, gpu->rb[i]->start, size << 2); 557 state->ring[i].data_size = size << 2; 558 } 559 } 560 } 561 562 /* Some targets prefer to collect their own registers */ 563 if (!adreno_gpu->registers) 564 return 0; 565 566 /* Count the number of registers */ 567 for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) 568 count += adreno_gpu->registers[i + 1] - 569 adreno_gpu->registers[i] + 1; 570 571 state->registers = kcalloc(count * 2, sizeof(u32), GFP_KERNEL); 572 if (state->registers) { 573 int pos = 0; 574 575 for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) { 576 u32 start = adreno_gpu->registers[i]; 577 u32 end = adreno_gpu->registers[i + 1]; 578 u32 addr; 579 580 for (addr = start; addr <= end; addr++) { 581 state->registers[pos++] = addr; 582 state->registers[pos++] = gpu_read(gpu, addr); 583 } 584 } 585 586 state->nr_registers = count; 587 } 588 589 return 0; 590 } 591 592 void adreno_gpu_state_destroy(struct msm_gpu_state *state) 593 { 594 int i; 595 596 for (i = 0; i < ARRAY_SIZE(state->ring); i++) 597 kvfree(state->ring[i].data); 598 599 for (i = 0; state->bos && i < state->nr_bos; i++) 600 kvfree(state->bos[i].data); 601 602 kfree(state->bos); 603 kfree(state->comm); 604 kfree(state->cmd); 605 kfree(state->registers); 606 } 607 608 static void adreno_gpu_state_kref_destroy(struct kref *kref) 609 { 610 struct msm_gpu_state *state = container_of(kref, 611 struct msm_gpu_state, ref); 612 613 adreno_gpu_state_destroy(state); 614 kfree(state); 615 } 616 617 int adreno_gpu_state_put(struct msm_gpu_state *state) 618 { 619 if (IS_ERR_OR_NULL(state)) 620 return 1; 621 622 return kref_put(&state->ref, adreno_gpu_state_kref_destroy); 623 } 624 625 #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP) 626 627 static char *adreno_gpu_ascii85_encode(u32 *src, size_t len) 628 { 629 void *buf; 630 size_t buf_itr = 0, buffer_size; 631 char out[ASCII85_BUFSZ]; 632 long l; 633 int i; 634 635 if (!src || !len) 636 return NULL; 637 638 l = ascii85_encode_len(len); 639 640 /* 641 * Ascii85 outputs either a 5 byte string or a 1 byte string. So we 642 * account for the worst case of 5 bytes per dword plus the 1 for '\0' 643 */ 644 buffer_size = (l * 5) + 1; 645 646 buf = kvmalloc(buffer_size, GFP_KERNEL); 647 if (!buf) 648 return NULL; 649 650 for (i = 0; i < l; i++) 651 buf_itr += snprintf(buf + buf_itr, buffer_size - buf_itr, "%s", 652 ascii85_encode(src[i], out)); 653 654 return buf; 655 } 656 657 /* len is expected to be in bytes */ 658 static void adreno_show_object(struct drm_printer *p, void **ptr, int len, 659 bool *encoded) 660 { 661 if (!*ptr || !len) 662 return; 663 664 if (!*encoded) { 665 long datalen, i; 666 u32 *buf = *ptr; 667 668 /* 669 * Only dump the non-zero part of the buffer - rarely will 670 * any data completely fill the entire allocated size of 671 * the buffer. 672 */ 673 for (datalen = 0, i = 0; i < len >> 2; i++) 674 if (buf[i]) 675 datalen = ((i + 1) << 2); 676 677 /* 678 * If we reach here, then the originally captured binary buffer 679 * will be replaced with the ascii85 encoded string 680 */ 681 *ptr = adreno_gpu_ascii85_encode(buf, datalen); 682 683 kvfree(buf); 684 685 *encoded = true; 686 } 687 688 if (!*ptr) 689 return; 690 691 drm_puts(p, " data: !!ascii85 |\n"); 692 drm_puts(p, " "); 693 694 drm_puts(p, *ptr); 695 696 drm_puts(p, "\n"); 697 } 698 699 void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state, 700 struct drm_printer *p) 701 { 702 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 703 int i; 704 705 if (IS_ERR_OR_NULL(state)) 706 return; 707 708 drm_printf(p, "revision: %d (%d.%d.%d.%d)\n", 709 adreno_gpu->info->revn, adreno_gpu->rev.core, 710 adreno_gpu->rev.major, adreno_gpu->rev.minor, 711 adreno_gpu->rev.patchid); 712 713 drm_printf(p, "rbbm-status: 0x%08x\n", state->rbbm_status); 714 715 drm_puts(p, "ringbuffer:\n"); 716 717 for (i = 0; i < gpu->nr_rings; i++) { 718 drm_printf(p, " - id: %d\n", i); 719 drm_printf(p, " iova: 0x%016llx\n", state->ring[i].iova); 720 drm_printf(p, " last-fence: %d\n", state->ring[i].seqno); 721 drm_printf(p, " retired-fence: %d\n", state->ring[i].fence); 722 drm_printf(p, " rptr: %d\n", state->ring[i].rptr); 723 drm_printf(p, " wptr: %d\n", state->ring[i].wptr); 724 drm_printf(p, " size: %d\n", MSM_GPU_RINGBUFFER_SZ); 725 726 adreno_show_object(p, &state->ring[i].data, 727 state->ring[i].data_size, &state->ring[i].encoded); 728 } 729 730 if (state->bos) { 731 drm_puts(p, "bos:\n"); 732 733 for (i = 0; i < state->nr_bos; i++) { 734 drm_printf(p, " - iova: 0x%016llx\n", 735 state->bos[i].iova); 736 drm_printf(p, " size: %zd\n", state->bos[i].size); 737 738 adreno_show_object(p, &state->bos[i].data, 739 state->bos[i].size, &state->bos[i].encoded); 740 } 741 } 742 743 if (state->nr_registers) { 744 drm_puts(p, "registers:\n"); 745 746 for (i = 0; i < state->nr_registers; i++) { 747 drm_printf(p, " - { offset: 0x%04x, value: 0x%08x }\n", 748 state->registers[i * 2] << 2, 749 state->registers[(i * 2) + 1]); 750 } 751 } 752 } 753 #endif 754 755 /* Dump common gpu status and scratch registers on any hang, to make 756 * the hangcheck logs more useful. The scratch registers seem always 757 * safe to read when GPU has hung (unlike some other regs, depending 758 * on how the GPU hung), and they are useful to match up to cmdstream 759 * dumps when debugging hangs: 760 */ 761 void adreno_dump_info(struct msm_gpu *gpu) 762 { 763 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 764 int i; 765 766 printk("revision: %d (%d.%d.%d.%d)\n", 767 adreno_gpu->info->revn, adreno_gpu->rev.core, 768 adreno_gpu->rev.major, adreno_gpu->rev.minor, 769 adreno_gpu->rev.patchid); 770 771 for (i = 0; i < gpu->nr_rings; i++) { 772 struct msm_ringbuffer *ring = gpu->rb[i]; 773 774 printk("rb %d: fence: %d/%d\n", i, 775 ring->memptrs->fence, 776 ring->seqno); 777 778 printk("rptr: %d\n", get_rptr(adreno_gpu, ring)); 779 printk("rb wptr: %d\n", get_wptr(ring)); 780 } 781 } 782 783 /* would be nice to not have to duplicate the _show() stuff with printk(): */ 784 void adreno_dump(struct msm_gpu *gpu) 785 { 786 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 787 int i; 788 789 if (!adreno_gpu->registers) 790 return; 791 792 /* dump these out in a form that can be parsed by demsm: */ 793 printk("IO:region %s 00000000 00020000\n", gpu->name); 794 for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) { 795 uint32_t start = adreno_gpu->registers[i]; 796 uint32_t end = adreno_gpu->registers[i+1]; 797 uint32_t addr; 798 799 for (addr = start; addr <= end; addr++) { 800 uint32_t val = gpu_read(gpu, addr); 801 printk("IO:R %08x %08x\n", addr<<2, val); 802 } 803 } 804 } 805 806 static uint32_t ring_freewords(struct msm_ringbuffer *ring) 807 { 808 struct adreno_gpu *adreno_gpu = to_adreno_gpu(ring->gpu); 809 uint32_t size = MSM_GPU_RINGBUFFER_SZ >> 2; 810 /* Use ring->next to calculate free size */ 811 uint32_t wptr = ring->next - ring->start; 812 uint32_t rptr = get_rptr(adreno_gpu, ring); 813 return (rptr + (size - 1) - wptr) % size; 814 } 815 816 void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords) 817 { 818 if (spin_until(ring_freewords(ring) >= ndwords)) 819 DRM_DEV_ERROR(ring->gpu->dev->dev, 820 "timeout waiting for space in ringbuffer %d\n", 821 ring->id); 822 } 823 824 /* Get legacy powerlevels from qcom,gpu-pwrlevels and populate the opp table */ 825 static int adreno_get_legacy_pwrlevels(struct device *dev) 826 { 827 struct device_node *child, *node; 828 int ret; 829 830 node = of_get_compatible_child(dev->of_node, "qcom,gpu-pwrlevels"); 831 if (!node) { 832 DRM_DEV_ERROR(dev, "Could not find the GPU powerlevels\n"); 833 return -ENXIO; 834 } 835 836 for_each_child_of_node(node, child) { 837 unsigned int val; 838 839 ret = of_property_read_u32(child, "qcom,gpu-freq", &val); 840 if (ret) 841 continue; 842 843 /* 844 * Skip the intentionally bogus clock value found at the bottom 845 * of most legacy frequency tables 846 */ 847 if (val != 27000000) 848 dev_pm_opp_add(dev, val, 0); 849 } 850 851 of_node_put(node); 852 853 return 0; 854 } 855 856 static int adreno_get_pwrlevels(struct device *dev, 857 struct msm_gpu *gpu) 858 { 859 unsigned long freq = ULONG_MAX; 860 struct dev_pm_opp *opp; 861 int ret; 862 863 gpu->fast_rate = 0; 864 865 /* You down with OPP? */ 866 if (!of_find_property(dev->of_node, "operating-points-v2", NULL)) 867 ret = adreno_get_legacy_pwrlevels(dev); 868 else { 869 ret = dev_pm_opp_of_add_table(dev); 870 if (ret) 871 DRM_DEV_ERROR(dev, "Unable to set the OPP table\n"); 872 } 873 874 if (!ret) { 875 /* Find the fastest defined rate */ 876 opp = dev_pm_opp_find_freq_floor(dev, &freq); 877 if (!IS_ERR(opp)) { 878 gpu->fast_rate = freq; 879 dev_pm_opp_put(opp); 880 } 881 } 882 883 if (!gpu->fast_rate) { 884 dev_warn(dev, 885 "Could not find a clock rate. Using a reasonable default\n"); 886 /* Pick a suitably safe clock speed for any target */ 887 gpu->fast_rate = 200000000; 888 } 889 890 DBG("fast_rate=%u, slow_rate=27000000", gpu->fast_rate); 891 892 /* Check for an interconnect path for the bus */ 893 gpu->icc_path = of_icc_get(dev, NULL); 894 if (IS_ERR(gpu->icc_path)) 895 gpu->icc_path = NULL; 896 897 return 0; 898 } 899 900 int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, 901 struct adreno_gpu *adreno_gpu, 902 const struct adreno_gpu_funcs *funcs, int nr_rings) 903 { 904 struct adreno_platform_config *config = pdev->dev.platform_data; 905 struct msm_gpu_config adreno_gpu_config = { 0 }; 906 struct msm_gpu *gpu = &adreno_gpu->base; 907 908 adreno_gpu->funcs = funcs; 909 adreno_gpu->info = adreno_info(config->rev); 910 adreno_gpu->gmem = adreno_gpu->info->gmem; 911 adreno_gpu->revn = adreno_gpu->info->revn; 912 adreno_gpu->rev = config->rev; 913 914 adreno_gpu_config.ioname = "kgsl_3d0_reg_memory"; 915 916 adreno_gpu_config.va_start = SZ_16M; 917 adreno_gpu_config.va_end = 0xffffffff; 918 /* maximum range of a2xx mmu */ 919 if (adreno_is_a2xx(adreno_gpu)) 920 adreno_gpu_config.va_end = SZ_16M + 0xfff * SZ_64K; 921 922 adreno_gpu_config.nr_rings = nr_rings; 923 924 adreno_get_pwrlevels(&pdev->dev, gpu); 925 926 pm_runtime_set_autosuspend_delay(&pdev->dev, 927 adreno_gpu->info->inactive_period); 928 pm_runtime_use_autosuspend(&pdev->dev); 929 pm_runtime_enable(&pdev->dev); 930 931 return msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base, 932 adreno_gpu->info->name, &adreno_gpu_config); 933 } 934 935 void adreno_gpu_cleanup(struct adreno_gpu *adreno_gpu) 936 { 937 struct msm_gpu *gpu = &adreno_gpu->base; 938 unsigned int i; 939 940 for (i = 0; i < ARRAY_SIZE(adreno_gpu->info->fw); i++) 941 release_firmware(adreno_gpu->fw[i]); 942 943 icc_put(gpu->icc_path); 944 945 msm_gpu_cleanup(&adreno_gpu->base); 946 } 947