1 /*
2  * Copyright (C) 2013 Red Hat
3  * Author: Rob Clark <robdclark@gmail.com>
4  *
5  * Copyright (c) 2014 The Linux Foundation. All rights reserved.
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms of the GNU General Public License version 2 as published by
9  * the Free Software Foundation.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along with
17  * this program.  If not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #include "adreno_gpu.h"
21 #include "msm_gem.h"
22 #include "msm_mmu.h"
23 
24 #define RB_SIZE    SZ_32K
25 #define RB_BLKSIZE 16
26 
27 int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value)
28 {
29 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
30 
31 	switch (param) {
32 	case MSM_PARAM_GPU_ID:
33 		*value = adreno_gpu->info->revn;
34 		return 0;
35 	case MSM_PARAM_GMEM_SIZE:
36 		*value = adreno_gpu->gmem;
37 		return 0;
38 	case MSM_PARAM_CHIP_ID:
39 		*value = adreno_gpu->rev.patchid |
40 				(adreno_gpu->rev.minor << 8) |
41 				(adreno_gpu->rev.major << 16) |
42 				(adreno_gpu->rev.core << 24);
43 		return 0;
44 	case MSM_PARAM_MAX_FREQ:
45 		*value = adreno_gpu->base.fast_rate;
46 		return 0;
47 	case MSM_PARAM_TIMESTAMP:
48 		if (adreno_gpu->funcs->get_timestamp)
49 			return adreno_gpu->funcs->get_timestamp(gpu, value);
50 		return -EINVAL;
51 	default:
52 		DBG("%s: invalid param: %u", gpu->name, param);
53 		return -EINVAL;
54 	}
55 }
56 
57 #define rbmemptr(adreno_gpu, member)  \
58 	((adreno_gpu)->memptrs_iova + offsetof(struct adreno_rbmemptrs, member))
59 
60 int adreno_hw_init(struct msm_gpu *gpu)
61 {
62 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
63 	int ret;
64 
65 	DBG("%s", gpu->name);
66 
67 	ret = msm_gem_get_iova(gpu->rb->bo, gpu->id, &gpu->rb_iova);
68 	if (ret) {
69 		gpu->rb_iova = 0;
70 		dev_err(gpu->dev->dev, "could not map ringbuffer: %d\n", ret);
71 		return ret;
72 	}
73 
74 	/* Setup REG_CP_RB_CNTL: */
75 	adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_CNTL,
76 			/* size is log2(quad-words): */
77 			AXXX_CP_RB_CNTL_BUFSZ(ilog2(gpu->rb->size / 8)) |
78 			AXXX_CP_RB_CNTL_BLKSZ(ilog2(RB_BLKSIZE / 8)) |
79 			(adreno_is_a430(adreno_gpu) ? AXXX_CP_RB_CNTL_NO_UPDATE : 0));
80 
81 	/* Setup ringbuffer address: */
82 	adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_BASE, gpu->rb_iova);
83 
84 	if (!adreno_is_a430(adreno_gpu))
85 		adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_RPTR_ADDR,
86 						rbmemptr(adreno_gpu, rptr));
87 
88 	return 0;
89 }
90 
91 static uint32_t get_wptr(struct msm_ringbuffer *ring)
92 {
93 	return ring->cur - ring->start;
94 }
95 
96 /* Use this helper to read rptr, since a430 doesn't update rptr in memory */
97 static uint32_t get_rptr(struct adreno_gpu *adreno_gpu)
98 {
99 	if (adreno_is_a430(adreno_gpu))
100 		return adreno_gpu->memptrs->rptr = adreno_gpu_read(
101 			adreno_gpu, REG_ADRENO_CP_RB_RPTR);
102 	else
103 		return adreno_gpu->memptrs->rptr;
104 }
105 
106 uint32_t adreno_last_fence(struct msm_gpu *gpu)
107 {
108 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
109 	return adreno_gpu->memptrs->fence;
110 }
111 
112 void adreno_recover(struct msm_gpu *gpu)
113 {
114 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
115 	struct drm_device *dev = gpu->dev;
116 	int ret;
117 
118 	gpu->funcs->pm_suspend(gpu);
119 
120 	/* reset ringbuffer: */
121 	gpu->rb->cur = gpu->rb->start;
122 
123 	/* reset completed fence seqno: */
124 	adreno_gpu->memptrs->fence = gpu->fctx->completed_fence;
125 	adreno_gpu->memptrs->rptr  = 0;
126 	adreno_gpu->memptrs->wptr  = 0;
127 
128 	gpu->funcs->pm_resume(gpu);
129 	ret = gpu->funcs->hw_init(gpu);
130 	if (ret) {
131 		dev_err(dev->dev, "gpu hw init failed: %d\n", ret);
132 		/* hmm, oh well? */
133 	}
134 }
135 
136 void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
137 		struct msm_file_private *ctx)
138 {
139 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
140 	struct msm_drm_private *priv = gpu->dev->dev_private;
141 	struct msm_ringbuffer *ring = gpu->rb;
142 	unsigned i;
143 
144 	for (i = 0; i < submit->nr_cmds; i++) {
145 		switch (submit->cmd[i].type) {
146 		case MSM_SUBMIT_CMD_IB_TARGET_BUF:
147 			/* ignore IB-targets */
148 			break;
149 		case MSM_SUBMIT_CMD_CTX_RESTORE_BUF:
150 			/* ignore if there has not been a ctx switch: */
151 			if (priv->lastctx == ctx)
152 				break;
153 		case MSM_SUBMIT_CMD_BUF:
154 			OUT_PKT3(ring, adreno_is_a430(adreno_gpu) ?
155 				CP_INDIRECT_BUFFER_PFE : CP_INDIRECT_BUFFER_PFD, 2);
156 			OUT_RING(ring, submit->cmd[i].iova);
157 			OUT_RING(ring, submit->cmd[i].size);
158 			OUT_PKT2(ring);
159 			break;
160 		}
161 	}
162 
163 	OUT_PKT0(ring, REG_AXXX_CP_SCRATCH_REG2, 1);
164 	OUT_RING(ring, submit->fence->seqno);
165 
166 	if (adreno_is_a3xx(adreno_gpu) || adreno_is_a4xx(adreno_gpu)) {
167 		/* Flush HLSQ lazy updates to make sure there is nothing
168 		 * pending for indirect loads after the timestamp has
169 		 * passed:
170 		 */
171 		OUT_PKT3(ring, CP_EVENT_WRITE, 1);
172 		OUT_RING(ring, HLSQ_FLUSH);
173 
174 		OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1);
175 		OUT_RING(ring, 0x00000000);
176 	}
177 
178 	OUT_PKT3(ring, CP_EVENT_WRITE, 3);
179 	OUT_RING(ring, CACHE_FLUSH_TS);
180 	OUT_RING(ring, rbmemptr(adreno_gpu, fence));
181 	OUT_RING(ring, submit->fence->seqno);
182 
183 	/* we could maybe be clever and only CP_COND_EXEC the interrupt: */
184 	OUT_PKT3(ring, CP_INTERRUPT, 1);
185 	OUT_RING(ring, 0x80000000);
186 
187 	/* Workaround for missing irq issue on 8x16/a306.  Unsure if the
188 	 * root cause is a platform issue or some a306 quirk, but this
189 	 * keeps things humming along:
190 	 */
191 	if (adreno_is_a306(adreno_gpu)) {
192 		OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1);
193 		OUT_RING(ring, 0x00000000);
194 		OUT_PKT3(ring, CP_INTERRUPT, 1);
195 		OUT_RING(ring, 0x80000000);
196 	}
197 
198 #if 0
199 	if (adreno_is_a3xx(adreno_gpu)) {
200 		/* Dummy set-constant to trigger context rollover */
201 		OUT_PKT3(ring, CP_SET_CONSTANT, 2);
202 		OUT_RING(ring, CP_REG(REG_A3XX_HLSQ_CL_KERNEL_GROUP_X_REG));
203 		OUT_RING(ring, 0x00000000);
204 	}
205 #endif
206 
207 	gpu->funcs->flush(gpu);
208 }
209 
210 void adreno_flush(struct msm_gpu *gpu)
211 {
212 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
213 	uint32_t wptr = get_wptr(gpu->rb);
214 
215 	/* ensure writes to ringbuffer have hit system memory: */
216 	mb();
217 
218 	adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_WPTR, wptr);
219 }
220 
221 void adreno_idle(struct msm_gpu *gpu)
222 {
223 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
224 	uint32_t wptr = get_wptr(gpu->rb);
225 	int ret;
226 
227 	/* wait for CP to drain ringbuffer: */
228 	ret = spin_until(get_rptr(adreno_gpu) == wptr);
229 
230 	if (ret)
231 		DRM_ERROR("%s: timeout waiting to drain ringbuffer!\n", gpu->name);
232 
233 	/* TODO maybe we need to reset GPU here to recover from hang? */
234 }
235 
236 #ifdef CONFIG_DEBUG_FS
237 void adreno_show(struct msm_gpu *gpu, struct seq_file *m)
238 {
239 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
240 	int i;
241 
242 	seq_printf(m, "revision: %d (%d.%d.%d.%d)\n",
243 			adreno_gpu->info->revn, adreno_gpu->rev.core,
244 			adreno_gpu->rev.major, adreno_gpu->rev.minor,
245 			adreno_gpu->rev.patchid);
246 
247 	seq_printf(m, "fence:    %d/%d\n", adreno_gpu->memptrs->fence,
248 			gpu->fctx->last_fence);
249 	seq_printf(m, "rptr:     %d\n", get_rptr(adreno_gpu));
250 	seq_printf(m, "wptr:     %d\n", adreno_gpu->memptrs->wptr);
251 	seq_printf(m, "rb wptr:  %d\n", get_wptr(gpu->rb));
252 
253 	gpu->funcs->pm_resume(gpu);
254 
255 	/* dump these out in a form that can be parsed by demsm: */
256 	seq_printf(m, "IO:region %s 00000000 00020000\n", gpu->name);
257 	for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) {
258 		uint32_t start = adreno_gpu->registers[i];
259 		uint32_t end   = adreno_gpu->registers[i+1];
260 		uint32_t addr;
261 
262 		for (addr = start; addr <= end; addr++) {
263 			uint32_t val = gpu_read(gpu, addr);
264 			seq_printf(m, "IO:R %08x %08x\n", addr<<2, val);
265 		}
266 	}
267 
268 	gpu->funcs->pm_suspend(gpu);
269 }
270 #endif
271 
272 /* Dump common gpu status and scratch registers on any hang, to make
273  * the hangcheck logs more useful.  The scratch registers seem always
274  * safe to read when GPU has hung (unlike some other regs, depending
275  * on how the GPU hung), and they are useful to match up to cmdstream
276  * dumps when debugging hangs:
277  */
278 void adreno_dump_info(struct msm_gpu *gpu)
279 {
280 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
281 	int i;
282 
283 	printk("revision: %d (%d.%d.%d.%d)\n",
284 			adreno_gpu->info->revn, adreno_gpu->rev.core,
285 			adreno_gpu->rev.major, adreno_gpu->rev.minor,
286 			adreno_gpu->rev.patchid);
287 
288 	printk("fence:    %d/%d\n", adreno_gpu->memptrs->fence,
289 			gpu->fctx->last_fence);
290 	printk("rptr:     %d\n", get_rptr(adreno_gpu));
291 	printk("wptr:     %d\n", adreno_gpu->memptrs->wptr);
292 	printk("rb wptr:  %d\n", get_wptr(gpu->rb));
293 
294 	for (i = 0; i < 8; i++) {
295 		printk("CP_SCRATCH_REG%d: %u\n", i,
296 			gpu_read(gpu, REG_AXXX_CP_SCRATCH_REG0 + i));
297 	}
298 }
299 
300 /* would be nice to not have to duplicate the _show() stuff with printk(): */
301 void adreno_dump(struct msm_gpu *gpu)
302 {
303 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
304 	int i;
305 
306 	/* dump these out in a form that can be parsed by demsm: */
307 	printk("IO:region %s 00000000 00020000\n", gpu->name);
308 	for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) {
309 		uint32_t start = adreno_gpu->registers[i];
310 		uint32_t end   = adreno_gpu->registers[i+1];
311 		uint32_t addr;
312 
313 		for (addr = start; addr <= end; addr++) {
314 			uint32_t val = gpu_read(gpu, addr);
315 			printk("IO:R %08x %08x\n", addr<<2, val);
316 		}
317 	}
318 }
319 
320 static uint32_t ring_freewords(struct msm_gpu *gpu)
321 {
322 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
323 	uint32_t size = gpu->rb->size / 4;
324 	uint32_t wptr = get_wptr(gpu->rb);
325 	uint32_t rptr = get_rptr(adreno_gpu);
326 	return (rptr + (size - 1) - wptr) % size;
327 }
328 
329 void adreno_wait_ring(struct msm_gpu *gpu, uint32_t ndwords)
330 {
331 	if (spin_until(ring_freewords(gpu) >= ndwords))
332 		DRM_ERROR("%s: timeout waiting for ringbuffer space\n", gpu->name);
333 }
334 
335 static const char *iommu_ports[] = {
336 		"gfx3d_user", "gfx3d_priv",
337 		"gfx3d1_user", "gfx3d1_priv",
338 };
339 
340 int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
341 		struct adreno_gpu *adreno_gpu, const struct adreno_gpu_funcs *funcs)
342 {
343 	struct adreno_platform_config *config = pdev->dev.platform_data;
344 	struct msm_gpu *gpu = &adreno_gpu->base;
345 	struct msm_mmu *mmu;
346 	int ret;
347 
348 	adreno_gpu->funcs = funcs;
349 	adreno_gpu->info = adreno_info(config->rev);
350 	adreno_gpu->gmem = adreno_gpu->info->gmem;
351 	adreno_gpu->revn = adreno_gpu->info->revn;
352 	adreno_gpu->rev = config->rev;
353 
354 	gpu->fast_rate = config->fast_rate;
355 	gpu->slow_rate = config->slow_rate;
356 	gpu->bus_freq  = config->bus_freq;
357 #ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
358 	gpu->bus_scale_table = config->bus_scale_table;
359 #endif
360 
361 	DBG("fast_rate=%u, slow_rate=%u, bus_freq=%u",
362 			gpu->fast_rate, gpu->slow_rate, gpu->bus_freq);
363 
364 	ret = msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base,
365 			adreno_gpu->info->name, "kgsl_3d0_reg_memory", "kgsl_3d0_irq",
366 			RB_SIZE);
367 	if (ret)
368 		return ret;
369 
370 	ret = request_firmware(&adreno_gpu->pm4, adreno_gpu->info->pm4fw, drm->dev);
371 	if (ret) {
372 		dev_err(drm->dev, "failed to load %s PM4 firmware: %d\n",
373 				adreno_gpu->info->pm4fw, ret);
374 		return ret;
375 	}
376 
377 	ret = request_firmware(&adreno_gpu->pfp, adreno_gpu->info->pfpfw, drm->dev);
378 	if (ret) {
379 		dev_err(drm->dev, "failed to load %s PFP firmware: %d\n",
380 				adreno_gpu->info->pfpfw, ret);
381 		return ret;
382 	}
383 
384 	mmu = gpu->mmu;
385 	if (mmu) {
386 		ret = mmu->funcs->attach(mmu, iommu_ports,
387 				ARRAY_SIZE(iommu_ports));
388 		if (ret)
389 			return ret;
390 	}
391 
392 	mutex_lock(&drm->struct_mutex);
393 	adreno_gpu->memptrs_bo = msm_gem_new(drm, sizeof(*adreno_gpu->memptrs),
394 			MSM_BO_UNCACHED);
395 	mutex_unlock(&drm->struct_mutex);
396 	if (IS_ERR(adreno_gpu->memptrs_bo)) {
397 		ret = PTR_ERR(adreno_gpu->memptrs_bo);
398 		adreno_gpu->memptrs_bo = NULL;
399 		dev_err(drm->dev, "could not allocate memptrs: %d\n", ret);
400 		return ret;
401 	}
402 
403 	adreno_gpu->memptrs = msm_gem_get_vaddr(adreno_gpu->memptrs_bo);
404 	if (IS_ERR(adreno_gpu->memptrs)) {
405 		dev_err(drm->dev, "could not vmap memptrs\n");
406 		return -ENOMEM;
407 	}
408 
409 	ret = msm_gem_get_iova(adreno_gpu->memptrs_bo, gpu->id,
410 			&adreno_gpu->memptrs_iova);
411 	if (ret) {
412 		dev_err(drm->dev, "could not map memptrs: %d\n", ret);
413 		return ret;
414 	}
415 
416 	return 0;
417 }
418 
419 void adreno_gpu_cleanup(struct adreno_gpu *gpu)
420 {
421 	if (gpu->memptrs_bo) {
422 		if (gpu->memptrs)
423 			msm_gem_put_vaddr(gpu->memptrs_bo);
424 
425 		if (gpu->memptrs_iova)
426 			msm_gem_put_iova(gpu->memptrs_bo, gpu->base.id);
427 
428 		drm_gem_object_unreference_unlocked(gpu->memptrs_bo);
429 	}
430 	release_firmware(gpu->pm4);
431 	release_firmware(gpu->pfp);
432 	msm_gpu_cleanup(&gpu->base);
433 }
434