1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 Red Hat 4 * Author: Rob Clark <robdclark@gmail.com> 5 * 6 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 7 */ 8 9 #include <linux/ascii85.h> 10 #include <linux/interconnect.h> 11 #include <linux/qcom_scm.h> 12 #include <linux/kernel.h> 13 #include <linux/of_address.h> 14 #include <linux/pm_opp.h> 15 #include <linux/slab.h> 16 #include <linux/soc/qcom/mdt_loader.h> 17 #include <soc/qcom/ocmem.h> 18 #include "adreno_gpu.h" 19 #include "a6xx_gpu.h" 20 #include "msm_gem.h" 21 #include "msm_mmu.h" 22 23 static bool zap_available = true; 24 25 static int zap_shader_load_mdt(struct msm_gpu *gpu, const char *fwname, 26 u32 pasid) 27 { 28 struct device *dev = &gpu->pdev->dev; 29 const struct firmware *fw; 30 const char *signed_fwname = NULL; 31 struct device_node *np, *mem_np; 32 struct resource r; 33 phys_addr_t mem_phys; 34 ssize_t mem_size; 35 void *mem_region = NULL; 36 int ret; 37 38 if (!IS_ENABLED(CONFIG_ARCH_QCOM)) { 39 zap_available = false; 40 return -EINVAL; 41 } 42 43 np = of_get_child_by_name(dev->of_node, "zap-shader"); 44 if (!np) { 45 zap_available = false; 46 return -ENODEV; 47 } 48 49 mem_np = of_parse_phandle(np, "memory-region", 0); 50 of_node_put(np); 51 if (!mem_np) { 52 zap_available = false; 53 return -EINVAL; 54 } 55 56 ret = of_address_to_resource(mem_np, 0, &r); 57 of_node_put(mem_np); 58 if (ret) 59 return ret; 60 61 mem_phys = r.start; 62 63 /* 64 * Check for a firmware-name property. This is the new scheme 65 * to handle firmware that may be signed with device specific 66 * keys, allowing us to have a different zap fw path for different 67 * devices. 68 * 69 * If the firmware-name property is found, we bypass the 70 * adreno_request_fw() mechanism, because we don't need to handle 71 * the /lib/firmware/qcom/... vs /lib/firmware/... case. 72 * 73 * If the firmware-name property is not found, for backwards 74 * compatibility we fall back to the fwname from the gpulist 75 * table. 76 */ 77 of_property_read_string_index(np, "firmware-name", 0, &signed_fwname); 78 if (signed_fwname) { 79 fwname = signed_fwname; 80 ret = request_firmware_direct(&fw, fwname, gpu->dev->dev); 81 if (ret) 82 fw = ERR_PTR(ret); 83 } else if (fwname) { 84 /* Request the MDT file from the default location: */ 85 fw = adreno_request_fw(to_adreno_gpu(gpu), fwname); 86 } else { 87 /* 88 * For new targets, we require the firmware-name property, 89 * if a zap-shader is required, rather than falling back 90 * to a firmware name specified in gpulist. 91 * 92 * Because the firmware is signed with a (potentially) 93 * device specific key, having the name come from gpulist 94 * was a bad idea, and is only provided for backwards 95 * compatibility for older targets. 96 */ 97 return -ENODEV; 98 } 99 100 if (IS_ERR(fw)) { 101 DRM_DEV_ERROR(dev, "Unable to load %s\n", fwname); 102 return PTR_ERR(fw); 103 } 104 105 /* Figure out how much memory we need */ 106 mem_size = qcom_mdt_get_size(fw); 107 if (mem_size < 0) { 108 ret = mem_size; 109 goto out; 110 } 111 112 if (mem_size > resource_size(&r)) { 113 DRM_DEV_ERROR(dev, 114 "memory region is too small to load the MDT\n"); 115 ret = -E2BIG; 116 goto out; 117 } 118 119 /* Allocate memory for the firmware image */ 120 mem_region = memremap(mem_phys, mem_size, MEMREMAP_WC); 121 if (!mem_region) { 122 ret = -ENOMEM; 123 goto out; 124 } 125 126 /* 127 * Load the rest of the MDT 128 * 129 * Note that we could be dealing with two different paths, since 130 * with upstream linux-firmware it would be in a qcom/ subdir.. 131 * adreno_request_fw() handles this, but qcom_mdt_load() does 132 * not. But since we've already gotten through adreno_request_fw() 133 * we know which of the two cases it is: 134 */ 135 if (signed_fwname || (to_adreno_gpu(gpu)->fwloc == FW_LOCATION_LEGACY)) { 136 ret = qcom_mdt_load(dev, fw, fwname, pasid, 137 mem_region, mem_phys, mem_size, NULL); 138 } else { 139 char *newname; 140 141 newname = kasprintf(GFP_KERNEL, "qcom/%s", fwname); 142 143 ret = qcom_mdt_load(dev, fw, newname, pasid, 144 mem_region, mem_phys, mem_size, NULL); 145 kfree(newname); 146 } 147 if (ret) 148 goto out; 149 150 /* Send the image to the secure world */ 151 ret = qcom_scm_pas_auth_and_reset(pasid); 152 153 /* 154 * If the scm call returns -EOPNOTSUPP we assume that this target 155 * doesn't need/support the zap shader so quietly fail 156 */ 157 if (ret == -EOPNOTSUPP) 158 zap_available = false; 159 else if (ret) 160 DRM_DEV_ERROR(dev, "Unable to authorize the image\n"); 161 162 out: 163 if (mem_region) 164 memunmap(mem_region); 165 166 release_firmware(fw); 167 168 return ret; 169 } 170 171 int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid) 172 { 173 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 174 struct platform_device *pdev = gpu->pdev; 175 176 /* Short cut if we determine the zap shader isn't available/needed */ 177 if (!zap_available) 178 return -ENODEV; 179 180 /* We need SCM to be able to load the firmware */ 181 if (!qcom_scm_is_available()) { 182 DRM_DEV_ERROR(&pdev->dev, "SCM is not available\n"); 183 return -EPROBE_DEFER; 184 } 185 186 return zap_shader_load_mdt(gpu, adreno_gpu->info->zapfw, pasid); 187 } 188 189 struct msm_gem_address_space * 190 adreno_iommu_create_address_space(struct msm_gpu *gpu, 191 struct platform_device *pdev) 192 { 193 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 194 struct iommu_domain *iommu; 195 struct msm_mmu *mmu; 196 struct msm_gem_address_space *aspace; 197 u64 start, size; 198 199 iommu = iommu_domain_alloc(&platform_bus_type); 200 if (!iommu) 201 return NULL; 202 203 204 if (adreno_is_a6xx(adreno_gpu)) { 205 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 206 struct io_pgtable_domain_attr pgtbl_cfg; 207 /* 208 * This allows GPU to set the bus attributes required to use system 209 * cache on behalf of the iommu page table walker. 210 */ 211 if (!IS_ERR(a6xx_gpu->htw_llc_slice)) { 212 pgtbl_cfg.quirks = IO_PGTABLE_QUIRK_ARM_OUTER_WBWA; 213 iommu_domain_set_attr(iommu, DOMAIN_ATTR_IO_PGTABLE_CFG, &pgtbl_cfg); 214 } 215 } 216 217 mmu = msm_iommu_new(&pdev->dev, iommu); 218 if (IS_ERR(mmu)) { 219 iommu_domain_free(iommu); 220 return ERR_CAST(mmu); 221 } 222 223 /* 224 * Use the aperture start or SZ_16M, whichever is greater. This will 225 * ensure that we align with the allocated pagetable range while still 226 * allowing room in the lower 32 bits for GMEM and whatnot 227 */ 228 start = max_t(u64, SZ_16M, iommu->geometry.aperture_start); 229 size = iommu->geometry.aperture_end - start + 1; 230 231 aspace = msm_gem_address_space_create(mmu, "gpu", 232 start & GENMASK_ULL(48, 0), size); 233 234 if (IS_ERR(aspace) && !IS_ERR(mmu)) 235 mmu->funcs->destroy(mmu); 236 237 return aspace; 238 } 239 240 int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value) 241 { 242 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 243 244 switch (param) { 245 case MSM_PARAM_GPU_ID: 246 *value = adreno_gpu->info->revn; 247 return 0; 248 case MSM_PARAM_GMEM_SIZE: 249 *value = adreno_gpu->gmem; 250 return 0; 251 case MSM_PARAM_GMEM_BASE: 252 *value = !adreno_is_a650(adreno_gpu) ? 0x100000 : 0; 253 return 0; 254 case MSM_PARAM_CHIP_ID: 255 *value = adreno_gpu->rev.patchid | 256 (adreno_gpu->rev.minor << 8) | 257 (adreno_gpu->rev.major << 16) | 258 (adreno_gpu->rev.core << 24); 259 return 0; 260 case MSM_PARAM_MAX_FREQ: 261 *value = adreno_gpu->base.fast_rate; 262 return 0; 263 case MSM_PARAM_TIMESTAMP: 264 if (adreno_gpu->funcs->get_timestamp) { 265 int ret; 266 267 pm_runtime_get_sync(&gpu->pdev->dev); 268 ret = adreno_gpu->funcs->get_timestamp(gpu, value); 269 pm_runtime_put_autosuspend(&gpu->pdev->dev); 270 271 return ret; 272 } 273 return -EINVAL; 274 case MSM_PARAM_NR_RINGS: 275 *value = gpu->nr_rings; 276 return 0; 277 case MSM_PARAM_PP_PGTABLE: 278 *value = 0; 279 return 0; 280 case MSM_PARAM_FAULTS: 281 *value = gpu->global_faults; 282 return 0; 283 default: 284 DBG("%s: invalid param: %u", gpu->name, param); 285 return -EINVAL; 286 } 287 } 288 289 const struct firmware * 290 adreno_request_fw(struct adreno_gpu *adreno_gpu, const char *fwname) 291 { 292 struct drm_device *drm = adreno_gpu->base.dev; 293 const struct firmware *fw = NULL; 294 char *newname; 295 int ret; 296 297 newname = kasprintf(GFP_KERNEL, "qcom/%s", fwname); 298 if (!newname) 299 return ERR_PTR(-ENOMEM); 300 301 /* 302 * Try first to load from qcom/$fwfile using a direct load (to avoid 303 * a potential timeout waiting for usermode helper) 304 */ 305 if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) || 306 (adreno_gpu->fwloc == FW_LOCATION_NEW)) { 307 308 ret = request_firmware_direct(&fw, newname, drm->dev); 309 if (!ret) { 310 DRM_DEV_INFO(drm->dev, "loaded %s from new location\n", 311 newname); 312 adreno_gpu->fwloc = FW_LOCATION_NEW; 313 goto out; 314 } else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) { 315 DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n", 316 newname, ret); 317 fw = ERR_PTR(ret); 318 goto out; 319 } 320 } 321 322 /* 323 * Then try the legacy location without qcom/ prefix 324 */ 325 if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) || 326 (adreno_gpu->fwloc == FW_LOCATION_LEGACY)) { 327 328 ret = request_firmware_direct(&fw, fwname, drm->dev); 329 if (!ret) { 330 DRM_DEV_INFO(drm->dev, "loaded %s from legacy location\n", 331 newname); 332 adreno_gpu->fwloc = FW_LOCATION_LEGACY; 333 goto out; 334 } else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) { 335 DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n", 336 fwname, ret); 337 fw = ERR_PTR(ret); 338 goto out; 339 } 340 } 341 342 /* 343 * Finally fall back to request_firmware() for cases where the 344 * usermode helper is needed (I think mainly android) 345 */ 346 if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) || 347 (adreno_gpu->fwloc == FW_LOCATION_HELPER)) { 348 349 ret = request_firmware(&fw, newname, drm->dev); 350 if (!ret) { 351 DRM_DEV_INFO(drm->dev, "loaded %s with helper\n", 352 newname); 353 adreno_gpu->fwloc = FW_LOCATION_HELPER; 354 goto out; 355 } else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) { 356 DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n", 357 newname, ret); 358 fw = ERR_PTR(ret); 359 goto out; 360 } 361 } 362 363 DRM_DEV_ERROR(drm->dev, "failed to load %s\n", fwname); 364 fw = ERR_PTR(-ENOENT); 365 out: 366 kfree(newname); 367 return fw; 368 } 369 370 int adreno_load_fw(struct adreno_gpu *adreno_gpu) 371 { 372 int i; 373 374 for (i = 0; i < ARRAY_SIZE(adreno_gpu->info->fw); i++) { 375 const struct firmware *fw; 376 377 if (!adreno_gpu->info->fw[i]) 378 continue; 379 380 /* Skip if the firmware has already been loaded */ 381 if (adreno_gpu->fw[i]) 382 continue; 383 384 fw = adreno_request_fw(adreno_gpu, adreno_gpu->info->fw[i]); 385 if (IS_ERR(fw)) 386 return PTR_ERR(fw); 387 388 adreno_gpu->fw[i] = fw; 389 } 390 391 return 0; 392 } 393 394 struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu, 395 const struct firmware *fw, u64 *iova) 396 { 397 struct drm_gem_object *bo; 398 void *ptr; 399 400 ptr = msm_gem_kernel_new_locked(gpu->dev, fw->size - 4, 401 MSM_BO_UNCACHED | MSM_BO_GPU_READONLY, gpu->aspace, &bo, iova); 402 403 if (IS_ERR(ptr)) 404 return ERR_CAST(ptr); 405 406 memcpy(ptr, &fw->data[4], fw->size - 4); 407 408 msm_gem_put_vaddr(bo); 409 410 return bo; 411 } 412 413 int adreno_hw_init(struct msm_gpu *gpu) 414 { 415 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 416 int ret, i; 417 418 DBG("%s", gpu->name); 419 420 ret = adreno_load_fw(adreno_gpu); 421 if (ret) 422 return ret; 423 424 for (i = 0; i < gpu->nr_rings; i++) { 425 struct msm_ringbuffer *ring = gpu->rb[i]; 426 427 if (!ring) 428 continue; 429 430 ring->cur = ring->start; 431 ring->next = ring->start; 432 433 /* reset completed fence seqno: */ 434 ring->memptrs->fence = ring->fctx->completed_fence; 435 ring->memptrs->rptr = 0; 436 } 437 438 return 0; 439 } 440 441 /* Use this helper to read rptr, since a430 doesn't update rptr in memory */ 442 static uint32_t get_rptr(struct adreno_gpu *adreno_gpu, 443 struct msm_ringbuffer *ring) 444 { 445 struct msm_gpu *gpu = &adreno_gpu->base; 446 447 return gpu->funcs->get_rptr(gpu, ring); 448 } 449 450 struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu) 451 { 452 return gpu->rb[0]; 453 } 454 455 void adreno_recover(struct msm_gpu *gpu) 456 { 457 struct drm_device *dev = gpu->dev; 458 int ret; 459 460 // XXX pm-runtime?? we *need* the device to be off after this 461 // so maybe continuing to call ->pm_suspend/resume() is better? 462 463 gpu->funcs->pm_suspend(gpu); 464 gpu->funcs->pm_resume(gpu); 465 466 ret = msm_gpu_hw_init(gpu); 467 if (ret) { 468 DRM_DEV_ERROR(dev->dev, "gpu hw init failed: %d\n", ret); 469 /* hmm, oh well? */ 470 } 471 } 472 473 void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, u32 reg) 474 { 475 uint32_t wptr; 476 477 /* Copy the shadow to the actual register */ 478 ring->cur = ring->next; 479 480 /* 481 * Mask wptr value that we calculate to fit in the HW range. This is 482 * to account for the possibility that the last command fit exactly into 483 * the ringbuffer and rb->next hasn't wrapped to zero yet 484 */ 485 wptr = get_wptr(ring); 486 487 /* ensure writes to ringbuffer have hit system memory: */ 488 mb(); 489 490 gpu_write(gpu, reg, wptr); 491 } 492 493 bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 494 { 495 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 496 uint32_t wptr = get_wptr(ring); 497 498 /* wait for CP to drain ringbuffer: */ 499 if (!spin_until(get_rptr(adreno_gpu, ring) == wptr)) 500 return true; 501 502 /* TODO maybe we need to reset GPU here to recover from hang? */ 503 DRM_ERROR("%s: timeout waiting to drain ringbuffer %d rptr/wptr = %X/%X\n", 504 gpu->name, ring->id, get_rptr(adreno_gpu, ring), wptr); 505 506 return false; 507 } 508 509 int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state) 510 { 511 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 512 int i, count = 0; 513 514 kref_init(&state->ref); 515 516 ktime_get_real_ts64(&state->time); 517 518 for (i = 0; i < gpu->nr_rings; i++) { 519 int size = 0, j; 520 521 state->ring[i].fence = gpu->rb[i]->memptrs->fence; 522 state->ring[i].iova = gpu->rb[i]->iova; 523 state->ring[i].seqno = gpu->rb[i]->seqno; 524 state->ring[i].rptr = get_rptr(adreno_gpu, gpu->rb[i]); 525 state->ring[i].wptr = get_wptr(gpu->rb[i]); 526 527 /* Copy at least 'wptr' dwords of the data */ 528 size = state->ring[i].wptr; 529 530 /* After wptr find the last non zero dword to save space */ 531 for (j = state->ring[i].wptr; j < MSM_GPU_RINGBUFFER_SZ >> 2; j++) 532 if (gpu->rb[i]->start[j]) 533 size = j + 1; 534 535 if (size) { 536 state->ring[i].data = kvmalloc(size << 2, GFP_KERNEL); 537 if (state->ring[i].data) { 538 memcpy(state->ring[i].data, gpu->rb[i]->start, size << 2); 539 state->ring[i].data_size = size << 2; 540 } 541 } 542 } 543 544 /* Some targets prefer to collect their own registers */ 545 if (!adreno_gpu->registers) 546 return 0; 547 548 /* Count the number of registers */ 549 for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) 550 count += adreno_gpu->registers[i + 1] - 551 adreno_gpu->registers[i] + 1; 552 553 state->registers = kcalloc(count * 2, sizeof(u32), GFP_KERNEL); 554 if (state->registers) { 555 int pos = 0; 556 557 for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) { 558 u32 start = adreno_gpu->registers[i]; 559 u32 end = adreno_gpu->registers[i + 1]; 560 u32 addr; 561 562 for (addr = start; addr <= end; addr++) { 563 state->registers[pos++] = addr; 564 state->registers[pos++] = gpu_read(gpu, addr); 565 } 566 } 567 568 state->nr_registers = count; 569 } 570 571 return 0; 572 } 573 574 void adreno_gpu_state_destroy(struct msm_gpu_state *state) 575 { 576 int i; 577 578 for (i = 0; i < ARRAY_SIZE(state->ring); i++) 579 kvfree(state->ring[i].data); 580 581 for (i = 0; state->bos && i < state->nr_bos; i++) 582 kvfree(state->bos[i].data); 583 584 kfree(state->bos); 585 kfree(state->comm); 586 kfree(state->cmd); 587 kfree(state->registers); 588 } 589 590 static void adreno_gpu_state_kref_destroy(struct kref *kref) 591 { 592 struct msm_gpu_state *state = container_of(kref, 593 struct msm_gpu_state, ref); 594 595 adreno_gpu_state_destroy(state); 596 kfree(state); 597 } 598 599 int adreno_gpu_state_put(struct msm_gpu_state *state) 600 { 601 if (IS_ERR_OR_NULL(state)) 602 return 1; 603 604 return kref_put(&state->ref, adreno_gpu_state_kref_destroy); 605 } 606 607 #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP) 608 609 static char *adreno_gpu_ascii85_encode(u32 *src, size_t len) 610 { 611 void *buf; 612 size_t buf_itr = 0, buffer_size; 613 char out[ASCII85_BUFSZ]; 614 long l; 615 int i; 616 617 if (!src || !len) 618 return NULL; 619 620 l = ascii85_encode_len(len); 621 622 /* 623 * Ascii85 outputs either a 5 byte string or a 1 byte string. So we 624 * account for the worst case of 5 bytes per dword plus the 1 for '\0' 625 */ 626 buffer_size = (l * 5) + 1; 627 628 buf = kvmalloc(buffer_size, GFP_KERNEL); 629 if (!buf) 630 return NULL; 631 632 for (i = 0; i < l; i++) 633 buf_itr += scnprintf(buf + buf_itr, buffer_size - buf_itr, "%s", 634 ascii85_encode(src[i], out)); 635 636 return buf; 637 } 638 639 /* len is expected to be in bytes */ 640 static void adreno_show_object(struct drm_printer *p, void **ptr, int len, 641 bool *encoded) 642 { 643 if (!*ptr || !len) 644 return; 645 646 if (!*encoded) { 647 long datalen, i; 648 u32 *buf = *ptr; 649 650 /* 651 * Only dump the non-zero part of the buffer - rarely will 652 * any data completely fill the entire allocated size of 653 * the buffer. 654 */ 655 for (datalen = 0, i = 0; i < len >> 2; i++) 656 if (buf[i]) 657 datalen = ((i + 1) << 2); 658 659 /* 660 * If we reach here, then the originally captured binary buffer 661 * will be replaced with the ascii85 encoded string 662 */ 663 *ptr = adreno_gpu_ascii85_encode(buf, datalen); 664 665 kvfree(buf); 666 667 *encoded = true; 668 } 669 670 if (!*ptr) 671 return; 672 673 drm_puts(p, " data: !!ascii85 |\n"); 674 drm_puts(p, " "); 675 676 drm_puts(p, *ptr); 677 678 drm_puts(p, "\n"); 679 } 680 681 void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state, 682 struct drm_printer *p) 683 { 684 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 685 int i; 686 687 if (IS_ERR_OR_NULL(state)) 688 return; 689 690 drm_printf(p, "revision: %d (%d.%d.%d.%d)\n", 691 adreno_gpu->info->revn, adreno_gpu->rev.core, 692 adreno_gpu->rev.major, adreno_gpu->rev.minor, 693 adreno_gpu->rev.patchid); 694 695 drm_printf(p, "rbbm-status: 0x%08x\n", state->rbbm_status); 696 697 drm_puts(p, "ringbuffer:\n"); 698 699 for (i = 0; i < gpu->nr_rings; i++) { 700 drm_printf(p, " - id: %d\n", i); 701 drm_printf(p, " iova: 0x%016llx\n", state->ring[i].iova); 702 drm_printf(p, " last-fence: %d\n", state->ring[i].seqno); 703 drm_printf(p, " retired-fence: %d\n", state->ring[i].fence); 704 drm_printf(p, " rptr: %d\n", state->ring[i].rptr); 705 drm_printf(p, " wptr: %d\n", state->ring[i].wptr); 706 drm_printf(p, " size: %d\n", MSM_GPU_RINGBUFFER_SZ); 707 708 adreno_show_object(p, &state->ring[i].data, 709 state->ring[i].data_size, &state->ring[i].encoded); 710 } 711 712 if (state->bos) { 713 drm_puts(p, "bos:\n"); 714 715 for (i = 0; i < state->nr_bos; i++) { 716 drm_printf(p, " - iova: 0x%016llx\n", 717 state->bos[i].iova); 718 drm_printf(p, " size: %zd\n", state->bos[i].size); 719 720 adreno_show_object(p, &state->bos[i].data, 721 state->bos[i].size, &state->bos[i].encoded); 722 } 723 } 724 725 if (state->nr_registers) { 726 drm_puts(p, "registers:\n"); 727 728 for (i = 0; i < state->nr_registers; i++) { 729 drm_printf(p, " - { offset: 0x%04x, value: 0x%08x }\n", 730 state->registers[i * 2] << 2, 731 state->registers[(i * 2) + 1]); 732 } 733 } 734 } 735 #endif 736 737 /* Dump common gpu status and scratch registers on any hang, to make 738 * the hangcheck logs more useful. The scratch registers seem always 739 * safe to read when GPU has hung (unlike some other regs, depending 740 * on how the GPU hung), and they are useful to match up to cmdstream 741 * dumps when debugging hangs: 742 */ 743 void adreno_dump_info(struct msm_gpu *gpu) 744 { 745 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 746 int i; 747 748 printk("revision: %d (%d.%d.%d.%d)\n", 749 adreno_gpu->info->revn, adreno_gpu->rev.core, 750 adreno_gpu->rev.major, adreno_gpu->rev.minor, 751 adreno_gpu->rev.patchid); 752 753 for (i = 0; i < gpu->nr_rings; i++) { 754 struct msm_ringbuffer *ring = gpu->rb[i]; 755 756 printk("rb %d: fence: %d/%d\n", i, 757 ring->memptrs->fence, 758 ring->seqno); 759 760 printk("rptr: %d\n", get_rptr(adreno_gpu, ring)); 761 printk("rb wptr: %d\n", get_wptr(ring)); 762 } 763 } 764 765 /* would be nice to not have to duplicate the _show() stuff with printk(): */ 766 void adreno_dump(struct msm_gpu *gpu) 767 { 768 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 769 int i; 770 771 if (!adreno_gpu->registers) 772 return; 773 774 /* dump these out in a form that can be parsed by demsm: */ 775 printk("IO:region %s 00000000 00020000\n", gpu->name); 776 for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) { 777 uint32_t start = adreno_gpu->registers[i]; 778 uint32_t end = adreno_gpu->registers[i+1]; 779 uint32_t addr; 780 781 for (addr = start; addr <= end; addr++) { 782 uint32_t val = gpu_read(gpu, addr); 783 printk("IO:R %08x %08x\n", addr<<2, val); 784 } 785 } 786 } 787 788 static uint32_t ring_freewords(struct msm_ringbuffer *ring) 789 { 790 struct adreno_gpu *adreno_gpu = to_adreno_gpu(ring->gpu); 791 uint32_t size = MSM_GPU_RINGBUFFER_SZ >> 2; 792 /* Use ring->next to calculate free size */ 793 uint32_t wptr = ring->next - ring->start; 794 uint32_t rptr = get_rptr(adreno_gpu, ring); 795 return (rptr + (size - 1) - wptr) % size; 796 } 797 798 void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords) 799 { 800 if (spin_until(ring_freewords(ring) >= ndwords)) 801 DRM_DEV_ERROR(ring->gpu->dev->dev, 802 "timeout waiting for space in ringbuffer %d\n", 803 ring->id); 804 } 805 806 /* Get legacy powerlevels from qcom,gpu-pwrlevels and populate the opp table */ 807 static int adreno_get_legacy_pwrlevels(struct device *dev) 808 { 809 struct device_node *child, *node; 810 int ret; 811 812 node = of_get_compatible_child(dev->of_node, "qcom,gpu-pwrlevels"); 813 if (!node) { 814 DRM_DEV_DEBUG(dev, "Could not find the GPU powerlevels\n"); 815 return -ENXIO; 816 } 817 818 for_each_child_of_node(node, child) { 819 unsigned int val; 820 821 ret = of_property_read_u32(child, "qcom,gpu-freq", &val); 822 if (ret) 823 continue; 824 825 /* 826 * Skip the intentionally bogus clock value found at the bottom 827 * of most legacy frequency tables 828 */ 829 if (val != 27000000) 830 dev_pm_opp_add(dev, val, 0); 831 } 832 833 of_node_put(node); 834 835 return 0; 836 } 837 838 static void adreno_get_pwrlevels(struct device *dev, 839 struct msm_gpu *gpu) 840 { 841 unsigned long freq = ULONG_MAX; 842 struct dev_pm_opp *opp; 843 int ret; 844 845 gpu->fast_rate = 0; 846 847 /* You down with OPP? */ 848 if (!of_find_property(dev->of_node, "operating-points-v2", NULL)) 849 ret = adreno_get_legacy_pwrlevels(dev); 850 else { 851 ret = dev_pm_opp_of_add_table(dev); 852 if (ret) 853 DRM_DEV_ERROR(dev, "Unable to set the OPP table\n"); 854 } 855 856 if (!ret) { 857 /* Find the fastest defined rate */ 858 opp = dev_pm_opp_find_freq_floor(dev, &freq); 859 if (!IS_ERR(opp)) { 860 gpu->fast_rate = freq; 861 dev_pm_opp_put(opp); 862 } 863 } 864 865 if (!gpu->fast_rate) { 866 dev_warn(dev, 867 "Could not find a clock rate. Using a reasonable default\n"); 868 /* Pick a suitably safe clock speed for any target */ 869 gpu->fast_rate = 200000000; 870 } 871 872 DBG("fast_rate=%u, slow_rate=27000000", gpu->fast_rate); 873 } 874 875 int adreno_gpu_ocmem_init(struct device *dev, struct adreno_gpu *adreno_gpu, 876 struct adreno_ocmem *adreno_ocmem) 877 { 878 struct ocmem_buf *ocmem_hdl; 879 struct ocmem *ocmem; 880 881 ocmem = of_get_ocmem(dev); 882 if (IS_ERR(ocmem)) { 883 if (PTR_ERR(ocmem) == -ENODEV) { 884 /* 885 * Return success since either the ocmem property was 886 * not specified in device tree, or ocmem support is 887 * not compiled into the kernel. 888 */ 889 return 0; 890 } 891 892 return PTR_ERR(ocmem); 893 } 894 895 ocmem_hdl = ocmem_allocate(ocmem, OCMEM_GRAPHICS, adreno_gpu->gmem); 896 if (IS_ERR(ocmem_hdl)) 897 return PTR_ERR(ocmem_hdl); 898 899 adreno_ocmem->ocmem = ocmem; 900 adreno_ocmem->base = ocmem_hdl->addr; 901 adreno_ocmem->hdl = ocmem_hdl; 902 adreno_gpu->gmem = ocmem_hdl->len; 903 904 return 0; 905 } 906 907 void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *adreno_ocmem) 908 { 909 if (adreno_ocmem && adreno_ocmem->base) 910 ocmem_free(adreno_ocmem->ocmem, OCMEM_GRAPHICS, 911 adreno_ocmem->hdl); 912 } 913 914 int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, 915 struct adreno_gpu *adreno_gpu, 916 const struct adreno_gpu_funcs *funcs, int nr_rings) 917 { 918 struct device *dev = &pdev->dev; 919 struct adreno_platform_config *config = dev->platform_data; 920 struct msm_gpu_config adreno_gpu_config = { 0 }; 921 struct msm_gpu *gpu = &adreno_gpu->base; 922 923 adreno_gpu->funcs = funcs; 924 adreno_gpu->info = adreno_info(config->rev); 925 adreno_gpu->gmem = adreno_gpu->info->gmem; 926 adreno_gpu->revn = adreno_gpu->info->revn; 927 adreno_gpu->rev = config->rev; 928 929 adreno_gpu_config.ioname = "kgsl_3d0_reg_memory"; 930 931 adreno_gpu_config.nr_rings = nr_rings; 932 933 adreno_get_pwrlevels(dev, gpu); 934 935 pm_runtime_set_autosuspend_delay(dev, 936 adreno_gpu->info->inactive_period); 937 pm_runtime_use_autosuspend(dev); 938 pm_runtime_enable(dev); 939 940 return msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base, 941 adreno_gpu->info->name, &adreno_gpu_config); 942 } 943 944 void adreno_gpu_cleanup(struct adreno_gpu *adreno_gpu) 945 { 946 struct msm_gpu *gpu = &adreno_gpu->base; 947 struct msm_drm_private *priv = gpu->dev->dev_private; 948 unsigned int i; 949 950 for (i = 0; i < ARRAY_SIZE(adreno_gpu->info->fw); i++) 951 release_firmware(adreno_gpu->fw[i]); 952 953 pm_runtime_disable(&priv->gpu_pdev->dev); 954 955 msm_gpu_cleanup(&adreno_gpu->base); 956 957 icc_put(gpu->icc_path); 958 icc_put(gpu->ocmem_icc_path); 959 } 960