1 /* 2 * Copyright (C) 2013-2014 Red Hat 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License version 2 as published by 9 * the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include <linux/pm_opp.h> 21 #include "adreno_gpu.h" 22 23 #define ANY_ID 0xff 24 25 bool hang_debug = false; 26 MODULE_PARM_DESC(hang_debug, "Dump registers when hang is detected (can be slow!)"); 27 module_param_named(hang_debug, hang_debug, bool, 0600); 28 29 static const struct adreno_info gpulist[] = { 30 { 31 .rev = ADRENO_REV(3, 0, 5, ANY_ID), 32 .revn = 305, 33 .name = "A305", 34 .pm4fw = "a300_pm4.fw", 35 .pfpfw = "a300_pfp.fw", 36 .gmem = SZ_256K, 37 .init = a3xx_gpu_init, 38 }, { 39 .rev = ADRENO_REV(3, 0, 6, 0), 40 .revn = 307, /* because a305c is revn==306 */ 41 .name = "A306", 42 .pm4fw = "a300_pm4.fw", 43 .pfpfw = "a300_pfp.fw", 44 .gmem = SZ_128K, 45 .init = a3xx_gpu_init, 46 }, { 47 .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID), 48 .revn = 320, 49 .name = "A320", 50 .pm4fw = "a300_pm4.fw", 51 .pfpfw = "a300_pfp.fw", 52 .gmem = SZ_512K, 53 .init = a3xx_gpu_init, 54 }, { 55 .rev = ADRENO_REV(3, 3, 0, ANY_ID), 56 .revn = 330, 57 .name = "A330", 58 .pm4fw = "a330_pm4.fw", 59 .pfpfw = "a330_pfp.fw", 60 .gmem = SZ_1M, 61 .init = a3xx_gpu_init, 62 }, { 63 .rev = ADRENO_REV(4, 2, 0, ANY_ID), 64 .revn = 420, 65 .name = "A420", 66 .pm4fw = "a420_pm4.fw", 67 .pfpfw = "a420_pfp.fw", 68 .gmem = (SZ_1M + SZ_512K), 69 .init = a4xx_gpu_init, 70 }, { 71 .rev = ADRENO_REV(4, 3, 0, ANY_ID), 72 .revn = 430, 73 .name = "A430", 74 .pm4fw = "a420_pm4.fw", 75 .pfpfw = "a420_pfp.fw", 76 .gmem = (SZ_1M + SZ_512K), 77 .init = a4xx_gpu_init, 78 }, { 79 .rev = ADRENO_REV(5, 3, 0, 2), 80 .revn = 530, 81 .name = "A530", 82 .pm4fw = "a530_pm4.fw", 83 .pfpfw = "a530_pfp.fw", 84 .gmem = SZ_1M, 85 .quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI | 86 ADRENO_QUIRK_FAULT_DETECT_MASK, 87 .init = a5xx_gpu_init, 88 .gpmufw = "a530v3_gpmu.fw2", 89 .zapfw = "a530_zap.mdt", 90 }, 91 }; 92 93 MODULE_FIRMWARE("a300_pm4.fw"); 94 MODULE_FIRMWARE("a300_pfp.fw"); 95 MODULE_FIRMWARE("a330_pm4.fw"); 96 MODULE_FIRMWARE("a330_pfp.fw"); 97 MODULE_FIRMWARE("a420_pm4.fw"); 98 MODULE_FIRMWARE("a420_pfp.fw"); 99 MODULE_FIRMWARE("a530_fm4.fw"); 100 MODULE_FIRMWARE("a530_pfp.fw"); 101 102 static inline bool _rev_match(uint8_t entry, uint8_t id) 103 { 104 return (entry == ANY_ID) || (entry == id); 105 } 106 107 const struct adreno_info *adreno_info(struct adreno_rev rev) 108 { 109 int i; 110 111 /* identify gpu: */ 112 for (i = 0; i < ARRAY_SIZE(gpulist); i++) { 113 const struct adreno_info *info = &gpulist[i]; 114 if (_rev_match(info->rev.core, rev.core) && 115 _rev_match(info->rev.major, rev.major) && 116 _rev_match(info->rev.minor, rev.minor) && 117 _rev_match(info->rev.patchid, rev.patchid)) 118 return info; 119 } 120 121 return NULL; 122 } 123 124 struct msm_gpu *adreno_load_gpu(struct drm_device *dev) 125 { 126 struct msm_drm_private *priv = dev->dev_private; 127 struct platform_device *pdev = priv->gpu_pdev; 128 struct msm_gpu *gpu = platform_get_drvdata(priv->gpu_pdev); 129 int ret; 130 131 if (!gpu) { 132 dev_err(dev->dev, "no adreno device\n"); 133 return NULL; 134 } 135 136 pm_runtime_get_sync(&pdev->dev); 137 mutex_lock(&dev->struct_mutex); 138 ret = msm_gpu_hw_init(gpu); 139 mutex_unlock(&dev->struct_mutex); 140 pm_runtime_put_sync(&pdev->dev); 141 if (ret) { 142 dev_err(dev->dev, "gpu hw init failed: %d\n", ret); 143 return NULL; 144 } 145 146 return gpu; 147 } 148 149 static void set_gpu_pdev(struct drm_device *dev, 150 struct platform_device *pdev) 151 { 152 struct msm_drm_private *priv = dev->dev_private; 153 priv->gpu_pdev = pdev; 154 } 155 156 static int find_chipid(struct device *dev, u32 *chipid) 157 { 158 struct device_node *node = dev->of_node; 159 const char *compat; 160 int ret; 161 162 /* first search the compat strings for qcom,adreno-XYZ.W: */ 163 ret = of_property_read_string_index(node, "compatible", 0, &compat); 164 if (ret == 0) { 165 unsigned rev, patch; 166 167 if (sscanf(compat, "qcom,adreno-%u.%u", &rev, &patch) == 2) { 168 *chipid = 0; 169 *chipid |= (rev / 100) << 24; /* core */ 170 rev %= 100; 171 *chipid |= (rev / 10) << 16; /* major */ 172 rev %= 10; 173 *chipid |= rev << 8; /* minor */ 174 *chipid |= patch; 175 176 return 0; 177 } 178 } 179 180 /* and if that fails, fall back to legacy "qcom,chipid" property: */ 181 ret = of_property_read_u32(node, "qcom,chipid", chipid); 182 if (ret) 183 return ret; 184 185 dev_warn(dev, "Using legacy qcom,chipid binding!\n"); 186 dev_warn(dev, "Use compatible qcom,adreno-%u%u%u.%u instead.\n", 187 (*chipid >> 24) & 0xff, (*chipid >> 16) & 0xff, 188 (*chipid >> 8) & 0xff, *chipid & 0xff); 189 190 return 0; 191 } 192 193 /* Get legacy powerlevels from qcom,gpu-pwrlevels and populate the opp table */ 194 static int adreno_get_legacy_pwrlevels(struct device *dev) 195 { 196 struct device_node *child, *node; 197 int ret; 198 199 node = of_find_compatible_node(dev->of_node, NULL, 200 "qcom,gpu-pwrlevels"); 201 if (!node) { 202 dev_err(dev, "Could not find the GPU powerlevels\n"); 203 return -ENXIO; 204 } 205 206 for_each_child_of_node(node, child) { 207 unsigned int val; 208 209 ret = of_property_read_u32(child, "qcom,gpu-freq", &val); 210 if (ret) 211 continue; 212 213 /* 214 * Skip the intentionally bogus clock value found at the bottom 215 * of most legacy frequency tables 216 */ 217 if (val != 27000000) 218 dev_pm_opp_add(dev, val, 0); 219 } 220 221 return 0; 222 } 223 224 static int adreno_get_pwrlevels(struct device *dev, 225 struct adreno_platform_config *config) 226 { 227 unsigned long freq = ULONG_MAX; 228 struct dev_pm_opp *opp; 229 int ret; 230 231 /* You down with OPP? */ 232 if (!of_find_property(dev->of_node, "operating-points-v2", NULL)) 233 ret = adreno_get_legacy_pwrlevels(dev); 234 else 235 ret = dev_pm_opp_of_add_table(dev); 236 237 if (ret) 238 return ret; 239 240 /* Find the fastest defined rate */ 241 opp = dev_pm_opp_find_freq_floor(dev, &freq); 242 if (!IS_ERR(opp)) 243 config->fast_rate = dev_pm_opp_get_freq(opp); 244 245 if (!config->fast_rate) { 246 DRM_DEV_INFO(dev, 247 "Could not find clock rate. Using default\n"); 248 /* Pick a suitably safe clock speed for any target */ 249 config->fast_rate = 200000000; 250 } 251 252 return 0; 253 } 254 255 static int adreno_bind(struct device *dev, struct device *master, void *data) 256 { 257 static struct adreno_platform_config config = {}; 258 const struct adreno_info *info; 259 struct drm_device *drm = dev_get_drvdata(master); 260 struct msm_gpu *gpu; 261 u32 val; 262 int ret; 263 264 ret = find_chipid(dev, &val); 265 if (ret) { 266 dev_err(dev, "could not find chipid: %d\n", ret); 267 return ret; 268 } 269 270 config.rev = ADRENO_REV((val >> 24) & 0xff, 271 (val >> 16) & 0xff, (val >> 8) & 0xff, val & 0xff); 272 273 /* find clock rates: */ 274 config.fast_rate = 0; 275 276 ret = adreno_get_pwrlevels(dev, &config); 277 if (ret) 278 return ret; 279 280 dev->platform_data = &config; 281 set_gpu_pdev(drm, to_platform_device(dev)); 282 283 info = adreno_info(config.rev); 284 285 if (!info) { 286 dev_warn(drm->dev, "Unknown GPU revision: %u.%u.%u.%u\n", 287 config.rev.core, config.rev.major, 288 config.rev.minor, config.rev.patchid); 289 return -ENXIO; 290 } 291 292 DBG("Found GPU: %u.%u.%u.%u", config.rev.core, config.rev.major, 293 config.rev.minor, config.rev.patchid); 294 295 gpu = info->init(drm); 296 if (IS_ERR(gpu)) { 297 dev_warn(drm->dev, "failed to load adreno gpu\n"); 298 return PTR_ERR(gpu); 299 } 300 301 dev_set_drvdata(dev, gpu); 302 303 return 0; 304 } 305 306 static void adreno_unbind(struct device *dev, struct device *master, 307 void *data) 308 { 309 struct msm_gpu *gpu = dev_get_drvdata(dev); 310 311 gpu->funcs->pm_suspend(gpu); 312 gpu->funcs->destroy(gpu); 313 314 set_gpu_pdev(dev_get_drvdata(master), NULL); 315 } 316 317 static const struct component_ops a3xx_ops = { 318 .bind = adreno_bind, 319 .unbind = adreno_unbind, 320 }; 321 322 static int adreno_probe(struct platform_device *pdev) 323 { 324 return component_add(&pdev->dev, &a3xx_ops); 325 } 326 327 static int adreno_remove(struct platform_device *pdev) 328 { 329 component_del(&pdev->dev, &a3xx_ops); 330 return 0; 331 } 332 333 static const struct of_device_id dt_match[] = { 334 { .compatible = "qcom,adreno" }, 335 { .compatible = "qcom,adreno-3xx" }, 336 /* for backwards compat w/ downstream kgsl DT files: */ 337 { .compatible = "qcom,kgsl-3d0" }, 338 {} 339 }; 340 341 #ifdef CONFIG_PM 342 static int adreno_resume(struct device *dev) 343 { 344 struct platform_device *pdev = to_platform_device(dev); 345 struct msm_gpu *gpu = platform_get_drvdata(pdev); 346 347 return gpu->funcs->pm_resume(gpu); 348 } 349 350 static int adreno_suspend(struct device *dev) 351 { 352 struct platform_device *pdev = to_platform_device(dev); 353 struct msm_gpu *gpu = platform_get_drvdata(pdev); 354 355 return gpu->funcs->pm_suspend(gpu); 356 } 357 #endif 358 359 static const struct dev_pm_ops adreno_pm_ops = { 360 SET_RUNTIME_PM_OPS(adreno_suspend, adreno_resume, NULL) 361 }; 362 363 static struct platform_driver adreno_driver = { 364 .probe = adreno_probe, 365 .remove = adreno_remove, 366 .driver = { 367 .name = "adreno", 368 .of_match_table = dt_match, 369 .pm = &adreno_pm_ops, 370 }, 371 }; 372 373 void __init adreno_register(void) 374 { 375 platform_driver_register(&adreno_driver); 376 } 377 378 void __exit adreno_unregister(void) 379 { 380 platform_driver_unregister(&adreno_driver); 381 } 382