1 /* 2 * Copyright (C) 2013-2014 Red Hat 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License version 2 as published by 9 * the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "adreno_gpu.h" 21 22 #define ANY_ID 0xff 23 24 bool hang_debug = false; 25 MODULE_PARM_DESC(hang_debug, "Dump registers when hang is detected (can be slow!)"); 26 module_param_named(hang_debug, hang_debug, bool, 0600); 27 28 static const struct adreno_info gpulist[] = { 29 { 30 .rev = ADRENO_REV(3, 0, 5, ANY_ID), 31 .revn = 305, 32 .name = "A305", 33 .fw = { 34 [ADRENO_FW_PM4] = "a300_pm4.fw", 35 [ADRENO_FW_PFP] = "a300_pfp.fw", 36 }, 37 .gmem = SZ_256K, 38 .init = a3xx_gpu_init, 39 }, { 40 .rev = ADRENO_REV(3, 0, 6, 0), 41 .revn = 307, /* because a305c is revn==306 */ 42 .name = "A306", 43 .fw = { 44 [ADRENO_FW_PM4] = "a300_pm4.fw", 45 [ADRENO_FW_PFP] = "a300_pfp.fw", 46 }, 47 .gmem = SZ_128K, 48 .init = a3xx_gpu_init, 49 }, { 50 .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID), 51 .revn = 320, 52 .name = "A320", 53 .fw = { 54 [ADRENO_FW_PM4] = "a300_pm4.fw", 55 [ADRENO_FW_PFP] = "a300_pfp.fw", 56 }, 57 .gmem = SZ_512K, 58 .init = a3xx_gpu_init, 59 }, { 60 .rev = ADRENO_REV(3, 3, 0, ANY_ID), 61 .revn = 330, 62 .name = "A330", 63 .fw = { 64 [ADRENO_FW_PM4] = "a330_pm4.fw", 65 [ADRENO_FW_PFP] = "a330_pfp.fw", 66 }, 67 .gmem = SZ_1M, 68 .init = a3xx_gpu_init, 69 }, { 70 .rev = ADRENO_REV(4, 2, 0, ANY_ID), 71 .revn = 420, 72 .name = "A420", 73 .fw = { 74 [ADRENO_FW_PM4] = "a420_pm4.fw", 75 [ADRENO_FW_PFP] = "a420_pfp.fw", 76 }, 77 .gmem = (SZ_1M + SZ_512K), 78 .init = a4xx_gpu_init, 79 }, { 80 .rev = ADRENO_REV(4, 3, 0, ANY_ID), 81 .revn = 430, 82 .name = "A430", 83 .fw = { 84 [ADRENO_FW_PM4] = "a420_pm4.fw", 85 [ADRENO_FW_PFP] = "a420_pfp.fw", 86 }, 87 .gmem = (SZ_1M + SZ_512K), 88 .init = a4xx_gpu_init, 89 }, { 90 .rev = ADRENO_REV(5, 3, 0, 2), 91 .revn = 530, 92 .name = "A530", 93 .fw = { 94 [ADRENO_FW_PM4] = "a530_pm4.fw", 95 [ADRENO_FW_PFP] = "a530_pfp.fw", 96 [ADRENO_FW_GPMU] = "a530v3_gpmu.fw2", 97 }, 98 .gmem = SZ_1M, 99 .quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI | 100 ADRENO_QUIRK_FAULT_DETECT_MASK, 101 .init = a5xx_gpu_init, 102 .zapfw = "a530_zap.mdt", 103 }, 104 }; 105 106 MODULE_FIRMWARE("qcom/a300_pm4.fw"); 107 MODULE_FIRMWARE("qcom/a300_pfp.fw"); 108 MODULE_FIRMWARE("qcom/a330_pm4.fw"); 109 MODULE_FIRMWARE("qcom/a330_pfp.fw"); 110 MODULE_FIRMWARE("qcom/a420_pm4.fw"); 111 MODULE_FIRMWARE("qcom/a420_pfp.fw"); 112 MODULE_FIRMWARE("qcom/a530_pm4.fw"); 113 MODULE_FIRMWARE("qcom/a530_pfp.fw"); 114 MODULE_FIRMWARE("qcom/a530v3_gpmu.fw2"); 115 MODULE_FIRMWARE("qcom/a530_zap.mdt"); 116 MODULE_FIRMWARE("qcom/a530_zap.b00"); 117 MODULE_FIRMWARE("qcom/a530_zap.b01"); 118 MODULE_FIRMWARE("qcom/a530_zap.b02"); 119 120 static inline bool _rev_match(uint8_t entry, uint8_t id) 121 { 122 return (entry == ANY_ID) || (entry == id); 123 } 124 125 const struct adreno_info *adreno_info(struct adreno_rev rev) 126 { 127 int i; 128 129 /* identify gpu: */ 130 for (i = 0; i < ARRAY_SIZE(gpulist); i++) { 131 const struct adreno_info *info = &gpulist[i]; 132 if (_rev_match(info->rev.core, rev.core) && 133 _rev_match(info->rev.major, rev.major) && 134 _rev_match(info->rev.minor, rev.minor) && 135 _rev_match(info->rev.patchid, rev.patchid)) 136 return info; 137 } 138 139 return NULL; 140 } 141 142 struct msm_gpu *adreno_load_gpu(struct drm_device *dev) 143 { 144 struct msm_drm_private *priv = dev->dev_private; 145 struct platform_device *pdev = priv->gpu_pdev; 146 struct msm_gpu *gpu = NULL; 147 int ret; 148 149 if (pdev) 150 gpu = platform_get_drvdata(pdev); 151 152 if (!gpu) { 153 dev_err_once(dev->dev, "no GPU device was found\n"); 154 return NULL; 155 } 156 157 pm_runtime_get_sync(&pdev->dev); 158 mutex_lock(&dev->struct_mutex); 159 ret = msm_gpu_hw_init(gpu); 160 mutex_unlock(&dev->struct_mutex); 161 pm_runtime_put_sync(&pdev->dev); 162 if (ret) { 163 dev_err(dev->dev, "gpu hw init failed: %d\n", ret); 164 return NULL; 165 } 166 167 #ifdef CONFIG_DEBUG_FS 168 if (gpu->funcs->debugfs_init) { 169 gpu->funcs->debugfs_init(gpu, dev->primary); 170 gpu->funcs->debugfs_init(gpu, dev->render); 171 } 172 #endif 173 174 return gpu; 175 } 176 177 static void set_gpu_pdev(struct drm_device *dev, 178 struct platform_device *pdev) 179 { 180 struct msm_drm_private *priv = dev->dev_private; 181 priv->gpu_pdev = pdev; 182 } 183 184 static int find_chipid(struct device *dev, struct adreno_rev *rev) 185 { 186 struct device_node *node = dev->of_node; 187 const char *compat; 188 int ret; 189 u32 chipid; 190 191 /* first search the compat strings for qcom,adreno-XYZ.W: */ 192 ret = of_property_read_string_index(node, "compatible", 0, &compat); 193 if (ret == 0) { 194 unsigned int r, patch; 195 196 if (sscanf(compat, "qcom,adreno-%u.%u", &r, &patch) == 2) { 197 rev->core = r / 100; 198 r %= 100; 199 rev->major = r / 10; 200 r %= 10; 201 rev->minor = r; 202 rev->patchid = patch; 203 204 return 0; 205 } 206 } 207 208 /* and if that fails, fall back to legacy "qcom,chipid" property: */ 209 ret = of_property_read_u32(node, "qcom,chipid", &chipid); 210 if (ret) { 211 dev_err(dev, "could not parse qcom,chipid: %d\n", ret); 212 return ret; 213 } 214 215 rev->core = (chipid >> 24) & 0xff; 216 rev->major = (chipid >> 16) & 0xff; 217 rev->minor = (chipid >> 8) & 0xff; 218 rev->patchid = (chipid & 0xff); 219 220 dev_warn(dev, "Using legacy qcom,chipid binding!\n"); 221 dev_warn(dev, "Use compatible qcom,adreno-%u%u%u.%u instead.\n", 222 rev->core, rev->major, rev->minor, rev->patchid); 223 224 return 0; 225 } 226 227 static int adreno_bind(struct device *dev, struct device *master, void *data) 228 { 229 static struct adreno_platform_config config = {}; 230 const struct adreno_info *info; 231 struct drm_device *drm = dev_get_drvdata(master); 232 struct msm_gpu *gpu; 233 int ret; 234 235 ret = find_chipid(dev, &config.rev); 236 if (ret) 237 return ret; 238 239 dev->platform_data = &config; 240 set_gpu_pdev(drm, to_platform_device(dev)); 241 242 info = adreno_info(config.rev); 243 244 if (!info) { 245 dev_warn(drm->dev, "Unknown GPU revision: %u.%u.%u.%u\n", 246 config.rev.core, config.rev.major, 247 config.rev.minor, config.rev.patchid); 248 return -ENXIO; 249 } 250 251 DBG("Found GPU: %u.%u.%u.%u", config.rev.core, config.rev.major, 252 config.rev.minor, config.rev.patchid); 253 254 gpu = info->init(drm); 255 if (IS_ERR(gpu)) { 256 dev_warn(drm->dev, "failed to load adreno gpu\n"); 257 return PTR_ERR(gpu); 258 } 259 260 dev_set_drvdata(dev, gpu); 261 262 return 0; 263 } 264 265 static void adreno_unbind(struct device *dev, struct device *master, 266 void *data) 267 { 268 struct msm_gpu *gpu = dev_get_drvdata(dev); 269 270 gpu->funcs->pm_suspend(gpu); 271 gpu->funcs->destroy(gpu); 272 273 set_gpu_pdev(dev_get_drvdata(master), NULL); 274 } 275 276 static const struct component_ops a3xx_ops = { 277 .bind = adreno_bind, 278 .unbind = adreno_unbind, 279 }; 280 281 static int adreno_probe(struct platform_device *pdev) 282 { 283 return component_add(&pdev->dev, &a3xx_ops); 284 } 285 286 static int adreno_remove(struct platform_device *pdev) 287 { 288 component_del(&pdev->dev, &a3xx_ops); 289 return 0; 290 } 291 292 static const struct of_device_id dt_match[] = { 293 { .compatible = "qcom,adreno" }, 294 { .compatible = "qcom,adreno-3xx" }, 295 /* for backwards compat w/ downstream kgsl DT files: */ 296 { .compatible = "qcom,kgsl-3d0" }, 297 {} 298 }; 299 300 #ifdef CONFIG_PM 301 static int adreno_resume(struct device *dev) 302 { 303 struct platform_device *pdev = to_platform_device(dev); 304 struct msm_gpu *gpu = platform_get_drvdata(pdev); 305 306 return gpu->funcs->pm_resume(gpu); 307 } 308 309 static int adreno_suspend(struct device *dev) 310 { 311 struct platform_device *pdev = to_platform_device(dev); 312 struct msm_gpu *gpu = platform_get_drvdata(pdev); 313 314 return gpu->funcs->pm_suspend(gpu); 315 } 316 #endif 317 318 static const struct dev_pm_ops adreno_pm_ops = { 319 SET_RUNTIME_PM_OPS(adreno_suspend, adreno_resume, NULL) 320 }; 321 322 static struct platform_driver adreno_driver = { 323 .probe = adreno_probe, 324 .remove = adreno_remove, 325 .driver = { 326 .name = "adreno", 327 .of_match_table = dt_match, 328 .pm = &adreno_pm_ops, 329 }, 330 }; 331 332 void __init adreno_register(void) 333 { 334 platform_driver_register(&adreno_driver); 335 } 336 337 void __exit adreno_unregister(void) 338 { 339 platform_driver_unregister(&adreno_driver); 340 } 341