1 /* 2 * Copyright (C) 2013-2014 Red Hat 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License version 2 as published by 9 * the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "adreno_gpu.h" 21 22 #define ANY_ID 0xff 23 24 bool hang_debug = false; 25 MODULE_PARM_DESC(hang_debug, "Dump registers when hang is detected (can be slow!)"); 26 module_param_named(hang_debug, hang_debug, bool, 0600); 27 28 struct msm_gpu *a3xx_gpu_init(struct drm_device *dev); 29 struct msm_gpu *a4xx_gpu_init(struct drm_device *dev); 30 31 static const struct adreno_info gpulist[] = { 32 { 33 .rev = ADRENO_REV(3, 0, 5, ANY_ID), 34 .revn = 305, 35 .name = "A305", 36 .pm4fw = "a300_pm4.fw", 37 .pfpfw = "a300_pfp.fw", 38 .gmem = SZ_256K, 39 .init = a3xx_gpu_init, 40 }, { 41 .rev = ADRENO_REV(3, 0, 6, 0), 42 .revn = 307, /* because a305c is revn==306 */ 43 .name = "A306", 44 .pm4fw = "a300_pm4.fw", 45 .pfpfw = "a300_pfp.fw", 46 .gmem = SZ_128K, 47 .init = a3xx_gpu_init, 48 }, { 49 .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID), 50 .revn = 320, 51 .name = "A320", 52 .pm4fw = "a300_pm4.fw", 53 .pfpfw = "a300_pfp.fw", 54 .gmem = SZ_512K, 55 .init = a3xx_gpu_init, 56 }, { 57 .rev = ADRENO_REV(3, 3, 0, ANY_ID), 58 .revn = 330, 59 .name = "A330", 60 .pm4fw = "a330_pm4.fw", 61 .pfpfw = "a330_pfp.fw", 62 .gmem = SZ_1M, 63 .init = a3xx_gpu_init, 64 }, { 65 .rev = ADRENO_REV(4, 2, 0, ANY_ID), 66 .revn = 420, 67 .name = "A420", 68 .pm4fw = "a420_pm4.fw", 69 .pfpfw = "a420_pfp.fw", 70 .gmem = (SZ_1M + SZ_512K), 71 .init = a4xx_gpu_init, 72 }, 73 }; 74 75 MODULE_FIRMWARE("a300_pm4.fw"); 76 MODULE_FIRMWARE("a300_pfp.fw"); 77 MODULE_FIRMWARE("a330_pm4.fw"); 78 MODULE_FIRMWARE("a330_pfp.fw"); 79 MODULE_FIRMWARE("a420_pm4.fw"); 80 MODULE_FIRMWARE("a420_pfp.fw"); 81 82 static inline bool _rev_match(uint8_t entry, uint8_t id) 83 { 84 return (entry == ANY_ID) || (entry == id); 85 } 86 87 const struct adreno_info *adreno_info(struct adreno_rev rev) 88 { 89 int i; 90 91 /* identify gpu: */ 92 for (i = 0; i < ARRAY_SIZE(gpulist); i++) { 93 const struct adreno_info *info = &gpulist[i]; 94 if (_rev_match(info->rev.core, rev.core) && 95 _rev_match(info->rev.major, rev.major) && 96 _rev_match(info->rev.minor, rev.minor) && 97 _rev_match(info->rev.patchid, rev.patchid)) 98 return info; 99 } 100 101 return NULL; 102 } 103 104 struct msm_gpu *adreno_load_gpu(struct drm_device *dev) 105 { 106 struct msm_drm_private *priv = dev->dev_private; 107 struct platform_device *pdev = priv->gpu_pdev; 108 struct adreno_platform_config *config; 109 struct adreno_rev rev; 110 const struct adreno_info *info; 111 struct msm_gpu *gpu = NULL; 112 113 if (!pdev) { 114 dev_err(dev->dev, "no adreno device\n"); 115 return NULL; 116 } 117 118 config = pdev->dev.platform_data; 119 rev = config->rev; 120 info = adreno_info(config->rev); 121 122 if (!info) { 123 dev_warn(dev->dev, "Unknown GPU revision: %u.%u.%u.%u\n", 124 rev.core, rev.major, rev.minor, rev.patchid); 125 return NULL; 126 } 127 128 DBG("Found GPU: %u.%u.%u.%u", rev.core, rev.major, 129 rev.minor, rev.patchid); 130 131 gpu = info->init(dev); 132 if (IS_ERR(gpu)) { 133 dev_warn(dev->dev, "failed to load adreno gpu\n"); 134 gpu = NULL; 135 /* not fatal */ 136 } 137 138 if (gpu) { 139 int ret; 140 mutex_lock(&dev->struct_mutex); 141 gpu->funcs->pm_resume(gpu); 142 mutex_unlock(&dev->struct_mutex); 143 ret = gpu->funcs->hw_init(gpu); 144 if (ret) { 145 dev_err(dev->dev, "gpu hw init failed: %d\n", ret); 146 gpu->funcs->destroy(gpu); 147 gpu = NULL; 148 } else { 149 /* give inactive pm a chance to kick in: */ 150 msm_gpu_retire(gpu); 151 } 152 } 153 154 return gpu; 155 } 156 157 static void set_gpu_pdev(struct drm_device *dev, 158 struct platform_device *pdev) 159 { 160 struct msm_drm_private *priv = dev->dev_private; 161 priv->gpu_pdev = pdev; 162 } 163 164 static int adreno_bind(struct device *dev, struct device *master, void *data) 165 { 166 static struct adreno_platform_config config = {}; 167 struct device_node *child, *node = dev->of_node; 168 u32 val; 169 int ret; 170 171 ret = of_property_read_u32(node, "qcom,chipid", &val); 172 if (ret) { 173 dev_err(dev, "could not find chipid: %d\n", ret); 174 return ret; 175 } 176 177 config.rev = ADRENO_REV((val >> 24) & 0xff, 178 (val >> 16) & 0xff, (val >> 8) & 0xff, val & 0xff); 179 180 /* find clock rates: */ 181 config.fast_rate = 0; 182 config.slow_rate = ~0; 183 for_each_child_of_node(node, child) { 184 if (of_device_is_compatible(child, "qcom,gpu-pwrlevels")) { 185 struct device_node *pwrlvl; 186 for_each_child_of_node(child, pwrlvl) { 187 ret = of_property_read_u32(pwrlvl, "qcom,gpu-freq", &val); 188 if (ret) { 189 dev_err(dev, "could not find gpu-freq: %d\n", ret); 190 return ret; 191 } 192 config.fast_rate = max(config.fast_rate, val); 193 config.slow_rate = min(config.slow_rate, val); 194 } 195 } 196 } 197 198 if (!config.fast_rate) { 199 dev_err(dev, "could not find clk rates\n"); 200 return -ENXIO; 201 } 202 203 dev->platform_data = &config; 204 set_gpu_pdev(dev_get_drvdata(master), to_platform_device(dev)); 205 return 0; 206 } 207 208 static void adreno_unbind(struct device *dev, struct device *master, 209 void *data) 210 { 211 set_gpu_pdev(dev_get_drvdata(master), NULL); 212 } 213 214 static const struct component_ops a3xx_ops = { 215 .bind = adreno_bind, 216 .unbind = adreno_unbind, 217 }; 218 219 static int adreno_probe(struct platform_device *pdev) 220 { 221 return component_add(&pdev->dev, &a3xx_ops); 222 } 223 224 static int adreno_remove(struct platform_device *pdev) 225 { 226 component_del(&pdev->dev, &a3xx_ops); 227 return 0; 228 } 229 230 static const struct of_device_id dt_match[] = { 231 { .compatible = "qcom,adreno-3xx" }, 232 /* for backwards compat w/ downstream kgsl DT files: */ 233 { .compatible = "qcom,kgsl-3d0" }, 234 {} 235 }; 236 237 static struct platform_driver adreno_driver = { 238 .probe = adreno_probe, 239 .remove = adreno_remove, 240 .driver = { 241 .name = "adreno", 242 .of_match_table = dt_match, 243 }, 244 }; 245 246 void __init adreno_register(void) 247 { 248 platform_driver_register(&adreno_driver); 249 } 250 251 void __exit adreno_unregister(void) 252 { 253 platform_driver_unregister(&adreno_driver); 254 } 255