1 /* 2 * Copyright (C) 2013-2014 Red Hat 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License version 2 as published by 9 * the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include <linux/pm_opp.h> 21 #include "adreno_gpu.h" 22 23 #define ANY_ID 0xff 24 25 bool hang_debug = false; 26 MODULE_PARM_DESC(hang_debug, "Dump registers when hang is detected (can be slow!)"); 27 module_param_named(hang_debug, hang_debug, bool, 0600); 28 29 static const struct adreno_info gpulist[] = { 30 { 31 .rev = ADRENO_REV(3, 0, 5, ANY_ID), 32 .revn = 305, 33 .name = "A305", 34 .pm4fw = "a300_pm4.fw", 35 .pfpfw = "a300_pfp.fw", 36 .gmem = SZ_256K, 37 .init = a3xx_gpu_init, 38 }, { 39 .rev = ADRENO_REV(3, 0, 6, 0), 40 .revn = 307, /* because a305c is revn==306 */ 41 .name = "A306", 42 .pm4fw = "a300_pm4.fw", 43 .pfpfw = "a300_pfp.fw", 44 .gmem = SZ_128K, 45 .init = a3xx_gpu_init, 46 }, { 47 .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID), 48 .revn = 320, 49 .name = "A320", 50 .pm4fw = "a300_pm4.fw", 51 .pfpfw = "a300_pfp.fw", 52 .gmem = SZ_512K, 53 .init = a3xx_gpu_init, 54 }, { 55 .rev = ADRENO_REV(3, 3, 0, ANY_ID), 56 .revn = 330, 57 .name = "A330", 58 .pm4fw = "a330_pm4.fw", 59 .pfpfw = "a330_pfp.fw", 60 .gmem = SZ_1M, 61 .init = a3xx_gpu_init, 62 }, { 63 .rev = ADRENO_REV(4, 2, 0, ANY_ID), 64 .revn = 420, 65 .name = "A420", 66 .pm4fw = "a420_pm4.fw", 67 .pfpfw = "a420_pfp.fw", 68 .gmem = (SZ_1M + SZ_512K), 69 .init = a4xx_gpu_init, 70 }, { 71 .rev = ADRENO_REV(4, 3, 0, ANY_ID), 72 .revn = 430, 73 .name = "A430", 74 .pm4fw = "a420_pm4.fw", 75 .pfpfw = "a420_pfp.fw", 76 .gmem = (SZ_1M + SZ_512K), 77 .init = a4xx_gpu_init, 78 }, { 79 .rev = ADRENO_REV(5, 3, 0, 2), 80 .revn = 530, 81 .name = "A530", 82 .pm4fw = "a530_pm4.fw", 83 .pfpfw = "a530_pfp.fw", 84 .gmem = SZ_1M, 85 .quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI | 86 ADRENO_QUIRK_FAULT_DETECT_MASK, 87 .init = a5xx_gpu_init, 88 .gpmufw = "a530v3_gpmu.fw2", 89 }, 90 }; 91 92 MODULE_FIRMWARE("a300_pm4.fw"); 93 MODULE_FIRMWARE("a300_pfp.fw"); 94 MODULE_FIRMWARE("a330_pm4.fw"); 95 MODULE_FIRMWARE("a330_pfp.fw"); 96 MODULE_FIRMWARE("a420_pm4.fw"); 97 MODULE_FIRMWARE("a420_pfp.fw"); 98 MODULE_FIRMWARE("a530_fm4.fw"); 99 MODULE_FIRMWARE("a530_pfp.fw"); 100 101 static inline bool _rev_match(uint8_t entry, uint8_t id) 102 { 103 return (entry == ANY_ID) || (entry == id); 104 } 105 106 const struct adreno_info *adreno_info(struct adreno_rev rev) 107 { 108 int i; 109 110 /* identify gpu: */ 111 for (i = 0; i < ARRAY_SIZE(gpulist); i++) { 112 const struct adreno_info *info = &gpulist[i]; 113 if (_rev_match(info->rev.core, rev.core) && 114 _rev_match(info->rev.major, rev.major) && 115 _rev_match(info->rev.minor, rev.minor) && 116 _rev_match(info->rev.patchid, rev.patchid)) 117 return info; 118 } 119 120 return NULL; 121 } 122 123 struct msm_gpu *adreno_load_gpu(struct drm_device *dev) 124 { 125 struct msm_drm_private *priv = dev->dev_private; 126 struct platform_device *pdev = priv->gpu_pdev; 127 struct adreno_platform_config *config; 128 struct adreno_rev rev; 129 const struct adreno_info *info; 130 struct msm_gpu *gpu = NULL; 131 132 if (!pdev) { 133 dev_err(dev->dev, "no adreno device\n"); 134 return NULL; 135 } 136 137 config = pdev->dev.platform_data; 138 rev = config->rev; 139 info = adreno_info(config->rev); 140 141 if (!info) { 142 dev_warn(dev->dev, "Unknown GPU revision: %u.%u.%u.%u\n", 143 rev.core, rev.major, rev.minor, rev.patchid); 144 return NULL; 145 } 146 147 DBG("Found GPU: %u.%u.%u.%u", rev.core, rev.major, 148 rev.minor, rev.patchid); 149 150 gpu = info->init(dev); 151 if (IS_ERR(gpu)) { 152 dev_warn(dev->dev, "failed to load adreno gpu\n"); 153 gpu = NULL; 154 /* not fatal */ 155 } 156 157 if (gpu) { 158 int ret; 159 160 pm_runtime_get_sync(&pdev->dev); 161 ret = msm_gpu_hw_init(gpu); 162 pm_runtime_put_sync(&pdev->dev); 163 if (ret) { 164 dev_err(dev->dev, "gpu hw init failed: %d\n", ret); 165 gpu->funcs->destroy(gpu); 166 gpu = NULL; 167 } 168 } 169 170 return gpu; 171 } 172 173 static void set_gpu_pdev(struct drm_device *dev, 174 struct platform_device *pdev) 175 { 176 struct msm_drm_private *priv = dev->dev_private; 177 priv->gpu_pdev = pdev; 178 } 179 180 static int find_chipid(struct device *dev, u32 *chipid) 181 { 182 struct device_node *node = dev->of_node; 183 const char *compat; 184 int ret; 185 186 /* first search the compat strings for qcom,adreno-XYZ.W: */ 187 ret = of_property_read_string_index(node, "compatible", 0, &compat); 188 if (ret == 0) { 189 unsigned rev, patch; 190 191 if (sscanf(compat, "qcom,adreno-%u.%u", &rev, &patch) == 2) { 192 *chipid = 0; 193 *chipid |= (rev / 100) << 24; /* core */ 194 rev %= 100; 195 *chipid |= (rev / 10) << 16; /* major */ 196 rev %= 10; 197 *chipid |= rev << 8; /* minor */ 198 *chipid |= patch; 199 200 return 0; 201 } 202 } 203 204 /* and if that fails, fall back to legacy "qcom,chipid" property: */ 205 ret = of_property_read_u32(node, "qcom,chipid", chipid); 206 if (ret) 207 return ret; 208 209 dev_warn(dev, "Using legacy qcom,chipid binding!\n"); 210 dev_warn(dev, "Use compatible qcom,adreno-%u%u%u.%u instead.\n", 211 (*chipid >> 24) & 0xff, (*chipid >> 16) & 0xff, 212 (*chipid >> 8) & 0xff, *chipid & 0xff); 213 214 return 0; 215 } 216 217 /* Get legacy powerlevels from qcom,gpu-pwrlevels and populate the opp table */ 218 static int adreno_get_legacy_pwrlevels(struct device *dev) 219 { 220 struct device_node *child, *node; 221 int ret; 222 223 node = of_find_compatible_node(dev->of_node, NULL, 224 "qcom,gpu-pwrlevels"); 225 if (!node) { 226 dev_err(dev, "Could not find the GPU powerlevels\n"); 227 return -ENXIO; 228 } 229 230 for_each_child_of_node(node, child) { 231 unsigned int val; 232 233 ret = of_property_read_u32(child, "qcom,gpu-freq", &val); 234 if (ret) 235 continue; 236 237 /* 238 * Skip the intentionally bogus clock value found at the bottom 239 * of most legacy frequency tables 240 */ 241 if (val != 27000000) 242 dev_pm_opp_add(dev, val, 0); 243 } 244 245 return 0; 246 } 247 248 static int adreno_get_pwrlevels(struct device *dev, 249 struct adreno_platform_config *config) 250 { 251 unsigned long freq = ULONG_MAX; 252 struct dev_pm_opp *opp; 253 int ret; 254 255 /* You down with OPP? */ 256 if (!of_find_property(dev->of_node, "operating-points-v2", NULL)) 257 ret = adreno_get_legacy_pwrlevels(dev); 258 else 259 ret = dev_pm_opp_of_add_table(dev); 260 261 if (ret) 262 return ret; 263 264 /* Find the fastest defined rate */ 265 opp = dev_pm_opp_find_freq_floor(dev, &freq); 266 if (!IS_ERR(opp)) 267 config->fast_rate = dev_pm_opp_get_freq(opp); 268 269 if (!config->fast_rate) { 270 DRM_DEV_INFO(dev, 271 "Could not find clock rate. Using default\n"); 272 /* Pick a suitably safe clock speed for any target */ 273 config->fast_rate = 200000000; 274 } 275 276 return 0; 277 } 278 279 static int adreno_bind(struct device *dev, struct device *master, void *data) 280 { 281 static struct adreno_platform_config config = {}; 282 u32 val; 283 int ret; 284 285 ret = find_chipid(dev, &val); 286 if (ret) { 287 dev_err(dev, "could not find chipid: %d\n", ret); 288 return ret; 289 } 290 291 config.rev = ADRENO_REV((val >> 24) & 0xff, 292 (val >> 16) & 0xff, (val >> 8) & 0xff, val & 0xff); 293 294 /* find clock rates: */ 295 config.fast_rate = 0; 296 297 ret = adreno_get_pwrlevels(dev, &config); 298 if (ret) 299 return ret; 300 301 dev->platform_data = &config; 302 set_gpu_pdev(dev_get_drvdata(master), to_platform_device(dev)); 303 return 0; 304 } 305 306 static void adreno_unbind(struct device *dev, struct device *master, 307 void *data) 308 { 309 set_gpu_pdev(dev_get_drvdata(master), NULL); 310 } 311 312 static const struct component_ops a3xx_ops = { 313 .bind = adreno_bind, 314 .unbind = adreno_unbind, 315 }; 316 317 static int adreno_probe(struct platform_device *pdev) 318 { 319 return component_add(&pdev->dev, &a3xx_ops); 320 } 321 322 static int adreno_remove(struct platform_device *pdev) 323 { 324 component_del(&pdev->dev, &a3xx_ops); 325 return 0; 326 } 327 328 static const struct of_device_id dt_match[] = { 329 { .compatible = "qcom,adreno" }, 330 { .compatible = "qcom,adreno-3xx" }, 331 /* for backwards compat w/ downstream kgsl DT files: */ 332 { .compatible = "qcom,kgsl-3d0" }, 333 {} 334 }; 335 336 #ifdef CONFIG_PM 337 static int adreno_resume(struct device *dev) 338 { 339 struct platform_device *pdev = to_platform_device(dev); 340 struct msm_gpu *gpu = platform_get_drvdata(pdev); 341 342 return gpu->funcs->pm_resume(gpu); 343 } 344 345 static int adreno_suspend(struct device *dev) 346 { 347 struct platform_device *pdev = to_platform_device(dev); 348 struct msm_gpu *gpu = platform_get_drvdata(pdev); 349 350 return gpu->funcs->pm_suspend(gpu); 351 } 352 #endif 353 354 static const struct dev_pm_ops adreno_pm_ops = { 355 SET_RUNTIME_PM_OPS(adreno_suspend, adreno_resume, NULL) 356 }; 357 358 static struct platform_driver adreno_driver = { 359 .probe = adreno_probe, 360 .remove = adreno_remove, 361 .driver = { 362 .name = "adreno", 363 .of_match_table = dt_match, 364 .pm = &adreno_pm_ops, 365 }, 366 }; 367 368 void __init adreno_register(void) 369 { 370 platform_driver_register(&adreno_driver); 371 } 372 373 void __exit adreno_unregister(void) 374 { 375 platform_driver_unregister(&adreno_driver); 376 } 377