1 /* 2 * Copyright (C) 2013-2014 Red Hat 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License version 2 as published by 9 * the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include <linux/pm_opp.h> 21 #include "adreno_gpu.h" 22 23 #define ANY_ID 0xff 24 25 bool hang_debug = false; 26 MODULE_PARM_DESC(hang_debug, "Dump registers when hang is detected (can be slow!)"); 27 module_param_named(hang_debug, hang_debug, bool, 0600); 28 29 static const struct adreno_info gpulist[] = { 30 { 31 .rev = ADRENO_REV(3, 0, 5, ANY_ID), 32 .revn = 305, 33 .name = "A305", 34 .pm4fw = "a300_pm4.fw", 35 .pfpfw = "a300_pfp.fw", 36 .gmem = SZ_256K, 37 .init = a3xx_gpu_init, 38 }, { 39 .rev = ADRENO_REV(3, 0, 6, 0), 40 .revn = 307, /* because a305c is revn==306 */ 41 .name = "A306", 42 .pm4fw = "a300_pm4.fw", 43 .pfpfw = "a300_pfp.fw", 44 .gmem = SZ_128K, 45 .init = a3xx_gpu_init, 46 }, { 47 .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID), 48 .revn = 320, 49 .name = "A320", 50 .pm4fw = "a300_pm4.fw", 51 .pfpfw = "a300_pfp.fw", 52 .gmem = SZ_512K, 53 .init = a3xx_gpu_init, 54 }, { 55 .rev = ADRENO_REV(3, 3, 0, ANY_ID), 56 .revn = 330, 57 .name = "A330", 58 .pm4fw = "a330_pm4.fw", 59 .pfpfw = "a330_pfp.fw", 60 .gmem = SZ_1M, 61 .init = a3xx_gpu_init, 62 }, { 63 .rev = ADRENO_REV(4, 2, 0, ANY_ID), 64 .revn = 420, 65 .name = "A420", 66 .pm4fw = "a420_pm4.fw", 67 .pfpfw = "a420_pfp.fw", 68 .gmem = (SZ_1M + SZ_512K), 69 .init = a4xx_gpu_init, 70 }, { 71 .rev = ADRENO_REV(4, 3, 0, ANY_ID), 72 .revn = 430, 73 .name = "A430", 74 .pm4fw = "a420_pm4.fw", 75 .pfpfw = "a420_pfp.fw", 76 .gmem = (SZ_1M + SZ_512K), 77 .init = a4xx_gpu_init, 78 }, { 79 .rev = ADRENO_REV(5, 3, 0, 2), 80 .revn = 530, 81 .name = "A530", 82 .pm4fw = "a530_pm4.fw", 83 .pfpfw = "a530_pfp.fw", 84 .gmem = SZ_1M, 85 .quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI | 86 ADRENO_QUIRK_FAULT_DETECT_MASK, 87 .init = a5xx_gpu_init, 88 .gpmufw = "a530v3_gpmu.fw2", 89 .zapfw = "a530_zap.mdt", 90 }, 91 }; 92 93 MODULE_FIRMWARE("a300_pm4.fw"); 94 MODULE_FIRMWARE("a300_pfp.fw"); 95 MODULE_FIRMWARE("a330_pm4.fw"); 96 MODULE_FIRMWARE("a330_pfp.fw"); 97 MODULE_FIRMWARE("a420_pm4.fw"); 98 MODULE_FIRMWARE("a420_pfp.fw"); 99 MODULE_FIRMWARE("a530_fm4.fw"); 100 MODULE_FIRMWARE("a530_pfp.fw"); 101 102 static inline bool _rev_match(uint8_t entry, uint8_t id) 103 { 104 return (entry == ANY_ID) || (entry == id); 105 } 106 107 const struct adreno_info *adreno_info(struct adreno_rev rev) 108 { 109 int i; 110 111 /* identify gpu: */ 112 for (i = 0; i < ARRAY_SIZE(gpulist); i++) { 113 const struct adreno_info *info = &gpulist[i]; 114 if (_rev_match(info->rev.core, rev.core) && 115 _rev_match(info->rev.major, rev.major) && 116 _rev_match(info->rev.minor, rev.minor) && 117 _rev_match(info->rev.patchid, rev.patchid)) 118 return info; 119 } 120 121 return NULL; 122 } 123 124 struct msm_gpu *adreno_load_gpu(struct drm_device *dev) 125 { 126 struct msm_drm_private *priv = dev->dev_private; 127 struct platform_device *pdev = priv->gpu_pdev; 128 struct adreno_platform_config *config; 129 struct adreno_rev rev; 130 const struct adreno_info *info; 131 struct msm_gpu *gpu = NULL; 132 133 if (!pdev) { 134 dev_err(dev->dev, "no adreno device\n"); 135 return NULL; 136 } 137 138 config = pdev->dev.platform_data; 139 rev = config->rev; 140 info = adreno_info(config->rev); 141 142 if (!info) { 143 dev_warn(dev->dev, "Unknown GPU revision: %u.%u.%u.%u\n", 144 rev.core, rev.major, rev.minor, rev.patchid); 145 return NULL; 146 } 147 148 DBG("Found GPU: %u.%u.%u.%u", rev.core, rev.major, 149 rev.minor, rev.patchid); 150 151 gpu = info->init(dev); 152 if (IS_ERR(gpu)) { 153 dev_warn(dev->dev, "failed to load adreno gpu\n"); 154 gpu = NULL; 155 /* not fatal */ 156 } 157 158 if (gpu) { 159 int ret; 160 161 pm_runtime_get_sync(&pdev->dev); 162 mutex_lock(&dev->struct_mutex); 163 ret = msm_gpu_hw_init(gpu); 164 mutex_unlock(&dev->struct_mutex); 165 pm_runtime_put_sync(&pdev->dev); 166 if (ret) { 167 dev_err(dev->dev, "gpu hw init failed: %d\n", ret); 168 gpu->funcs->destroy(gpu); 169 gpu = NULL; 170 } 171 } 172 173 return gpu; 174 } 175 176 static void set_gpu_pdev(struct drm_device *dev, 177 struct platform_device *pdev) 178 { 179 struct msm_drm_private *priv = dev->dev_private; 180 priv->gpu_pdev = pdev; 181 } 182 183 static int find_chipid(struct device *dev, u32 *chipid) 184 { 185 struct device_node *node = dev->of_node; 186 const char *compat; 187 int ret; 188 189 /* first search the compat strings for qcom,adreno-XYZ.W: */ 190 ret = of_property_read_string_index(node, "compatible", 0, &compat); 191 if (ret == 0) { 192 unsigned rev, patch; 193 194 if (sscanf(compat, "qcom,adreno-%u.%u", &rev, &patch) == 2) { 195 *chipid = 0; 196 *chipid |= (rev / 100) << 24; /* core */ 197 rev %= 100; 198 *chipid |= (rev / 10) << 16; /* major */ 199 rev %= 10; 200 *chipid |= rev << 8; /* minor */ 201 *chipid |= patch; 202 203 return 0; 204 } 205 } 206 207 /* and if that fails, fall back to legacy "qcom,chipid" property: */ 208 ret = of_property_read_u32(node, "qcom,chipid", chipid); 209 if (ret) 210 return ret; 211 212 dev_warn(dev, "Using legacy qcom,chipid binding!\n"); 213 dev_warn(dev, "Use compatible qcom,adreno-%u%u%u.%u instead.\n", 214 (*chipid >> 24) & 0xff, (*chipid >> 16) & 0xff, 215 (*chipid >> 8) & 0xff, *chipid & 0xff); 216 217 return 0; 218 } 219 220 /* Get legacy powerlevels from qcom,gpu-pwrlevels and populate the opp table */ 221 static int adreno_get_legacy_pwrlevels(struct device *dev) 222 { 223 struct device_node *child, *node; 224 int ret; 225 226 node = of_find_compatible_node(dev->of_node, NULL, 227 "qcom,gpu-pwrlevels"); 228 if (!node) { 229 dev_err(dev, "Could not find the GPU powerlevels\n"); 230 return -ENXIO; 231 } 232 233 for_each_child_of_node(node, child) { 234 unsigned int val; 235 236 ret = of_property_read_u32(child, "qcom,gpu-freq", &val); 237 if (ret) 238 continue; 239 240 /* 241 * Skip the intentionally bogus clock value found at the bottom 242 * of most legacy frequency tables 243 */ 244 if (val != 27000000) 245 dev_pm_opp_add(dev, val, 0); 246 } 247 248 return 0; 249 } 250 251 static int adreno_get_pwrlevels(struct device *dev, 252 struct adreno_platform_config *config) 253 { 254 unsigned long freq = ULONG_MAX; 255 struct dev_pm_opp *opp; 256 int ret; 257 258 /* You down with OPP? */ 259 if (!of_find_property(dev->of_node, "operating-points-v2", NULL)) 260 ret = adreno_get_legacy_pwrlevels(dev); 261 else 262 ret = dev_pm_opp_of_add_table(dev); 263 264 if (ret) 265 return ret; 266 267 /* Find the fastest defined rate */ 268 opp = dev_pm_opp_find_freq_floor(dev, &freq); 269 if (!IS_ERR(opp)) 270 config->fast_rate = dev_pm_opp_get_freq(opp); 271 272 if (!config->fast_rate) { 273 DRM_DEV_INFO(dev, 274 "Could not find clock rate. Using default\n"); 275 /* Pick a suitably safe clock speed for any target */ 276 config->fast_rate = 200000000; 277 } 278 279 return 0; 280 } 281 282 static int adreno_bind(struct device *dev, struct device *master, void *data) 283 { 284 static struct adreno_platform_config config = {}; 285 u32 val; 286 int ret; 287 288 ret = find_chipid(dev, &val); 289 if (ret) { 290 dev_err(dev, "could not find chipid: %d\n", ret); 291 return ret; 292 } 293 294 config.rev = ADRENO_REV((val >> 24) & 0xff, 295 (val >> 16) & 0xff, (val >> 8) & 0xff, val & 0xff); 296 297 /* find clock rates: */ 298 config.fast_rate = 0; 299 300 ret = adreno_get_pwrlevels(dev, &config); 301 if (ret) 302 return ret; 303 304 dev->platform_data = &config; 305 set_gpu_pdev(dev_get_drvdata(master), to_platform_device(dev)); 306 return 0; 307 } 308 309 static void adreno_unbind(struct device *dev, struct device *master, 310 void *data) 311 { 312 set_gpu_pdev(dev_get_drvdata(master), NULL); 313 } 314 315 static const struct component_ops a3xx_ops = { 316 .bind = adreno_bind, 317 .unbind = adreno_unbind, 318 }; 319 320 static int adreno_probe(struct platform_device *pdev) 321 { 322 return component_add(&pdev->dev, &a3xx_ops); 323 } 324 325 static int adreno_remove(struct platform_device *pdev) 326 { 327 component_del(&pdev->dev, &a3xx_ops); 328 return 0; 329 } 330 331 static const struct of_device_id dt_match[] = { 332 { .compatible = "qcom,adreno" }, 333 { .compatible = "qcom,adreno-3xx" }, 334 /* for backwards compat w/ downstream kgsl DT files: */ 335 { .compatible = "qcom,kgsl-3d0" }, 336 {} 337 }; 338 339 #ifdef CONFIG_PM 340 static int adreno_resume(struct device *dev) 341 { 342 struct platform_device *pdev = to_platform_device(dev); 343 struct msm_gpu *gpu = platform_get_drvdata(pdev); 344 345 return gpu->funcs->pm_resume(gpu); 346 } 347 348 static int adreno_suspend(struct device *dev) 349 { 350 struct platform_device *pdev = to_platform_device(dev); 351 struct msm_gpu *gpu = platform_get_drvdata(pdev); 352 353 return gpu->funcs->pm_suspend(gpu); 354 } 355 #endif 356 357 static const struct dev_pm_ops adreno_pm_ops = { 358 SET_RUNTIME_PM_OPS(adreno_suspend, adreno_resume, NULL) 359 }; 360 361 static struct platform_driver adreno_driver = { 362 .probe = adreno_probe, 363 .remove = adreno_remove, 364 .driver = { 365 .name = "adreno", 366 .of_match_table = dt_match, 367 .pm = &adreno_pm_ops, 368 }, 369 }; 370 371 void __init adreno_register(void) 372 { 373 platform_driver_register(&adreno_driver); 374 } 375 376 void __exit adreno_unregister(void) 377 { 378 platform_driver_unregister(&adreno_driver); 379 } 380