1 /* 2 * Copyright (C) 2013-2014 Red Hat 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License version 2 as published by 9 * the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "adreno_gpu.h" 21 22 #define ANY_ID 0xff 23 24 bool hang_debug = false; 25 MODULE_PARM_DESC(hang_debug, "Dump registers when hang is detected (can be slow!)"); 26 module_param_named(hang_debug, hang_debug, bool, 0600); 27 28 static const struct adreno_info gpulist[] = { 29 { 30 .rev = ADRENO_REV(2, 0, 0, 0), 31 .revn = 200, 32 .name = "A200", 33 .fw = { 34 [ADRENO_FW_PM4] = "yamato_pm4.fw", 35 [ADRENO_FW_PFP] = "yamato_pfp.fw", 36 }, 37 .gmem = SZ_256K, 38 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 39 .init = a2xx_gpu_init, 40 }, { /* a200 on i.mx51 has only 128kib gmem */ 41 .rev = ADRENO_REV(2, 0, 0, 1), 42 .revn = 201, 43 .name = "A200", 44 .fw = { 45 [ADRENO_FW_PM4] = "yamato_pm4.fw", 46 [ADRENO_FW_PFP] = "yamato_pfp.fw", 47 }, 48 .gmem = SZ_128K, 49 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 50 .init = a2xx_gpu_init, 51 }, { 52 .rev = ADRENO_REV(2, 2, 0, ANY_ID), 53 .revn = 220, 54 .name = "A220", 55 .fw = { 56 [ADRENO_FW_PM4] = "leia_pm4_470.fw", 57 [ADRENO_FW_PFP] = "leia_pfp_470.fw", 58 }, 59 .gmem = SZ_512K, 60 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 61 .init = a2xx_gpu_init, 62 }, { 63 .rev = ADRENO_REV(3, 0, 5, ANY_ID), 64 .revn = 305, 65 .name = "A305", 66 .fw = { 67 [ADRENO_FW_PM4] = "a300_pm4.fw", 68 [ADRENO_FW_PFP] = "a300_pfp.fw", 69 }, 70 .gmem = SZ_256K, 71 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 72 .init = a3xx_gpu_init, 73 }, { 74 .rev = ADRENO_REV(3, 0, 6, 0), 75 .revn = 307, /* because a305c is revn==306 */ 76 .name = "A306", 77 .fw = { 78 [ADRENO_FW_PM4] = "a300_pm4.fw", 79 [ADRENO_FW_PFP] = "a300_pfp.fw", 80 }, 81 .gmem = SZ_128K, 82 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 83 .init = a3xx_gpu_init, 84 }, { 85 .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID), 86 .revn = 320, 87 .name = "A320", 88 .fw = { 89 [ADRENO_FW_PM4] = "a300_pm4.fw", 90 [ADRENO_FW_PFP] = "a300_pfp.fw", 91 }, 92 .gmem = SZ_512K, 93 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 94 .init = a3xx_gpu_init, 95 }, { 96 .rev = ADRENO_REV(3, 3, 0, ANY_ID), 97 .revn = 330, 98 .name = "A330", 99 .fw = { 100 [ADRENO_FW_PM4] = "a330_pm4.fw", 101 [ADRENO_FW_PFP] = "a330_pfp.fw", 102 }, 103 .gmem = SZ_1M, 104 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 105 .init = a3xx_gpu_init, 106 }, { 107 .rev = ADRENO_REV(4, 2, 0, ANY_ID), 108 .revn = 420, 109 .name = "A420", 110 .fw = { 111 [ADRENO_FW_PM4] = "a420_pm4.fw", 112 [ADRENO_FW_PFP] = "a420_pfp.fw", 113 }, 114 .gmem = (SZ_1M + SZ_512K), 115 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 116 .init = a4xx_gpu_init, 117 }, { 118 .rev = ADRENO_REV(4, 3, 0, ANY_ID), 119 .revn = 430, 120 .name = "A430", 121 .fw = { 122 [ADRENO_FW_PM4] = "a420_pm4.fw", 123 [ADRENO_FW_PFP] = "a420_pfp.fw", 124 }, 125 .gmem = (SZ_1M + SZ_512K), 126 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 127 .init = a4xx_gpu_init, 128 }, { 129 .rev = ADRENO_REV(5, 3, 0, 2), 130 .revn = 530, 131 .name = "A530", 132 .fw = { 133 [ADRENO_FW_PM4] = "a530_pm4.fw", 134 [ADRENO_FW_PFP] = "a530_pfp.fw", 135 [ADRENO_FW_GPMU] = "a530v3_gpmu.fw2", 136 }, 137 .gmem = SZ_1M, 138 /* 139 * Increase inactive period to 250 to avoid bouncing 140 * the GDSC which appears to make it grumpy 141 */ 142 .inactive_period = 250, 143 .quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI | 144 ADRENO_QUIRK_FAULT_DETECT_MASK, 145 .init = a5xx_gpu_init, 146 .zapfw = "a530_zap.mdt", 147 }, { 148 .rev = ADRENO_REV(6, 3, 0, ANY_ID), 149 .revn = 630, 150 .name = "A630", 151 .fw = { 152 [ADRENO_FW_SQE] = "a630_sqe.fw", 153 [ADRENO_FW_GMU] = "a630_gmu.bin", 154 }, 155 .gmem = SZ_1M, 156 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 157 .init = a6xx_gpu_init, 158 .zapfw = "a630_zap.mdt", 159 }, 160 }; 161 162 MODULE_FIRMWARE("qcom/a300_pm4.fw"); 163 MODULE_FIRMWARE("qcom/a300_pfp.fw"); 164 MODULE_FIRMWARE("qcom/a330_pm4.fw"); 165 MODULE_FIRMWARE("qcom/a330_pfp.fw"); 166 MODULE_FIRMWARE("qcom/a420_pm4.fw"); 167 MODULE_FIRMWARE("qcom/a420_pfp.fw"); 168 MODULE_FIRMWARE("qcom/a530_pm4.fw"); 169 MODULE_FIRMWARE("qcom/a530_pfp.fw"); 170 MODULE_FIRMWARE("qcom/a530v3_gpmu.fw2"); 171 MODULE_FIRMWARE("qcom/a530_zap.mdt"); 172 MODULE_FIRMWARE("qcom/a530_zap.b00"); 173 MODULE_FIRMWARE("qcom/a530_zap.b01"); 174 MODULE_FIRMWARE("qcom/a530_zap.b02"); 175 MODULE_FIRMWARE("qcom/a630_sqe.fw"); 176 MODULE_FIRMWARE("qcom/a630_gmu.bin"); 177 178 static inline bool _rev_match(uint8_t entry, uint8_t id) 179 { 180 return (entry == ANY_ID) || (entry == id); 181 } 182 183 const struct adreno_info *adreno_info(struct adreno_rev rev) 184 { 185 int i; 186 187 /* identify gpu: */ 188 for (i = 0; i < ARRAY_SIZE(gpulist); i++) { 189 const struct adreno_info *info = &gpulist[i]; 190 if (_rev_match(info->rev.core, rev.core) && 191 _rev_match(info->rev.major, rev.major) && 192 _rev_match(info->rev.minor, rev.minor) && 193 _rev_match(info->rev.patchid, rev.patchid)) 194 return info; 195 } 196 197 return NULL; 198 } 199 200 struct msm_gpu *adreno_load_gpu(struct drm_device *dev) 201 { 202 struct msm_drm_private *priv = dev->dev_private; 203 struct platform_device *pdev = priv->gpu_pdev; 204 struct msm_gpu *gpu = NULL; 205 struct adreno_gpu *adreno_gpu; 206 int ret; 207 208 if (pdev) 209 gpu = platform_get_drvdata(pdev); 210 211 if (!gpu) { 212 dev_err_once(dev->dev, "no GPU device was found\n"); 213 return NULL; 214 } 215 216 adreno_gpu = to_adreno_gpu(gpu); 217 218 /* 219 * The number one reason for HW init to fail is if the firmware isn't 220 * loaded yet. Try that first and don't bother continuing on 221 * otherwise 222 */ 223 224 ret = adreno_load_fw(adreno_gpu); 225 if (ret) 226 return NULL; 227 228 /* Make sure pm runtime is active and reset any previous errors */ 229 pm_runtime_set_active(&pdev->dev); 230 231 ret = pm_runtime_get_sync(&pdev->dev); 232 if (ret < 0) { 233 pm_runtime_put_sync(&pdev->dev); 234 DRM_DEV_ERROR(dev->dev, "Couldn't power up the GPU: %d\n", ret); 235 return NULL; 236 } 237 238 mutex_lock(&dev->struct_mutex); 239 ret = msm_gpu_hw_init(gpu); 240 mutex_unlock(&dev->struct_mutex); 241 pm_runtime_put_autosuspend(&pdev->dev); 242 if (ret) { 243 DRM_DEV_ERROR(dev->dev, "gpu hw init failed: %d\n", ret); 244 return NULL; 245 } 246 247 #ifdef CONFIG_DEBUG_FS 248 if (gpu->funcs->debugfs_init) { 249 gpu->funcs->debugfs_init(gpu, dev->primary); 250 gpu->funcs->debugfs_init(gpu, dev->render); 251 } 252 #endif 253 254 return gpu; 255 } 256 257 static void set_gpu_pdev(struct drm_device *dev, 258 struct platform_device *pdev) 259 { 260 struct msm_drm_private *priv = dev->dev_private; 261 priv->gpu_pdev = pdev; 262 } 263 264 static int find_chipid(struct device *dev, struct adreno_rev *rev) 265 { 266 struct device_node *node = dev->of_node; 267 const char *compat; 268 int ret; 269 u32 chipid; 270 271 /* first search the compat strings for qcom,adreno-XYZ.W: */ 272 ret = of_property_read_string_index(node, "compatible", 0, &compat); 273 if (ret == 0) { 274 unsigned int r, patch; 275 276 if (sscanf(compat, "qcom,adreno-%u.%u", &r, &patch) == 2 || 277 sscanf(compat, "amd,imageon-%u.%u", &r, &patch) == 2) { 278 rev->core = r / 100; 279 r %= 100; 280 rev->major = r / 10; 281 r %= 10; 282 rev->minor = r; 283 rev->patchid = patch; 284 285 return 0; 286 } 287 } 288 289 /* and if that fails, fall back to legacy "qcom,chipid" property: */ 290 ret = of_property_read_u32(node, "qcom,chipid", &chipid); 291 if (ret) { 292 DRM_DEV_ERROR(dev, "could not parse qcom,chipid: %d\n", ret); 293 return ret; 294 } 295 296 rev->core = (chipid >> 24) & 0xff; 297 rev->major = (chipid >> 16) & 0xff; 298 rev->minor = (chipid >> 8) & 0xff; 299 rev->patchid = (chipid & 0xff); 300 301 dev_warn(dev, "Using legacy qcom,chipid binding!\n"); 302 dev_warn(dev, "Use compatible qcom,adreno-%u%u%u.%u instead.\n", 303 rev->core, rev->major, rev->minor, rev->patchid); 304 305 return 0; 306 } 307 308 static int adreno_bind(struct device *dev, struct device *master, void *data) 309 { 310 static struct adreno_platform_config config = {}; 311 const struct adreno_info *info; 312 struct drm_device *drm = dev_get_drvdata(master); 313 struct msm_drm_private *priv = drm->dev_private; 314 struct msm_gpu *gpu; 315 int ret; 316 317 ret = find_chipid(dev, &config.rev); 318 if (ret) 319 return ret; 320 321 dev->platform_data = &config; 322 set_gpu_pdev(drm, to_platform_device(dev)); 323 324 info = adreno_info(config.rev); 325 326 if (!info) { 327 dev_warn(drm->dev, "Unknown GPU revision: %u.%u.%u.%u\n", 328 config.rev.core, config.rev.major, 329 config.rev.minor, config.rev.patchid); 330 return -ENXIO; 331 } 332 333 DBG("Found GPU: %u.%u.%u.%u", config.rev.core, config.rev.major, 334 config.rev.minor, config.rev.patchid); 335 336 priv->is_a2xx = config.rev.core == 2; 337 338 gpu = info->init(drm); 339 if (IS_ERR(gpu)) { 340 dev_warn(drm->dev, "failed to load adreno gpu\n"); 341 return PTR_ERR(gpu); 342 } 343 344 dev_set_drvdata(dev, gpu); 345 346 return 0; 347 } 348 349 static void adreno_unbind(struct device *dev, struct device *master, 350 void *data) 351 { 352 struct msm_gpu *gpu = dev_get_drvdata(dev); 353 354 gpu->funcs->pm_suspend(gpu); 355 gpu->funcs->destroy(gpu); 356 357 set_gpu_pdev(dev_get_drvdata(master), NULL); 358 } 359 360 static const struct component_ops a3xx_ops = { 361 .bind = adreno_bind, 362 .unbind = adreno_unbind, 363 }; 364 365 static void adreno_device_register_headless(void) 366 { 367 /* on imx5, we don't have a top-level mdp/dpu node 368 * this creates a dummy node for the driver for that case 369 */ 370 struct platform_device_info dummy_info = { 371 .parent = NULL, 372 .name = "msm", 373 .id = -1, 374 .res = NULL, 375 .num_res = 0, 376 .data = NULL, 377 .size_data = 0, 378 .dma_mask = ~0, 379 }; 380 platform_device_register_full(&dummy_info); 381 } 382 383 static int adreno_probe(struct platform_device *pdev) 384 { 385 386 int ret; 387 388 ret = component_add(&pdev->dev, &a3xx_ops); 389 if (ret) 390 return ret; 391 392 if (of_device_is_compatible(pdev->dev.of_node, "amd,imageon")) 393 adreno_device_register_headless(); 394 395 return 0; 396 } 397 398 static int adreno_remove(struct platform_device *pdev) 399 { 400 component_del(&pdev->dev, &a3xx_ops); 401 return 0; 402 } 403 404 static const struct of_device_id dt_match[] = { 405 { .compatible = "qcom,adreno" }, 406 { .compatible = "qcom,adreno-3xx" }, 407 /* for compatibility with imx5 gpu: */ 408 { .compatible = "amd,imageon" }, 409 /* for backwards compat w/ downstream kgsl DT files: */ 410 { .compatible = "qcom,kgsl-3d0" }, 411 {} 412 }; 413 414 #ifdef CONFIG_PM 415 static int adreno_resume(struct device *dev) 416 { 417 struct platform_device *pdev = to_platform_device(dev); 418 struct msm_gpu *gpu = platform_get_drvdata(pdev); 419 420 return gpu->funcs->pm_resume(gpu); 421 } 422 423 static int adreno_suspend(struct device *dev) 424 { 425 struct platform_device *pdev = to_platform_device(dev); 426 struct msm_gpu *gpu = platform_get_drvdata(pdev); 427 428 return gpu->funcs->pm_suspend(gpu); 429 } 430 #endif 431 432 static const struct dev_pm_ops adreno_pm_ops = { 433 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) 434 SET_RUNTIME_PM_OPS(adreno_suspend, adreno_resume, NULL) 435 }; 436 437 static struct platform_driver adreno_driver = { 438 .probe = adreno_probe, 439 .remove = adreno_remove, 440 .driver = { 441 .name = "adreno", 442 .of_match_table = dt_match, 443 .pm = &adreno_pm_ops, 444 }, 445 }; 446 447 void __init adreno_register(void) 448 { 449 platform_driver_register(&adreno_driver); 450 } 451 452 void __exit adreno_unregister(void) 453 { 454 platform_driver_unregister(&adreno_driver); 455 } 456