1 /* 2 * Copyright (C) 2013-2014 Red Hat 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License version 2 as published by 9 * the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "adreno_gpu.h" 21 22 #define ANY_ID 0xff 23 24 bool hang_debug = false; 25 MODULE_PARM_DESC(hang_debug, "Dump registers when hang is detected (can be slow!)"); 26 module_param_named(hang_debug, hang_debug, bool, 0600); 27 28 static const struct adreno_info gpulist[] = { 29 { 30 .rev = ADRENO_REV(3, 0, 5, ANY_ID), 31 .revn = 305, 32 .name = "A305", 33 .fw = { 34 [ADRENO_FW_PM4] = "a300_pm4.fw", 35 [ADRENO_FW_PFP] = "a300_pfp.fw", 36 }, 37 .gmem = SZ_256K, 38 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 39 .init = a3xx_gpu_init, 40 }, { 41 .rev = ADRENO_REV(3, 0, 6, 0), 42 .revn = 307, /* because a305c is revn==306 */ 43 .name = "A306", 44 .fw = { 45 [ADRENO_FW_PM4] = "a300_pm4.fw", 46 [ADRENO_FW_PFP] = "a300_pfp.fw", 47 }, 48 .gmem = SZ_128K, 49 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 50 .init = a3xx_gpu_init, 51 }, { 52 .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID), 53 .revn = 320, 54 .name = "A320", 55 .fw = { 56 [ADRENO_FW_PM4] = "a300_pm4.fw", 57 [ADRENO_FW_PFP] = "a300_pfp.fw", 58 }, 59 .gmem = SZ_512K, 60 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 61 .init = a3xx_gpu_init, 62 }, { 63 .rev = ADRENO_REV(3, 3, 0, ANY_ID), 64 .revn = 330, 65 .name = "A330", 66 .fw = { 67 [ADRENO_FW_PM4] = "a330_pm4.fw", 68 [ADRENO_FW_PFP] = "a330_pfp.fw", 69 }, 70 .gmem = SZ_1M, 71 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 72 .init = a3xx_gpu_init, 73 }, { 74 .rev = ADRENO_REV(4, 2, 0, ANY_ID), 75 .revn = 420, 76 .name = "A420", 77 .fw = { 78 [ADRENO_FW_PM4] = "a420_pm4.fw", 79 [ADRENO_FW_PFP] = "a420_pfp.fw", 80 }, 81 .gmem = (SZ_1M + SZ_512K), 82 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 83 .init = a4xx_gpu_init, 84 }, { 85 .rev = ADRENO_REV(4, 3, 0, ANY_ID), 86 .revn = 430, 87 .name = "A430", 88 .fw = { 89 [ADRENO_FW_PM4] = "a420_pm4.fw", 90 [ADRENO_FW_PFP] = "a420_pfp.fw", 91 }, 92 .gmem = (SZ_1M + SZ_512K), 93 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 94 .init = a4xx_gpu_init, 95 }, { 96 .rev = ADRENO_REV(5, 3, 0, 2), 97 .revn = 530, 98 .name = "A530", 99 .fw = { 100 [ADRENO_FW_PM4] = "a530_pm4.fw", 101 [ADRENO_FW_PFP] = "a530_pfp.fw", 102 [ADRENO_FW_GPMU] = "a530v3_gpmu.fw2", 103 }, 104 .gmem = SZ_1M, 105 /* 106 * Increase inactive period to 250 to avoid bouncing 107 * the GDSC which appears to make it grumpy 108 */ 109 .inactive_period = 250, 110 .quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI | 111 ADRENO_QUIRK_FAULT_DETECT_MASK, 112 .init = a5xx_gpu_init, 113 .zapfw = "a530_zap.mdt", 114 }, { 115 .rev = ADRENO_REV(6, 3, 0, ANY_ID), 116 .revn = 630, 117 .name = "A630", 118 .fw = { 119 [ADRENO_FW_SQE] = "a630_sqe.fw", 120 [ADRENO_FW_GMU] = "a630_gmu.bin", 121 }, 122 .gmem = SZ_1M, 123 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 124 .init = a6xx_gpu_init, 125 }, 126 }; 127 128 MODULE_FIRMWARE("qcom/a300_pm4.fw"); 129 MODULE_FIRMWARE("qcom/a300_pfp.fw"); 130 MODULE_FIRMWARE("qcom/a330_pm4.fw"); 131 MODULE_FIRMWARE("qcom/a330_pfp.fw"); 132 MODULE_FIRMWARE("qcom/a420_pm4.fw"); 133 MODULE_FIRMWARE("qcom/a420_pfp.fw"); 134 MODULE_FIRMWARE("qcom/a530_pm4.fw"); 135 MODULE_FIRMWARE("qcom/a530_pfp.fw"); 136 MODULE_FIRMWARE("qcom/a530v3_gpmu.fw2"); 137 MODULE_FIRMWARE("qcom/a530_zap.mdt"); 138 MODULE_FIRMWARE("qcom/a530_zap.b00"); 139 MODULE_FIRMWARE("qcom/a530_zap.b01"); 140 MODULE_FIRMWARE("qcom/a530_zap.b02"); 141 MODULE_FIRMWARE("qcom/a630_sqe.fw"); 142 MODULE_FIRMWARE("qcom/a630_gmu.bin"); 143 144 static inline bool _rev_match(uint8_t entry, uint8_t id) 145 { 146 return (entry == ANY_ID) || (entry == id); 147 } 148 149 const struct adreno_info *adreno_info(struct adreno_rev rev) 150 { 151 int i; 152 153 /* identify gpu: */ 154 for (i = 0; i < ARRAY_SIZE(gpulist); i++) { 155 const struct adreno_info *info = &gpulist[i]; 156 if (_rev_match(info->rev.core, rev.core) && 157 _rev_match(info->rev.major, rev.major) && 158 _rev_match(info->rev.minor, rev.minor) && 159 _rev_match(info->rev.patchid, rev.patchid)) 160 return info; 161 } 162 163 return NULL; 164 } 165 166 struct msm_gpu *adreno_load_gpu(struct drm_device *dev) 167 { 168 struct msm_drm_private *priv = dev->dev_private; 169 struct platform_device *pdev = priv->gpu_pdev; 170 struct msm_gpu *gpu = NULL; 171 struct adreno_gpu *adreno_gpu; 172 int ret; 173 174 if (pdev) 175 gpu = platform_get_drvdata(pdev); 176 177 if (!gpu) { 178 dev_err_once(dev->dev, "no GPU device was found\n"); 179 return NULL; 180 } 181 182 adreno_gpu = to_adreno_gpu(gpu); 183 184 /* 185 * The number one reason for HW init to fail is if the firmware isn't 186 * loaded yet. Try that first and don't bother continuing on 187 * otherwise 188 */ 189 190 ret = adreno_load_fw(adreno_gpu); 191 if (ret) 192 return NULL; 193 194 /* Make sure pm runtime is active and reset any previous errors */ 195 pm_runtime_set_active(&pdev->dev); 196 197 ret = pm_runtime_get_sync(&pdev->dev); 198 if (ret < 0) { 199 dev_err(dev->dev, "Couldn't power up the GPU: %d\n", ret); 200 return NULL; 201 } 202 203 mutex_lock(&dev->struct_mutex); 204 ret = msm_gpu_hw_init(gpu); 205 mutex_unlock(&dev->struct_mutex); 206 pm_runtime_put_autosuspend(&pdev->dev); 207 if (ret) { 208 dev_err(dev->dev, "gpu hw init failed: %d\n", ret); 209 return NULL; 210 } 211 212 #ifdef CONFIG_DEBUG_FS 213 if (gpu->funcs->debugfs_init) { 214 gpu->funcs->debugfs_init(gpu, dev->primary); 215 gpu->funcs->debugfs_init(gpu, dev->render); 216 } 217 #endif 218 219 return gpu; 220 } 221 222 static void set_gpu_pdev(struct drm_device *dev, 223 struct platform_device *pdev) 224 { 225 struct msm_drm_private *priv = dev->dev_private; 226 priv->gpu_pdev = pdev; 227 } 228 229 static int find_chipid(struct device *dev, struct adreno_rev *rev) 230 { 231 struct device_node *node = dev->of_node; 232 const char *compat; 233 int ret; 234 u32 chipid; 235 236 /* first search the compat strings for qcom,adreno-XYZ.W: */ 237 ret = of_property_read_string_index(node, "compatible", 0, &compat); 238 if (ret == 0) { 239 unsigned int r, patch; 240 241 if (sscanf(compat, "qcom,adreno-%u.%u", &r, &patch) == 2) { 242 rev->core = r / 100; 243 r %= 100; 244 rev->major = r / 10; 245 r %= 10; 246 rev->minor = r; 247 rev->patchid = patch; 248 249 return 0; 250 } 251 } 252 253 /* and if that fails, fall back to legacy "qcom,chipid" property: */ 254 ret = of_property_read_u32(node, "qcom,chipid", &chipid); 255 if (ret) { 256 dev_err(dev, "could not parse qcom,chipid: %d\n", ret); 257 return ret; 258 } 259 260 rev->core = (chipid >> 24) & 0xff; 261 rev->major = (chipid >> 16) & 0xff; 262 rev->minor = (chipid >> 8) & 0xff; 263 rev->patchid = (chipid & 0xff); 264 265 dev_warn(dev, "Using legacy qcom,chipid binding!\n"); 266 dev_warn(dev, "Use compatible qcom,adreno-%u%u%u.%u instead.\n", 267 rev->core, rev->major, rev->minor, rev->patchid); 268 269 return 0; 270 } 271 272 static int adreno_bind(struct device *dev, struct device *master, void *data) 273 { 274 static struct adreno_platform_config config = {}; 275 const struct adreno_info *info; 276 struct drm_device *drm = dev_get_drvdata(master); 277 struct msm_gpu *gpu; 278 int ret; 279 280 ret = find_chipid(dev, &config.rev); 281 if (ret) 282 return ret; 283 284 dev->platform_data = &config; 285 set_gpu_pdev(drm, to_platform_device(dev)); 286 287 info = adreno_info(config.rev); 288 289 if (!info) { 290 dev_warn(drm->dev, "Unknown GPU revision: %u.%u.%u.%u\n", 291 config.rev.core, config.rev.major, 292 config.rev.minor, config.rev.patchid); 293 return -ENXIO; 294 } 295 296 DBG("Found GPU: %u.%u.%u.%u", config.rev.core, config.rev.major, 297 config.rev.minor, config.rev.patchid); 298 299 gpu = info->init(drm); 300 if (IS_ERR(gpu)) { 301 dev_warn(drm->dev, "failed to load adreno gpu\n"); 302 return PTR_ERR(gpu); 303 } 304 305 dev_set_drvdata(dev, gpu); 306 307 return 0; 308 } 309 310 static void adreno_unbind(struct device *dev, struct device *master, 311 void *data) 312 { 313 struct msm_gpu *gpu = dev_get_drvdata(dev); 314 315 gpu->funcs->pm_suspend(gpu); 316 gpu->funcs->destroy(gpu); 317 318 set_gpu_pdev(dev_get_drvdata(master), NULL); 319 } 320 321 static const struct component_ops a3xx_ops = { 322 .bind = adreno_bind, 323 .unbind = adreno_unbind, 324 }; 325 326 static int adreno_probe(struct platform_device *pdev) 327 { 328 return component_add(&pdev->dev, &a3xx_ops); 329 } 330 331 static int adreno_remove(struct platform_device *pdev) 332 { 333 component_del(&pdev->dev, &a3xx_ops); 334 return 0; 335 } 336 337 static const struct of_device_id dt_match[] = { 338 { .compatible = "qcom,adreno" }, 339 { .compatible = "qcom,adreno-3xx" }, 340 /* for backwards compat w/ downstream kgsl DT files: */ 341 { .compatible = "qcom,kgsl-3d0" }, 342 {} 343 }; 344 345 #ifdef CONFIG_PM 346 static int adreno_resume(struct device *dev) 347 { 348 struct platform_device *pdev = to_platform_device(dev); 349 struct msm_gpu *gpu = platform_get_drvdata(pdev); 350 351 return gpu->funcs->pm_resume(gpu); 352 } 353 354 static int adreno_suspend(struct device *dev) 355 { 356 struct platform_device *pdev = to_platform_device(dev); 357 struct msm_gpu *gpu = platform_get_drvdata(pdev); 358 359 return gpu->funcs->pm_suspend(gpu); 360 } 361 #endif 362 363 static const struct dev_pm_ops adreno_pm_ops = { 364 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) 365 SET_RUNTIME_PM_OPS(adreno_suspend, adreno_resume, NULL) 366 }; 367 368 static struct platform_driver adreno_driver = { 369 .probe = adreno_probe, 370 .remove = adreno_remove, 371 .driver = { 372 .name = "adreno", 373 .of_match_table = dt_match, 374 .pm = &adreno_pm_ops, 375 }, 376 }; 377 378 void __init adreno_register(void) 379 { 380 platform_driver_register(&adreno_driver); 381 } 382 383 void __exit adreno_unregister(void) 384 { 385 platform_driver_unregister(&adreno_driver); 386 } 387