1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013-2014 Red Hat 4 * Author: Rob Clark <robdclark@gmail.com> 5 * 6 * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved. 7 */ 8 9 #include "adreno_gpu.h" 10 11 #define ANY_ID 0xff 12 13 bool hang_debug = false; 14 MODULE_PARM_DESC(hang_debug, "Dump registers when hang is detected (can be slow!)"); 15 module_param_named(hang_debug, hang_debug, bool, 0600); 16 17 static const struct adreno_info gpulist[] = { 18 { 19 .rev = ADRENO_REV(2, 0, 0, 0), 20 .revn = 200, 21 .name = "A200", 22 .fw = { 23 [ADRENO_FW_PM4] = "yamato_pm4.fw", 24 [ADRENO_FW_PFP] = "yamato_pfp.fw", 25 }, 26 .gmem = SZ_256K, 27 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 28 .init = a2xx_gpu_init, 29 }, { /* a200 on i.mx51 has only 128kib gmem */ 30 .rev = ADRENO_REV(2, 0, 0, 1), 31 .revn = 201, 32 .name = "A200", 33 .fw = { 34 [ADRENO_FW_PM4] = "yamato_pm4.fw", 35 [ADRENO_FW_PFP] = "yamato_pfp.fw", 36 }, 37 .gmem = SZ_128K, 38 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 39 .init = a2xx_gpu_init, 40 }, { 41 .rev = ADRENO_REV(2, 2, 0, ANY_ID), 42 .revn = 220, 43 .name = "A220", 44 .fw = { 45 [ADRENO_FW_PM4] = "leia_pm4_470.fw", 46 [ADRENO_FW_PFP] = "leia_pfp_470.fw", 47 }, 48 .gmem = SZ_512K, 49 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 50 .init = a2xx_gpu_init, 51 }, { 52 .rev = ADRENO_REV(3, 0, 5, ANY_ID), 53 .revn = 305, 54 .name = "A305", 55 .fw = { 56 [ADRENO_FW_PM4] = "a300_pm4.fw", 57 [ADRENO_FW_PFP] = "a300_pfp.fw", 58 }, 59 .gmem = SZ_256K, 60 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 61 .init = a3xx_gpu_init, 62 }, { 63 .rev = ADRENO_REV(3, 0, 6, 0), 64 .revn = 307, /* because a305c is revn==306 */ 65 .name = "A306", 66 .fw = { 67 [ADRENO_FW_PM4] = "a300_pm4.fw", 68 [ADRENO_FW_PFP] = "a300_pfp.fw", 69 }, 70 .gmem = SZ_128K, 71 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 72 .init = a3xx_gpu_init, 73 }, { 74 .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID), 75 .revn = 320, 76 .name = "A320", 77 .fw = { 78 [ADRENO_FW_PM4] = "a300_pm4.fw", 79 [ADRENO_FW_PFP] = "a300_pfp.fw", 80 }, 81 .gmem = SZ_512K, 82 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 83 .init = a3xx_gpu_init, 84 }, { 85 .rev = ADRENO_REV(3, 3, 0, ANY_ID), 86 .revn = 330, 87 .name = "A330", 88 .fw = { 89 [ADRENO_FW_PM4] = "a330_pm4.fw", 90 [ADRENO_FW_PFP] = "a330_pfp.fw", 91 }, 92 .gmem = SZ_1M, 93 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 94 .init = a3xx_gpu_init, 95 }, { 96 .rev = ADRENO_REV(4, 2, 0, ANY_ID), 97 .revn = 420, 98 .name = "A420", 99 .fw = { 100 [ADRENO_FW_PM4] = "a420_pm4.fw", 101 [ADRENO_FW_PFP] = "a420_pfp.fw", 102 }, 103 .gmem = (SZ_1M + SZ_512K), 104 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 105 .init = a4xx_gpu_init, 106 }, { 107 .rev = ADRENO_REV(4, 3, 0, ANY_ID), 108 .revn = 430, 109 .name = "A430", 110 .fw = { 111 [ADRENO_FW_PM4] = "a420_pm4.fw", 112 [ADRENO_FW_PFP] = "a420_pfp.fw", 113 }, 114 .gmem = (SZ_1M + SZ_512K), 115 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 116 .init = a4xx_gpu_init, 117 }, { 118 .rev = ADRENO_REV(5, 3, 0, 2), 119 .revn = 530, 120 .name = "A530", 121 .fw = { 122 [ADRENO_FW_PM4] = "a530_pm4.fw", 123 [ADRENO_FW_PFP] = "a530_pfp.fw", 124 [ADRENO_FW_GPMU] = "a530v3_gpmu.fw2", 125 }, 126 .gmem = SZ_1M, 127 /* 128 * Increase inactive period to 250 to avoid bouncing 129 * the GDSC which appears to make it grumpy 130 */ 131 .inactive_period = 250, 132 .quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI | 133 ADRENO_QUIRK_FAULT_DETECT_MASK, 134 .init = a5xx_gpu_init, 135 .zapfw = "a530_zap.mdt", 136 }, { 137 .rev = ADRENO_REV(5, 4, 0, 2), 138 .revn = 540, 139 .name = "A540", 140 .fw = { 141 [ADRENO_FW_PM4] = "a530_pm4.fw", 142 [ADRENO_FW_PFP] = "a530_pfp.fw", 143 [ADRENO_FW_GPMU] = "a540_gpmu.fw2", 144 }, 145 .gmem = SZ_1M, 146 /* 147 * Increase inactive period to 250 to avoid bouncing 148 * the GDSC which appears to make it grumpy 149 */ 150 .inactive_period = 250, 151 .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE, 152 .init = a5xx_gpu_init, 153 .zapfw = "a540_zap.mdt", 154 }, { 155 .rev = ADRENO_REV(6, 3, 0, ANY_ID), 156 .revn = 630, 157 .name = "A630", 158 .fw = { 159 [ADRENO_FW_SQE] = "a630_sqe.fw", 160 [ADRENO_FW_GMU] = "a630_gmu.bin", 161 }, 162 .gmem = SZ_1M, 163 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 164 .init = a6xx_gpu_init, 165 .zapfw = "a630_zap.mdt", 166 }, 167 }; 168 169 MODULE_FIRMWARE("qcom/a300_pm4.fw"); 170 MODULE_FIRMWARE("qcom/a300_pfp.fw"); 171 MODULE_FIRMWARE("qcom/a330_pm4.fw"); 172 MODULE_FIRMWARE("qcom/a330_pfp.fw"); 173 MODULE_FIRMWARE("qcom/a420_pm4.fw"); 174 MODULE_FIRMWARE("qcom/a420_pfp.fw"); 175 MODULE_FIRMWARE("qcom/a530_pm4.fw"); 176 MODULE_FIRMWARE("qcom/a530_pfp.fw"); 177 MODULE_FIRMWARE("qcom/a530v3_gpmu.fw2"); 178 MODULE_FIRMWARE("qcom/a530_zap.mdt"); 179 MODULE_FIRMWARE("qcom/a530_zap.b00"); 180 MODULE_FIRMWARE("qcom/a530_zap.b01"); 181 MODULE_FIRMWARE("qcom/a530_zap.b02"); 182 MODULE_FIRMWARE("qcom/a630_sqe.fw"); 183 MODULE_FIRMWARE("qcom/a630_gmu.bin"); 184 MODULE_FIRMWARE("qcom/a630_zap.mbn"); 185 186 static inline bool _rev_match(uint8_t entry, uint8_t id) 187 { 188 return (entry == ANY_ID) || (entry == id); 189 } 190 191 const struct adreno_info *adreno_info(struct adreno_rev rev) 192 { 193 int i; 194 195 /* identify gpu: */ 196 for (i = 0; i < ARRAY_SIZE(gpulist); i++) { 197 const struct adreno_info *info = &gpulist[i]; 198 if (_rev_match(info->rev.core, rev.core) && 199 _rev_match(info->rev.major, rev.major) && 200 _rev_match(info->rev.minor, rev.minor) && 201 _rev_match(info->rev.patchid, rev.patchid)) 202 return info; 203 } 204 205 return NULL; 206 } 207 208 struct msm_gpu *adreno_load_gpu(struct drm_device *dev) 209 { 210 struct msm_drm_private *priv = dev->dev_private; 211 struct platform_device *pdev = priv->gpu_pdev; 212 struct msm_gpu *gpu = NULL; 213 struct adreno_gpu *adreno_gpu; 214 int ret; 215 216 if (pdev) 217 gpu = platform_get_drvdata(pdev); 218 219 if (!gpu) { 220 dev_err_once(dev->dev, "no GPU device was found\n"); 221 return NULL; 222 } 223 224 adreno_gpu = to_adreno_gpu(gpu); 225 226 /* 227 * The number one reason for HW init to fail is if the firmware isn't 228 * loaded yet. Try that first and don't bother continuing on 229 * otherwise 230 */ 231 232 ret = adreno_load_fw(adreno_gpu); 233 if (ret) 234 return NULL; 235 236 /* Make sure pm runtime is active and reset any previous errors */ 237 pm_runtime_set_active(&pdev->dev); 238 239 ret = pm_runtime_get_sync(&pdev->dev); 240 if (ret < 0) { 241 pm_runtime_put_sync(&pdev->dev); 242 DRM_DEV_ERROR(dev->dev, "Couldn't power up the GPU: %d\n", ret); 243 return NULL; 244 } 245 246 mutex_lock(&dev->struct_mutex); 247 ret = msm_gpu_hw_init(gpu); 248 mutex_unlock(&dev->struct_mutex); 249 pm_runtime_put_autosuspend(&pdev->dev); 250 if (ret) { 251 DRM_DEV_ERROR(dev->dev, "gpu hw init failed: %d\n", ret); 252 return NULL; 253 } 254 255 #ifdef CONFIG_DEBUG_FS 256 if (gpu->funcs->debugfs_init) { 257 gpu->funcs->debugfs_init(gpu, dev->primary); 258 gpu->funcs->debugfs_init(gpu, dev->render); 259 } 260 #endif 261 262 return gpu; 263 } 264 265 static void set_gpu_pdev(struct drm_device *dev, 266 struct platform_device *pdev) 267 { 268 struct msm_drm_private *priv = dev->dev_private; 269 priv->gpu_pdev = pdev; 270 } 271 272 static int find_chipid(struct device *dev, struct adreno_rev *rev) 273 { 274 struct device_node *node = dev->of_node; 275 const char *compat; 276 int ret; 277 u32 chipid; 278 279 /* first search the compat strings for qcom,adreno-XYZ.W: */ 280 ret = of_property_read_string_index(node, "compatible", 0, &compat); 281 if (ret == 0) { 282 unsigned int r, patch; 283 284 if (sscanf(compat, "qcom,adreno-%u.%u", &r, &patch) == 2 || 285 sscanf(compat, "amd,imageon-%u.%u", &r, &patch) == 2) { 286 rev->core = r / 100; 287 r %= 100; 288 rev->major = r / 10; 289 r %= 10; 290 rev->minor = r; 291 rev->patchid = patch; 292 293 return 0; 294 } 295 } 296 297 /* and if that fails, fall back to legacy "qcom,chipid" property: */ 298 ret = of_property_read_u32(node, "qcom,chipid", &chipid); 299 if (ret) { 300 DRM_DEV_ERROR(dev, "could not parse qcom,chipid: %d\n", ret); 301 return ret; 302 } 303 304 rev->core = (chipid >> 24) & 0xff; 305 rev->major = (chipid >> 16) & 0xff; 306 rev->minor = (chipid >> 8) & 0xff; 307 rev->patchid = (chipid & 0xff); 308 309 dev_warn(dev, "Using legacy qcom,chipid binding!\n"); 310 dev_warn(dev, "Use compatible qcom,adreno-%u%u%u.%u instead.\n", 311 rev->core, rev->major, rev->minor, rev->patchid); 312 313 return 0; 314 } 315 316 static int adreno_bind(struct device *dev, struct device *master, void *data) 317 { 318 static struct adreno_platform_config config = {}; 319 const struct adreno_info *info; 320 struct drm_device *drm = dev_get_drvdata(master); 321 struct msm_drm_private *priv = drm->dev_private; 322 struct msm_gpu *gpu; 323 int ret; 324 325 ret = find_chipid(dev, &config.rev); 326 if (ret) 327 return ret; 328 329 dev->platform_data = &config; 330 set_gpu_pdev(drm, to_platform_device(dev)); 331 332 info = adreno_info(config.rev); 333 334 if (!info) { 335 dev_warn(drm->dev, "Unknown GPU revision: %u.%u.%u.%u\n", 336 config.rev.core, config.rev.major, 337 config.rev.minor, config.rev.patchid); 338 return -ENXIO; 339 } 340 341 DBG("Found GPU: %u.%u.%u.%u", config.rev.core, config.rev.major, 342 config.rev.minor, config.rev.patchid); 343 344 priv->is_a2xx = config.rev.core == 2; 345 346 gpu = info->init(drm); 347 if (IS_ERR(gpu)) { 348 dev_warn(drm->dev, "failed to load adreno gpu\n"); 349 return PTR_ERR(gpu); 350 } 351 352 dev_set_drvdata(dev, gpu); 353 354 return 0; 355 } 356 357 static void adreno_unbind(struct device *dev, struct device *master, 358 void *data) 359 { 360 struct msm_gpu *gpu = dev_get_drvdata(dev); 361 362 pm_runtime_force_suspend(dev); 363 gpu->funcs->destroy(gpu); 364 365 set_gpu_pdev(dev_get_drvdata(master), NULL); 366 } 367 368 static const struct component_ops a3xx_ops = { 369 .bind = adreno_bind, 370 .unbind = adreno_unbind, 371 }; 372 373 static void adreno_device_register_headless(void) 374 { 375 /* on imx5, we don't have a top-level mdp/dpu node 376 * this creates a dummy node for the driver for that case 377 */ 378 struct platform_device_info dummy_info = { 379 .parent = NULL, 380 .name = "msm", 381 .id = -1, 382 .res = NULL, 383 .num_res = 0, 384 .data = NULL, 385 .size_data = 0, 386 .dma_mask = ~0, 387 }; 388 platform_device_register_full(&dummy_info); 389 } 390 391 static int adreno_probe(struct platform_device *pdev) 392 { 393 394 int ret; 395 396 ret = component_add(&pdev->dev, &a3xx_ops); 397 if (ret) 398 return ret; 399 400 if (of_device_is_compatible(pdev->dev.of_node, "amd,imageon")) 401 adreno_device_register_headless(); 402 403 return 0; 404 } 405 406 static int adreno_remove(struct platform_device *pdev) 407 { 408 component_del(&pdev->dev, &a3xx_ops); 409 return 0; 410 } 411 412 static const struct of_device_id dt_match[] = { 413 { .compatible = "qcom,adreno" }, 414 { .compatible = "qcom,adreno-3xx" }, 415 /* for compatibility with imx5 gpu: */ 416 { .compatible = "amd,imageon" }, 417 /* for backwards compat w/ downstream kgsl DT files: */ 418 { .compatible = "qcom,kgsl-3d0" }, 419 {} 420 }; 421 422 #ifdef CONFIG_PM 423 static int adreno_resume(struct device *dev) 424 { 425 struct platform_device *pdev = to_platform_device(dev); 426 struct msm_gpu *gpu = platform_get_drvdata(pdev); 427 428 return gpu->funcs->pm_resume(gpu); 429 } 430 431 static int adreno_suspend(struct device *dev) 432 { 433 struct platform_device *pdev = to_platform_device(dev); 434 struct msm_gpu *gpu = platform_get_drvdata(pdev); 435 436 return gpu->funcs->pm_suspend(gpu); 437 } 438 #endif 439 440 static const struct dev_pm_ops adreno_pm_ops = { 441 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) 442 SET_RUNTIME_PM_OPS(adreno_suspend, adreno_resume, NULL) 443 }; 444 445 static struct platform_driver adreno_driver = { 446 .probe = adreno_probe, 447 .remove = adreno_remove, 448 .driver = { 449 .name = "adreno", 450 .of_match_table = dt_match, 451 .pm = &adreno_pm_ops, 452 }, 453 }; 454 455 void __init adreno_register(void) 456 { 457 platform_driver_register(&adreno_driver); 458 } 459 460 void __exit adreno_unregister(void) 461 { 462 platform_driver_unregister(&adreno_driver); 463 } 464