1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2013-2014 Red Hat
4  * Author: Rob Clark <robdclark@gmail.com>
5  *
6  * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved.
7  */
8 
9 #include "adreno_gpu.h"
10 
11 #define ANY_ID 0xff
12 
13 bool hang_debug = false;
14 MODULE_PARM_DESC(hang_debug, "Dump registers when hang is detected (can be slow!)");
15 module_param_named(hang_debug, hang_debug, bool, 0600);
16 
17 static const struct adreno_info gpulist[] = {
18 	{
19 		.rev   = ADRENO_REV(2, 0, 0, 0),
20 		.revn  = 200,
21 		.name  = "A200",
22 		.fw = {
23 			[ADRENO_FW_PM4] = "yamato_pm4.fw",
24 			[ADRENO_FW_PFP] = "yamato_pfp.fw",
25 		},
26 		.gmem  = SZ_256K,
27 		.inactive_period = DRM_MSM_INACTIVE_PERIOD,
28 		.init  = a2xx_gpu_init,
29 	}, { /* a200 on i.mx51 has only 128kib gmem */
30 		.rev   = ADRENO_REV(2, 0, 0, 1),
31 		.revn  = 201,
32 		.name  = "A200",
33 		.fw = {
34 			[ADRENO_FW_PM4] = "yamato_pm4.fw",
35 			[ADRENO_FW_PFP] = "yamato_pfp.fw",
36 		},
37 		.gmem  = SZ_128K,
38 		.inactive_period = DRM_MSM_INACTIVE_PERIOD,
39 		.init  = a2xx_gpu_init,
40 	}, {
41 		.rev   = ADRENO_REV(2, 2, 0, ANY_ID),
42 		.revn  = 220,
43 		.name  = "A220",
44 		.fw = {
45 			[ADRENO_FW_PM4] = "leia_pm4_470.fw",
46 			[ADRENO_FW_PFP] = "leia_pfp_470.fw",
47 		},
48 		.gmem  = SZ_512K,
49 		.inactive_period = DRM_MSM_INACTIVE_PERIOD,
50 		.init  = a2xx_gpu_init,
51 	}, {
52 		.rev   = ADRENO_REV(3, 0, 5, ANY_ID),
53 		.revn  = 305,
54 		.name  = "A305",
55 		.fw = {
56 			[ADRENO_FW_PM4] = "a300_pm4.fw",
57 			[ADRENO_FW_PFP] = "a300_pfp.fw",
58 		},
59 		.gmem  = SZ_256K,
60 		.inactive_period = DRM_MSM_INACTIVE_PERIOD,
61 		.init  = a3xx_gpu_init,
62 	}, {
63 		.rev   = ADRENO_REV(3, 0, 6, 0),
64 		.revn  = 307,        /* because a305c is revn==306 */
65 		.name  = "A306",
66 		.fw = {
67 			[ADRENO_FW_PM4] = "a300_pm4.fw",
68 			[ADRENO_FW_PFP] = "a300_pfp.fw",
69 		},
70 		.gmem  = SZ_128K,
71 		.inactive_period = DRM_MSM_INACTIVE_PERIOD,
72 		.init  = a3xx_gpu_init,
73 	}, {
74 		.rev   = ADRENO_REV(3, 2, ANY_ID, ANY_ID),
75 		.revn  = 320,
76 		.name  = "A320",
77 		.fw = {
78 			[ADRENO_FW_PM4] = "a300_pm4.fw",
79 			[ADRENO_FW_PFP] = "a300_pfp.fw",
80 		},
81 		.gmem  = SZ_512K,
82 		.inactive_period = DRM_MSM_INACTIVE_PERIOD,
83 		.init  = a3xx_gpu_init,
84 	}, {
85 		.rev   = ADRENO_REV(3, 3, 0, ANY_ID),
86 		.revn  = 330,
87 		.name  = "A330",
88 		.fw = {
89 			[ADRENO_FW_PM4] = "a330_pm4.fw",
90 			[ADRENO_FW_PFP] = "a330_pfp.fw",
91 		},
92 		.gmem  = SZ_1M,
93 		.inactive_period = DRM_MSM_INACTIVE_PERIOD,
94 		.init  = a3xx_gpu_init,
95 	}, {
96 		.rev   = ADRENO_REV(4, 2, 0, ANY_ID),
97 		.revn  = 420,
98 		.name  = "A420",
99 		.fw = {
100 			[ADRENO_FW_PM4] = "a420_pm4.fw",
101 			[ADRENO_FW_PFP] = "a420_pfp.fw",
102 		},
103 		.gmem  = (SZ_1M + SZ_512K),
104 		.inactive_period = DRM_MSM_INACTIVE_PERIOD,
105 		.init  = a4xx_gpu_init,
106 	}, {
107 		.rev   = ADRENO_REV(4, 3, 0, ANY_ID),
108 		.revn  = 430,
109 		.name  = "A430",
110 		.fw = {
111 			[ADRENO_FW_PM4] = "a420_pm4.fw",
112 			[ADRENO_FW_PFP] = "a420_pfp.fw",
113 		},
114 		.gmem  = (SZ_1M + SZ_512K),
115 		.inactive_period = DRM_MSM_INACTIVE_PERIOD,
116 		.init  = a4xx_gpu_init,
117 	}, {
118 		.rev   = ADRENO_REV(5, 1, 0, ANY_ID),
119 		.revn = 510,
120 		.name = "A510",
121 		.fw = {
122 			[ADRENO_FW_PM4] = "a530_pm4.fw",
123 			[ADRENO_FW_PFP] = "a530_pfp.fw",
124 		},
125 		.gmem = SZ_256K,
126 		/*
127 		 * Increase inactive period to 250 to avoid bouncing
128 		 * the GDSC which appears to make it grumpy
129 		 */
130 		.inactive_period = 250,
131 		.init = a5xx_gpu_init,
132 	}, {
133 		.rev = ADRENO_REV(5, 3, 0, 2),
134 		.revn = 530,
135 		.name = "A530",
136 		.fw = {
137 			[ADRENO_FW_PM4] = "a530_pm4.fw",
138 			[ADRENO_FW_PFP] = "a530_pfp.fw",
139 			[ADRENO_FW_GPMU] = "a530v3_gpmu.fw2",
140 		},
141 		.gmem = SZ_1M,
142 		/*
143 		 * Increase inactive period to 250 to avoid bouncing
144 		 * the GDSC which appears to make it grumpy
145 		 */
146 		.inactive_period = 250,
147 		.quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI |
148 			ADRENO_QUIRK_FAULT_DETECT_MASK,
149 		.init = a5xx_gpu_init,
150 		.zapfw = "a530_zap.mdt",
151 	}, {
152 		.rev = ADRENO_REV(5, 4, 0, 2),
153 		.revn = 540,
154 		.name = "A540",
155 		.fw = {
156 			[ADRENO_FW_PM4] = "a530_pm4.fw",
157 			[ADRENO_FW_PFP] = "a530_pfp.fw",
158 			[ADRENO_FW_GPMU] = "a540_gpmu.fw2",
159 		},
160 		.gmem = SZ_1M,
161 		/*
162 		 * Increase inactive period to 250 to avoid bouncing
163 		 * the GDSC which appears to make it grumpy
164 		 */
165 		.inactive_period = 250,
166 		.quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE,
167 		.init = a5xx_gpu_init,
168 		.zapfw = "a540_zap.mdt",
169 	}, {
170 		.rev = ADRENO_REV(6, 1, 8, ANY_ID),
171 		.revn = 618,
172 		.name = "A618",
173 		.fw = {
174 			[ADRENO_FW_SQE] = "a630_sqe.fw",
175 			[ADRENO_FW_GMU] = "a630_gmu.bin",
176 		},
177 		.gmem = SZ_512K,
178 		.inactive_period = DRM_MSM_INACTIVE_PERIOD,
179 		.init = a6xx_gpu_init,
180 	}, {
181 		.rev = ADRENO_REV(6, 3, 0, ANY_ID),
182 		.revn = 630,
183 		.name = "A630",
184 		.fw = {
185 			[ADRENO_FW_SQE] = "a630_sqe.fw",
186 			[ADRENO_FW_GMU] = "a630_gmu.bin",
187 		},
188 		.gmem = SZ_1M,
189 		.inactive_period = DRM_MSM_INACTIVE_PERIOD,
190 		.init = a6xx_gpu_init,
191 		.zapfw = "a630_zap.mdt",
192 	},
193 };
194 
195 MODULE_FIRMWARE("qcom/a300_pm4.fw");
196 MODULE_FIRMWARE("qcom/a300_pfp.fw");
197 MODULE_FIRMWARE("qcom/a330_pm4.fw");
198 MODULE_FIRMWARE("qcom/a330_pfp.fw");
199 MODULE_FIRMWARE("qcom/a420_pm4.fw");
200 MODULE_FIRMWARE("qcom/a420_pfp.fw");
201 MODULE_FIRMWARE("qcom/a530_pm4.fw");
202 MODULE_FIRMWARE("qcom/a530_pfp.fw");
203 MODULE_FIRMWARE("qcom/a530v3_gpmu.fw2");
204 MODULE_FIRMWARE("qcom/a530_zap.mdt");
205 MODULE_FIRMWARE("qcom/a530_zap.b00");
206 MODULE_FIRMWARE("qcom/a530_zap.b01");
207 MODULE_FIRMWARE("qcom/a530_zap.b02");
208 MODULE_FIRMWARE("qcom/a630_sqe.fw");
209 MODULE_FIRMWARE("qcom/a630_gmu.bin");
210 MODULE_FIRMWARE("qcom/a630_zap.mbn");
211 
212 static inline bool _rev_match(uint8_t entry, uint8_t id)
213 {
214 	return (entry == ANY_ID) || (entry == id);
215 }
216 
217 const struct adreno_info *adreno_info(struct adreno_rev rev)
218 {
219 	int i;
220 
221 	/* identify gpu: */
222 	for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
223 		const struct adreno_info *info = &gpulist[i];
224 		if (_rev_match(info->rev.core, rev.core) &&
225 				_rev_match(info->rev.major, rev.major) &&
226 				_rev_match(info->rev.minor, rev.minor) &&
227 				_rev_match(info->rev.patchid, rev.patchid))
228 			return info;
229 	}
230 
231 	return NULL;
232 }
233 
234 struct msm_gpu *adreno_load_gpu(struct drm_device *dev)
235 {
236 	struct msm_drm_private *priv = dev->dev_private;
237 	struct platform_device *pdev = priv->gpu_pdev;
238 	struct msm_gpu *gpu = NULL;
239 	struct adreno_gpu *adreno_gpu;
240 	int ret;
241 
242 	if (pdev)
243 		gpu = platform_get_drvdata(pdev);
244 
245 	if (!gpu) {
246 		dev_err_once(dev->dev, "no GPU device was found\n");
247 		return NULL;
248 	}
249 
250 	adreno_gpu = to_adreno_gpu(gpu);
251 
252 	/*
253 	 * The number one reason for HW init to fail is if the firmware isn't
254 	 * loaded yet. Try that first and don't bother continuing on
255 	 * otherwise
256 	 */
257 
258 	ret = adreno_load_fw(adreno_gpu);
259 	if (ret)
260 		return NULL;
261 
262 	/* Make sure pm runtime is active and reset any previous errors */
263 	pm_runtime_set_active(&pdev->dev);
264 
265 	ret = pm_runtime_get_sync(&pdev->dev);
266 	if (ret < 0) {
267 		pm_runtime_put_sync(&pdev->dev);
268 		DRM_DEV_ERROR(dev->dev, "Couldn't power up the GPU: %d\n", ret);
269 		return NULL;
270 	}
271 
272 	mutex_lock(&dev->struct_mutex);
273 	ret = msm_gpu_hw_init(gpu);
274 	mutex_unlock(&dev->struct_mutex);
275 	pm_runtime_put_autosuspend(&pdev->dev);
276 	if (ret) {
277 		DRM_DEV_ERROR(dev->dev, "gpu hw init failed: %d\n", ret);
278 		return NULL;
279 	}
280 
281 #ifdef CONFIG_DEBUG_FS
282 	if (gpu->funcs->debugfs_init) {
283 		gpu->funcs->debugfs_init(gpu, dev->primary);
284 		gpu->funcs->debugfs_init(gpu, dev->render);
285 	}
286 #endif
287 
288 	return gpu;
289 }
290 
291 static void set_gpu_pdev(struct drm_device *dev,
292 		struct platform_device *pdev)
293 {
294 	struct msm_drm_private *priv = dev->dev_private;
295 	priv->gpu_pdev = pdev;
296 }
297 
298 static int find_chipid(struct device *dev, struct adreno_rev *rev)
299 {
300 	struct device_node *node = dev->of_node;
301 	const char *compat;
302 	int ret;
303 	u32 chipid;
304 
305 	/* first search the compat strings for qcom,adreno-XYZ.W: */
306 	ret = of_property_read_string_index(node, "compatible", 0, &compat);
307 	if (ret == 0) {
308 		unsigned int r, patch;
309 
310 		if (sscanf(compat, "qcom,adreno-%u.%u", &r, &patch) == 2 ||
311 		    sscanf(compat, "amd,imageon-%u.%u", &r, &patch) == 2) {
312 			rev->core = r / 100;
313 			r %= 100;
314 			rev->major = r / 10;
315 			r %= 10;
316 			rev->minor = r;
317 			rev->patchid = patch;
318 
319 			return 0;
320 		}
321 	}
322 
323 	/* and if that fails, fall back to legacy "qcom,chipid" property: */
324 	ret = of_property_read_u32(node, "qcom,chipid", &chipid);
325 	if (ret) {
326 		DRM_DEV_ERROR(dev, "could not parse qcom,chipid: %d\n", ret);
327 		return ret;
328 	}
329 
330 	rev->core = (chipid >> 24) & 0xff;
331 	rev->major = (chipid >> 16) & 0xff;
332 	rev->minor = (chipid >> 8) & 0xff;
333 	rev->patchid = (chipid & 0xff);
334 
335 	dev_warn(dev, "Using legacy qcom,chipid binding!\n");
336 	dev_warn(dev, "Use compatible qcom,adreno-%u%u%u.%u instead.\n",
337 		rev->core, rev->major, rev->minor, rev->patchid);
338 
339 	return 0;
340 }
341 
342 static int adreno_bind(struct device *dev, struct device *master, void *data)
343 {
344 	static struct adreno_platform_config config = {};
345 	const struct adreno_info *info;
346 	struct drm_device *drm = dev_get_drvdata(master);
347 	struct msm_drm_private *priv = drm->dev_private;
348 	struct msm_gpu *gpu;
349 	int ret;
350 
351 	ret = find_chipid(dev, &config.rev);
352 	if (ret)
353 		return ret;
354 
355 	dev->platform_data = &config;
356 	set_gpu_pdev(drm, to_platform_device(dev));
357 
358 	info = adreno_info(config.rev);
359 
360 	if (!info) {
361 		dev_warn(drm->dev, "Unknown GPU revision: %u.%u.%u.%u\n",
362 			config.rev.core, config.rev.major,
363 			config.rev.minor, config.rev.patchid);
364 		return -ENXIO;
365 	}
366 
367 	DBG("Found GPU: %u.%u.%u.%u", config.rev.core, config.rev.major,
368 		config.rev.minor, config.rev.patchid);
369 
370 	priv->is_a2xx = config.rev.core == 2;
371 
372 	gpu = info->init(drm);
373 	if (IS_ERR(gpu)) {
374 		dev_warn(drm->dev, "failed to load adreno gpu\n");
375 		return PTR_ERR(gpu);
376 	}
377 
378 	dev_set_drvdata(dev, gpu);
379 
380 	return 0;
381 }
382 
383 static void adreno_unbind(struct device *dev, struct device *master,
384 		void *data)
385 {
386 	struct msm_gpu *gpu = dev_get_drvdata(dev);
387 
388 	pm_runtime_force_suspend(dev);
389 	gpu->funcs->destroy(gpu);
390 
391 	set_gpu_pdev(dev_get_drvdata(master), NULL);
392 }
393 
394 static const struct component_ops a3xx_ops = {
395 		.bind   = adreno_bind,
396 		.unbind = adreno_unbind,
397 };
398 
399 static void adreno_device_register_headless(void)
400 {
401 	/* on imx5, we don't have a top-level mdp/dpu node
402 	 * this creates a dummy node for the driver for that case
403 	 */
404 	struct platform_device_info dummy_info = {
405 		.parent = NULL,
406 		.name = "msm",
407 		.id = -1,
408 		.res = NULL,
409 		.num_res = 0,
410 		.data = NULL,
411 		.size_data = 0,
412 		.dma_mask = ~0,
413 	};
414 	platform_device_register_full(&dummy_info);
415 }
416 
417 static int adreno_probe(struct platform_device *pdev)
418 {
419 
420 	int ret;
421 
422 	ret = component_add(&pdev->dev, &a3xx_ops);
423 	if (ret)
424 		return ret;
425 
426 	if (of_device_is_compatible(pdev->dev.of_node, "amd,imageon"))
427 		adreno_device_register_headless();
428 
429 	return 0;
430 }
431 
432 static int adreno_remove(struct platform_device *pdev)
433 {
434 	component_del(&pdev->dev, &a3xx_ops);
435 	return 0;
436 }
437 
438 static const struct of_device_id dt_match[] = {
439 	{ .compatible = "qcom,adreno" },
440 	{ .compatible = "qcom,adreno-3xx" },
441 	/* for compatibility with imx5 gpu: */
442 	{ .compatible = "amd,imageon" },
443 	/* for backwards compat w/ downstream kgsl DT files: */
444 	{ .compatible = "qcom,kgsl-3d0" },
445 	{}
446 };
447 
448 #ifdef CONFIG_PM
449 static int adreno_resume(struct device *dev)
450 {
451 	struct platform_device *pdev = to_platform_device(dev);
452 	struct msm_gpu *gpu = platform_get_drvdata(pdev);
453 
454 	return gpu->funcs->pm_resume(gpu);
455 }
456 
457 static int adreno_suspend(struct device *dev)
458 {
459 	struct platform_device *pdev = to_platform_device(dev);
460 	struct msm_gpu *gpu = platform_get_drvdata(pdev);
461 
462 	return gpu->funcs->pm_suspend(gpu);
463 }
464 #endif
465 
466 static const struct dev_pm_ops adreno_pm_ops = {
467 	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
468 	SET_RUNTIME_PM_OPS(adreno_suspend, adreno_resume, NULL)
469 };
470 
471 static struct platform_driver adreno_driver = {
472 	.probe = adreno_probe,
473 	.remove = adreno_remove,
474 	.driver = {
475 		.name = "adreno",
476 		.of_match_table = dt_match,
477 		.pm = &adreno_pm_ops,
478 	},
479 };
480 
481 void __init adreno_register(void)
482 {
483 	platform_driver_register(&adreno_driver);
484 }
485 
486 void __exit adreno_unregister(void)
487 {
488 	platform_driver_unregister(&adreno_driver);
489 }
490