1 /* 2 * Copyright (C) 2013-2014 Red Hat 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License version 2 as published by 9 * the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "adreno_gpu.h" 21 22 #define ANY_ID 0xff 23 24 bool hang_debug = false; 25 MODULE_PARM_DESC(hang_debug, "Dump registers when hang is detected (can be slow!)"); 26 module_param_named(hang_debug, hang_debug, bool, 0600); 27 28 static const struct adreno_info gpulist[] = { 29 { 30 .rev = ADRENO_REV(2, 0, 0, 0), 31 .revn = 200, 32 .name = "A200", 33 .fw = { 34 [ADRENO_FW_PM4] = "yamato_pm4.fw", 35 [ADRENO_FW_PFP] = "yamato_pfp.fw", 36 }, 37 .gmem = SZ_256K, 38 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 39 .init = a2xx_gpu_init, 40 }, { /* a200 on i.mx51 has only 128kib gmem */ 41 .rev = ADRENO_REV(2, 0, 0, 1), 42 .revn = 201, 43 .name = "A200", 44 .fw = { 45 [ADRENO_FW_PM4] = "yamato_pm4.fw", 46 [ADRENO_FW_PFP] = "yamato_pfp.fw", 47 }, 48 .gmem = SZ_128K, 49 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 50 .init = a2xx_gpu_init, 51 }, { 52 .rev = ADRENO_REV(2, 2, 0, ANY_ID), 53 .revn = 220, 54 .name = "A220", 55 .fw = { 56 [ADRENO_FW_PM4] = "leia_pm4_470.fw", 57 [ADRENO_FW_PFP] = "leia_pfp_470.fw", 58 }, 59 .gmem = SZ_512K, 60 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 61 .init = a2xx_gpu_init, 62 }, { 63 .rev = ADRENO_REV(3, 0, 5, ANY_ID), 64 .revn = 305, 65 .name = "A305", 66 .fw = { 67 [ADRENO_FW_PM4] = "a300_pm4.fw", 68 [ADRENO_FW_PFP] = "a300_pfp.fw", 69 }, 70 .gmem = SZ_256K, 71 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 72 .init = a3xx_gpu_init, 73 }, { 74 .rev = ADRENO_REV(3, 0, 6, 0), 75 .revn = 307, /* because a305c is revn==306 */ 76 .name = "A306", 77 .fw = { 78 [ADRENO_FW_PM4] = "a300_pm4.fw", 79 [ADRENO_FW_PFP] = "a300_pfp.fw", 80 }, 81 .gmem = SZ_128K, 82 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 83 .init = a3xx_gpu_init, 84 }, { 85 .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID), 86 .revn = 320, 87 .name = "A320", 88 .fw = { 89 [ADRENO_FW_PM4] = "a300_pm4.fw", 90 [ADRENO_FW_PFP] = "a300_pfp.fw", 91 }, 92 .gmem = SZ_512K, 93 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 94 .init = a3xx_gpu_init, 95 }, { 96 .rev = ADRENO_REV(3, 3, 0, ANY_ID), 97 .revn = 330, 98 .name = "A330", 99 .fw = { 100 [ADRENO_FW_PM4] = "a330_pm4.fw", 101 [ADRENO_FW_PFP] = "a330_pfp.fw", 102 }, 103 .gmem = SZ_1M, 104 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 105 .init = a3xx_gpu_init, 106 }, { 107 .rev = ADRENO_REV(4, 2, 0, ANY_ID), 108 .revn = 420, 109 .name = "A420", 110 .fw = { 111 [ADRENO_FW_PM4] = "a420_pm4.fw", 112 [ADRENO_FW_PFP] = "a420_pfp.fw", 113 }, 114 .gmem = (SZ_1M + SZ_512K), 115 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 116 .init = a4xx_gpu_init, 117 }, { 118 .rev = ADRENO_REV(4, 3, 0, ANY_ID), 119 .revn = 430, 120 .name = "A430", 121 .fw = { 122 [ADRENO_FW_PM4] = "a420_pm4.fw", 123 [ADRENO_FW_PFP] = "a420_pfp.fw", 124 }, 125 .gmem = (SZ_1M + SZ_512K), 126 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 127 .init = a4xx_gpu_init, 128 }, { 129 .rev = ADRENO_REV(5, 3, 0, 2), 130 .revn = 530, 131 .name = "A530", 132 .fw = { 133 [ADRENO_FW_PM4] = "a530_pm4.fw", 134 [ADRENO_FW_PFP] = "a530_pfp.fw", 135 [ADRENO_FW_GPMU] = "a530v3_gpmu.fw2", 136 }, 137 .gmem = SZ_1M, 138 /* 139 * Increase inactive period to 250 to avoid bouncing 140 * the GDSC which appears to make it grumpy 141 */ 142 .inactive_period = 250, 143 .quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI | 144 ADRENO_QUIRK_FAULT_DETECT_MASK, 145 .init = a5xx_gpu_init, 146 .zapfw = "a530_zap.mdt", 147 }, { 148 .rev = ADRENO_REV(6, 3, 0, ANY_ID), 149 .revn = 630, 150 .name = "A630", 151 .fw = { 152 [ADRENO_FW_SQE] = "a630_sqe.fw", 153 [ADRENO_FW_GMU] = "a630_gmu.bin", 154 }, 155 .gmem = SZ_1M, 156 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 157 .init = a6xx_gpu_init, 158 }, 159 }; 160 161 MODULE_FIRMWARE("qcom/a300_pm4.fw"); 162 MODULE_FIRMWARE("qcom/a300_pfp.fw"); 163 MODULE_FIRMWARE("qcom/a330_pm4.fw"); 164 MODULE_FIRMWARE("qcom/a330_pfp.fw"); 165 MODULE_FIRMWARE("qcom/a420_pm4.fw"); 166 MODULE_FIRMWARE("qcom/a420_pfp.fw"); 167 MODULE_FIRMWARE("qcom/a530_pm4.fw"); 168 MODULE_FIRMWARE("qcom/a530_pfp.fw"); 169 MODULE_FIRMWARE("qcom/a530v3_gpmu.fw2"); 170 MODULE_FIRMWARE("qcom/a530_zap.mdt"); 171 MODULE_FIRMWARE("qcom/a530_zap.b00"); 172 MODULE_FIRMWARE("qcom/a530_zap.b01"); 173 MODULE_FIRMWARE("qcom/a530_zap.b02"); 174 MODULE_FIRMWARE("qcom/a630_sqe.fw"); 175 MODULE_FIRMWARE("qcom/a630_gmu.bin"); 176 177 static inline bool _rev_match(uint8_t entry, uint8_t id) 178 { 179 return (entry == ANY_ID) || (entry == id); 180 } 181 182 const struct adreno_info *adreno_info(struct adreno_rev rev) 183 { 184 int i; 185 186 /* identify gpu: */ 187 for (i = 0; i < ARRAY_SIZE(gpulist); i++) { 188 const struct adreno_info *info = &gpulist[i]; 189 if (_rev_match(info->rev.core, rev.core) && 190 _rev_match(info->rev.major, rev.major) && 191 _rev_match(info->rev.minor, rev.minor) && 192 _rev_match(info->rev.patchid, rev.patchid)) 193 return info; 194 } 195 196 return NULL; 197 } 198 199 struct msm_gpu *adreno_load_gpu(struct drm_device *dev) 200 { 201 struct msm_drm_private *priv = dev->dev_private; 202 struct platform_device *pdev = priv->gpu_pdev; 203 struct msm_gpu *gpu = NULL; 204 struct adreno_gpu *adreno_gpu; 205 int ret; 206 207 if (pdev) 208 gpu = platform_get_drvdata(pdev); 209 210 if (!gpu) { 211 dev_err_once(dev->dev, "no GPU device was found\n"); 212 return NULL; 213 } 214 215 adreno_gpu = to_adreno_gpu(gpu); 216 217 /* 218 * The number one reason for HW init to fail is if the firmware isn't 219 * loaded yet. Try that first and don't bother continuing on 220 * otherwise 221 */ 222 223 ret = adreno_load_fw(adreno_gpu); 224 if (ret) 225 return NULL; 226 227 /* Make sure pm runtime is active and reset any previous errors */ 228 pm_runtime_set_active(&pdev->dev); 229 230 ret = pm_runtime_get_sync(&pdev->dev); 231 if (ret < 0) { 232 DRM_DEV_ERROR(dev->dev, "Couldn't power up the GPU: %d\n", ret); 233 return NULL; 234 } 235 236 mutex_lock(&dev->struct_mutex); 237 ret = msm_gpu_hw_init(gpu); 238 mutex_unlock(&dev->struct_mutex); 239 pm_runtime_put_autosuspend(&pdev->dev); 240 if (ret) { 241 DRM_DEV_ERROR(dev->dev, "gpu hw init failed: %d\n", ret); 242 return NULL; 243 } 244 245 #ifdef CONFIG_DEBUG_FS 246 if (gpu->funcs->debugfs_init) { 247 gpu->funcs->debugfs_init(gpu, dev->primary); 248 gpu->funcs->debugfs_init(gpu, dev->render); 249 } 250 #endif 251 252 return gpu; 253 } 254 255 static void set_gpu_pdev(struct drm_device *dev, 256 struct platform_device *pdev) 257 { 258 struct msm_drm_private *priv = dev->dev_private; 259 priv->gpu_pdev = pdev; 260 } 261 262 static int find_chipid(struct device *dev, struct adreno_rev *rev) 263 { 264 struct device_node *node = dev->of_node; 265 const char *compat; 266 int ret; 267 u32 chipid; 268 269 /* first search the compat strings for qcom,adreno-XYZ.W: */ 270 ret = of_property_read_string_index(node, "compatible", 0, &compat); 271 if (ret == 0) { 272 unsigned int r, patch; 273 274 if (sscanf(compat, "qcom,adreno-%u.%u", &r, &patch) == 2 || 275 sscanf(compat, "amd,imageon-%u.%u", &r, &patch) == 2) { 276 rev->core = r / 100; 277 r %= 100; 278 rev->major = r / 10; 279 r %= 10; 280 rev->minor = r; 281 rev->patchid = patch; 282 283 return 0; 284 } 285 } 286 287 /* and if that fails, fall back to legacy "qcom,chipid" property: */ 288 ret = of_property_read_u32(node, "qcom,chipid", &chipid); 289 if (ret) { 290 DRM_DEV_ERROR(dev, "could not parse qcom,chipid: %d\n", ret); 291 return ret; 292 } 293 294 rev->core = (chipid >> 24) & 0xff; 295 rev->major = (chipid >> 16) & 0xff; 296 rev->minor = (chipid >> 8) & 0xff; 297 rev->patchid = (chipid & 0xff); 298 299 dev_warn(dev, "Using legacy qcom,chipid binding!\n"); 300 dev_warn(dev, "Use compatible qcom,adreno-%u%u%u.%u instead.\n", 301 rev->core, rev->major, rev->minor, rev->patchid); 302 303 return 0; 304 } 305 306 static int adreno_bind(struct device *dev, struct device *master, void *data) 307 { 308 static struct adreno_platform_config config = {}; 309 const struct adreno_info *info; 310 struct drm_device *drm = dev_get_drvdata(master); 311 struct msm_drm_private *priv = drm->dev_private; 312 struct msm_gpu *gpu; 313 int ret; 314 315 ret = find_chipid(dev, &config.rev); 316 if (ret) 317 return ret; 318 319 dev->platform_data = &config; 320 set_gpu_pdev(drm, to_platform_device(dev)); 321 322 info = adreno_info(config.rev); 323 324 if (!info) { 325 dev_warn(drm->dev, "Unknown GPU revision: %u.%u.%u.%u\n", 326 config.rev.core, config.rev.major, 327 config.rev.minor, config.rev.patchid); 328 return -ENXIO; 329 } 330 331 DBG("Found GPU: %u.%u.%u.%u", config.rev.core, config.rev.major, 332 config.rev.minor, config.rev.patchid); 333 334 priv->is_a2xx = config.rev.core == 2; 335 336 gpu = info->init(drm); 337 if (IS_ERR(gpu)) { 338 dev_warn(drm->dev, "failed to load adreno gpu\n"); 339 return PTR_ERR(gpu); 340 } 341 342 dev_set_drvdata(dev, gpu); 343 344 return 0; 345 } 346 347 static void adreno_unbind(struct device *dev, struct device *master, 348 void *data) 349 { 350 struct msm_gpu *gpu = dev_get_drvdata(dev); 351 352 gpu->funcs->pm_suspend(gpu); 353 gpu->funcs->destroy(gpu); 354 355 set_gpu_pdev(dev_get_drvdata(master), NULL); 356 } 357 358 static const struct component_ops a3xx_ops = { 359 .bind = adreno_bind, 360 .unbind = adreno_unbind, 361 }; 362 363 static void adreno_device_register_headless(void) 364 { 365 /* on imx5, we don't have a top-level mdp/dpu node 366 * this creates a dummy node for the driver for that case 367 */ 368 struct platform_device_info dummy_info = { 369 .parent = NULL, 370 .name = "msm", 371 .id = -1, 372 .res = NULL, 373 .num_res = 0, 374 .data = NULL, 375 .size_data = 0, 376 .dma_mask = ~0, 377 }; 378 platform_device_register_full(&dummy_info); 379 } 380 381 static int adreno_probe(struct platform_device *pdev) 382 { 383 384 int ret; 385 386 ret = component_add(&pdev->dev, &a3xx_ops); 387 if (ret) 388 return ret; 389 390 if (of_device_is_compatible(pdev->dev.of_node, "amd,imageon")) 391 adreno_device_register_headless(); 392 393 return 0; 394 } 395 396 static int adreno_remove(struct platform_device *pdev) 397 { 398 component_del(&pdev->dev, &a3xx_ops); 399 return 0; 400 } 401 402 static const struct of_device_id dt_match[] = { 403 { .compatible = "qcom,adreno" }, 404 { .compatible = "qcom,adreno-3xx" }, 405 /* for compatibility with imx5 gpu: */ 406 { .compatible = "amd,imageon" }, 407 /* for backwards compat w/ downstream kgsl DT files: */ 408 { .compatible = "qcom,kgsl-3d0" }, 409 {} 410 }; 411 412 #ifdef CONFIG_PM 413 static int adreno_resume(struct device *dev) 414 { 415 struct platform_device *pdev = to_platform_device(dev); 416 struct msm_gpu *gpu = platform_get_drvdata(pdev); 417 418 return gpu->funcs->pm_resume(gpu); 419 } 420 421 static int adreno_suspend(struct device *dev) 422 { 423 struct platform_device *pdev = to_platform_device(dev); 424 struct msm_gpu *gpu = platform_get_drvdata(pdev); 425 426 return gpu->funcs->pm_suspend(gpu); 427 } 428 #endif 429 430 static const struct dev_pm_ops adreno_pm_ops = { 431 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) 432 SET_RUNTIME_PM_OPS(adreno_suspend, adreno_resume, NULL) 433 }; 434 435 static struct platform_driver adreno_driver = { 436 .probe = adreno_probe, 437 .remove = adreno_remove, 438 .driver = { 439 .name = "adreno", 440 .of_match_table = dt_match, 441 .pm = &adreno_pm_ops, 442 }, 443 }; 444 445 void __init adreno_register(void) 446 { 447 platform_driver_register(&adreno_driver); 448 } 449 450 void __exit adreno_unregister(void) 451 { 452 platform_driver_unregister(&adreno_driver); 453 } 454