1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013-2014 Red Hat 4 * Author: Rob Clark <robdclark@gmail.com> 5 * 6 * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved. 7 */ 8 9 #include "adreno_gpu.h" 10 11 bool hang_debug = false; 12 MODULE_PARM_DESC(hang_debug, "Dump registers when hang is detected (can be slow!)"); 13 module_param_named(hang_debug, hang_debug, bool, 0600); 14 15 bool snapshot_debugbus = false; 16 MODULE_PARM_DESC(snapshot_debugbus, "Include debugbus sections in GPU devcoredump (if not fused off)"); 17 module_param_named(snapshot_debugbus, snapshot_debugbus, bool, 0600); 18 19 bool allow_vram_carveout = false; 20 MODULE_PARM_DESC(allow_vram_carveout, "Allow using VRAM Carveout, in place of IOMMU"); 21 module_param_named(allow_vram_carveout, allow_vram_carveout, bool, 0600); 22 23 static const struct adreno_info gpulist[] = { 24 { 25 .rev = ADRENO_REV(2, 0, 0, 0), 26 .revn = 200, 27 .name = "A200", 28 .fw = { 29 [ADRENO_FW_PM4] = "yamato_pm4.fw", 30 [ADRENO_FW_PFP] = "yamato_pfp.fw", 31 }, 32 .gmem = SZ_256K, 33 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 34 .init = a2xx_gpu_init, 35 }, { /* a200 on i.mx51 has only 128kib gmem */ 36 .rev = ADRENO_REV(2, 0, 0, 1), 37 .revn = 201, 38 .name = "A200", 39 .fw = { 40 [ADRENO_FW_PM4] = "yamato_pm4.fw", 41 [ADRENO_FW_PFP] = "yamato_pfp.fw", 42 }, 43 .gmem = SZ_128K, 44 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 45 .init = a2xx_gpu_init, 46 }, { 47 .rev = ADRENO_REV(2, 2, 0, ANY_ID), 48 .revn = 220, 49 .name = "A220", 50 .fw = { 51 [ADRENO_FW_PM4] = "leia_pm4_470.fw", 52 [ADRENO_FW_PFP] = "leia_pfp_470.fw", 53 }, 54 .gmem = SZ_512K, 55 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 56 .init = a2xx_gpu_init, 57 }, { 58 .rev = ADRENO_REV(3, 0, 5, ANY_ID), 59 .revn = 305, 60 .name = "A305", 61 .fw = { 62 [ADRENO_FW_PM4] = "a300_pm4.fw", 63 [ADRENO_FW_PFP] = "a300_pfp.fw", 64 }, 65 .gmem = SZ_256K, 66 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 67 .init = a3xx_gpu_init, 68 }, { 69 .rev = ADRENO_REV(3, 0, 6, 0), 70 .revn = 307, /* because a305c is revn==306 */ 71 .name = "A306", 72 .fw = { 73 [ADRENO_FW_PM4] = "a300_pm4.fw", 74 [ADRENO_FW_PFP] = "a300_pfp.fw", 75 }, 76 .gmem = SZ_128K, 77 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 78 .init = a3xx_gpu_init, 79 }, { 80 .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID), 81 .revn = 320, 82 .name = "A320", 83 .fw = { 84 [ADRENO_FW_PM4] = "a300_pm4.fw", 85 [ADRENO_FW_PFP] = "a300_pfp.fw", 86 }, 87 .gmem = SZ_512K, 88 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 89 .init = a3xx_gpu_init, 90 }, { 91 .rev = ADRENO_REV(3, 3, 0, ANY_ID), 92 .revn = 330, 93 .name = "A330", 94 .fw = { 95 [ADRENO_FW_PM4] = "a330_pm4.fw", 96 [ADRENO_FW_PFP] = "a330_pfp.fw", 97 }, 98 .gmem = SZ_1M, 99 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 100 .init = a3xx_gpu_init, 101 }, { 102 .rev = ADRENO_REV(4, 0, 5, ANY_ID), 103 .revn = 405, 104 .name = "A405", 105 .fw = { 106 [ADRENO_FW_PM4] = "a420_pm4.fw", 107 [ADRENO_FW_PFP] = "a420_pfp.fw", 108 }, 109 .gmem = SZ_256K, 110 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 111 .init = a4xx_gpu_init, 112 }, { 113 .rev = ADRENO_REV(4, 2, 0, ANY_ID), 114 .revn = 420, 115 .name = "A420", 116 .fw = { 117 [ADRENO_FW_PM4] = "a420_pm4.fw", 118 [ADRENO_FW_PFP] = "a420_pfp.fw", 119 }, 120 .gmem = (SZ_1M + SZ_512K), 121 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 122 .init = a4xx_gpu_init, 123 }, { 124 .rev = ADRENO_REV(4, 3, 0, ANY_ID), 125 .revn = 430, 126 .name = "A430", 127 .fw = { 128 [ADRENO_FW_PM4] = "a420_pm4.fw", 129 [ADRENO_FW_PFP] = "a420_pfp.fw", 130 }, 131 .gmem = (SZ_1M + SZ_512K), 132 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 133 .init = a4xx_gpu_init, 134 }, { 135 .rev = ADRENO_REV(5, 0, 6, ANY_ID), 136 .revn = 506, 137 .name = "A506", 138 .fw = { 139 [ADRENO_FW_PM4] = "a530_pm4.fw", 140 [ADRENO_FW_PFP] = "a530_pfp.fw", 141 }, 142 .gmem = (SZ_128K + SZ_8K), 143 /* 144 * Increase inactive period to 250 to avoid bouncing 145 * the GDSC which appears to make it grumpy 146 */ 147 .inactive_period = 250, 148 .quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI | 149 ADRENO_QUIRK_LMLOADKILL_DISABLE, 150 .init = a5xx_gpu_init, 151 .zapfw = "a506_zap.mdt", 152 }, { 153 .rev = ADRENO_REV(5, 0, 8, ANY_ID), 154 .revn = 508, 155 .name = "A508", 156 .fw = { 157 [ADRENO_FW_PM4] = "a530_pm4.fw", 158 [ADRENO_FW_PFP] = "a530_pfp.fw", 159 }, 160 .gmem = (SZ_128K + SZ_8K), 161 /* 162 * Increase inactive period to 250 to avoid bouncing 163 * the GDSC which appears to make it grumpy 164 */ 165 .inactive_period = 250, 166 .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE, 167 .init = a5xx_gpu_init, 168 .zapfw = "a508_zap.mdt", 169 }, { 170 .rev = ADRENO_REV(5, 0, 9, ANY_ID), 171 .revn = 509, 172 .name = "A509", 173 .fw = { 174 [ADRENO_FW_PM4] = "a530_pm4.fw", 175 [ADRENO_FW_PFP] = "a530_pfp.fw", 176 }, 177 .gmem = (SZ_256K + SZ_16K), 178 /* 179 * Increase inactive period to 250 to avoid bouncing 180 * the GDSC which appears to make it grumpy 181 */ 182 .inactive_period = 250, 183 .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE, 184 .init = a5xx_gpu_init, 185 /* Adreno 509 uses the same ZAP as 512 */ 186 .zapfw = "a512_zap.mdt", 187 }, { 188 .rev = ADRENO_REV(5, 1, 0, ANY_ID), 189 .revn = 510, 190 .name = "A510", 191 .fw = { 192 [ADRENO_FW_PM4] = "a530_pm4.fw", 193 [ADRENO_FW_PFP] = "a530_pfp.fw", 194 }, 195 .gmem = SZ_256K, 196 /* 197 * Increase inactive period to 250 to avoid bouncing 198 * the GDSC which appears to make it grumpy 199 */ 200 .inactive_period = 250, 201 .init = a5xx_gpu_init, 202 }, { 203 .rev = ADRENO_REV(5, 1, 2, ANY_ID), 204 .revn = 512, 205 .name = "A512", 206 .fw = { 207 [ADRENO_FW_PM4] = "a530_pm4.fw", 208 [ADRENO_FW_PFP] = "a530_pfp.fw", 209 }, 210 .gmem = (SZ_256K + SZ_16K), 211 /* 212 * Increase inactive period to 250 to avoid bouncing 213 * the GDSC which appears to make it grumpy 214 */ 215 .inactive_period = 250, 216 .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE, 217 .init = a5xx_gpu_init, 218 .zapfw = "a512_zap.mdt", 219 }, { 220 .rev = ADRENO_REV(5, 3, 0, 2), 221 .revn = 530, 222 .name = "A530", 223 .fw = { 224 [ADRENO_FW_PM4] = "a530_pm4.fw", 225 [ADRENO_FW_PFP] = "a530_pfp.fw", 226 [ADRENO_FW_GPMU] = "a530v3_gpmu.fw2", 227 }, 228 .gmem = SZ_1M, 229 /* 230 * Increase inactive period to 250 to avoid bouncing 231 * the GDSC which appears to make it grumpy 232 */ 233 .inactive_period = 250, 234 .quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI | 235 ADRENO_QUIRK_FAULT_DETECT_MASK, 236 .init = a5xx_gpu_init, 237 .zapfw = "a530_zap.mdt", 238 }, { 239 .rev = ADRENO_REV(5, 4, 0, ANY_ID), 240 .revn = 540, 241 .name = "A540", 242 .fw = { 243 [ADRENO_FW_PM4] = "a530_pm4.fw", 244 [ADRENO_FW_PFP] = "a530_pfp.fw", 245 [ADRENO_FW_GPMU] = "a540_gpmu.fw2", 246 }, 247 .gmem = SZ_1M, 248 /* 249 * Increase inactive period to 250 to avoid bouncing 250 * the GDSC which appears to make it grumpy 251 */ 252 .inactive_period = 250, 253 .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE, 254 .init = a5xx_gpu_init, 255 .zapfw = "a540_zap.mdt", 256 }, { 257 .rev = ADRENO_REV(6, 1, 8, ANY_ID), 258 .revn = 618, 259 .name = "A618", 260 .fw = { 261 [ADRENO_FW_SQE] = "a630_sqe.fw", 262 [ADRENO_FW_GMU] = "a630_gmu.bin", 263 }, 264 .gmem = SZ_512K, 265 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 266 .init = a6xx_gpu_init, 267 }, { 268 .rev = ADRENO_REV(6, 3, 0, ANY_ID), 269 .revn = 630, 270 .name = "A630", 271 .fw = { 272 [ADRENO_FW_SQE] = "a630_sqe.fw", 273 [ADRENO_FW_GMU] = "a630_gmu.bin", 274 }, 275 .gmem = SZ_1M, 276 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 277 .init = a6xx_gpu_init, 278 .zapfw = "a630_zap.mdt", 279 .hwcg = a630_hwcg, 280 }, { 281 .rev = ADRENO_REV(6, 4, 0, ANY_ID), 282 .revn = 640, 283 .name = "A640", 284 .fw = { 285 [ADRENO_FW_SQE] = "a630_sqe.fw", 286 [ADRENO_FW_GMU] = "a640_gmu.bin", 287 }, 288 .gmem = SZ_1M, 289 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 290 .init = a6xx_gpu_init, 291 .zapfw = "a640_zap.mdt", 292 .hwcg = a640_hwcg, 293 }, { 294 .rev = ADRENO_REV(6, 5, 0, ANY_ID), 295 .revn = 650, 296 .name = "A650", 297 .fw = { 298 [ADRENO_FW_SQE] = "a650_sqe.fw", 299 [ADRENO_FW_GMU] = "a650_gmu.bin", 300 }, 301 .gmem = SZ_1M + SZ_128K, 302 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 303 .init = a6xx_gpu_init, 304 .zapfw = "a650_zap.mdt", 305 .hwcg = a650_hwcg, 306 }, { 307 .rev = ADRENO_REV(6, 6, 0, ANY_ID), 308 .revn = 660, 309 .name = "A660", 310 .fw = { 311 [ADRENO_FW_SQE] = "a660_sqe.fw", 312 [ADRENO_FW_GMU] = "a660_gmu.bin", 313 }, 314 .gmem = SZ_1M + SZ_512K, 315 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 316 .init = a6xx_gpu_init, 317 .zapfw = "a660_zap.mdt", 318 .hwcg = a660_hwcg, 319 }, { 320 .rev = ADRENO_REV(6, 3, 5, ANY_ID), 321 .name = "Adreno 7c Gen 3", 322 .fw = { 323 [ADRENO_FW_SQE] = "a660_sqe.fw", 324 [ADRENO_FW_GMU] = "a660_gmu.bin", 325 }, 326 .gmem = SZ_512K, 327 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 328 .init = a6xx_gpu_init, 329 .hwcg = a660_hwcg, 330 }, { 331 .rev = ADRENO_REV(6, 8, 0, ANY_ID), 332 .revn = 680, 333 .name = "A680", 334 .fw = { 335 [ADRENO_FW_SQE] = "a630_sqe.fw", 336 [ADRENO_FW_GMU] = "a640_gmu.bin", 337 }, 338 .gmem = SZ_2M, 339 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 340 .init = a6xx_gpu_init, 341 .zapfw = "a640_zap.mdt", 342 .hwcg = a640_hwcg, 343 }, 344 }; 345 346 MODULE_FIRMWARE("qcom/a300_pm4.fw"); 347 MODULE_FIRMWARE("qcom/a300_pfp.fw"); 348 MODULE_FIRMWARE("qcom/a330_pm4.fw"); 349 MODULE_FIRMWARE("qcom/a330_pfp.fw"); 350 MODULE_FIRMWARE("qcom/a420_pm4.fw"); 351 MODULE_FIRMWARE("qcom/a420_pfp.fw"); 352 MODULE_FIRMWARE("qcom/a530_pm4.fw"); 353 MODULE_FIRMWARE("qcom/a530_pfp.fw"); 354 MODULE_FIRMWARE("qcom/a530v3_gpmu.fw2"); 355 MODULE_FIRMWARE("qcom/a530_zap.mdt"); 356 MODULE_FIRMWARE("qcom/a530_zap.b00"); 357 MODULE_FIRMWARE("qcom/a530_zap.b01"); 358 MODULE_FIRMWARE("qcom/a530_zap.b02"); 359 MODULE_FIRMWARE("qcom/a630_sqe.fw"); 360 MODULE_FIRMWARE("qcom/a630_gmu.bin"); 361 MODULE_FIRMWARE("qcom/a630_zap.mbn"); 362 363 static inline bool _rev_match(uint8_t entry, uint8_t id) 364 { 365 return (entry == ANY_ID) || (entry == id); 366 } 367 368 bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2) 369 { 370 371 return _rev_match(rev1.core, rev2.core) && 372 _rev_match(rev1.major, rev2.major) && 373 _rev_match(rev1.minor, rev2.minor) && 374 _rev_match(rev1.patchid, rev2.patchid); 375 } 376 377 const struct adreno_info *adreno_info(struct adreno_rev rev) 378 { 379 int i; 380 381 /* identify gpu: */ 382 for (i = 0; i < ARRAY_SIZE(gpulist); i++) { 383 const struct adreno_info *info = &gpulist[i]; 384 if (adreno_cmp_rev(info->rev, rev)) 385 return info; 386 } 387 388 return NULL; 389 } 390 391 struct msm_gpu *adreno_load_gpu(struct drm_device *dev) 392 { 393 struct msm_drm_private *priv = dev->dev_private; 394 struct platform_device *pdev = priv->gpu_pdev; 395 struct msm_gpu *gpu = NULL; 396 struct adreno_gpu *adreno_gpu; 397 int ret; 398 399 if (pdev) 400 gpu = dev_to_gpu(&pdev->dev); 401 402 if (!gpu) { 403 dev_err_once(dev->dev, "no GPU device was found\n"); 404 return NULL; 405 } 406 407 adreno_gpu = to_adreno_gpu(gpu); 408 409 /* 410 * The number one reason for HW init to fail is if the firmware isn't 411 * loaded yet. Try that first and don't bother continuing on 412 * otherwise 413 */ 414 415 ret = adreno_load_fw(adreno_gpu); 416 if (ret) 417 return NULL; 418 419 /* Make sure pm runtime is active and reset any previous errors */ 420 pm_runtime_set_active(&pdev->dev); 421 422 ret = pm_runtime_get_sync(&pdev->dev); 423 if (ret < 0) { 424 pm_runtime_put_sync(&pdev->dev); 425 DRM_DEV_ERROR(dev->dev, "Couldn't power up the GPU: %d\n", ret); 426 return NULL; 427 } 428 429 mutex_lock(&gpu->lock); 430 ret = msm_gpu_hw_init(gpu); 431 mutex_unlock(&gpu->lock); 432 pm_runtime_put_autosuspend(&pdev->dev); 433 if (ret) { 434 DRM_DEV_ERROR(dev->dev, "gpu hw init failed: %d\n", ret); 435 return NULL; 436 } 437 438 #ifdef CONFIG_DEBUG_FS 439 if (gpu->funcs->debugfs_init) { 440 gpu->funcs->debugfs_init(gpu, dev->primary); 441 gpu->funcs->debugfs_init(gpu, dev->render); 442 } 443 #endif 444 445 return gpu; 446 } 447 448 static int find_chipid(struct device *dev, struct adreno_rev *rev) 449 { 450 struct device_node *node = dev->of_node; 451 const char *compat; 452 int ret; 453 u32 chipid; 454 455 /* first search the compat strings for qcom,adreno-XYZ.W: */ 456 ret = of_property_read_string_index(node, "compatible", 0, &compat); 457 if (ret == 0) { 458 unsigned int r, patch; 459 460 if (sscanf(compat, "qcom,adreno-%u.%u", &r, &patch) == 2 || 461 sscanf(compat, "amd,imageon-%u.%u", &r, &patch) == 2) { 462 rev->core = r / 100; 463 r %= 100; 464 rev->major = r / 10; 465 r %= 10; 466 rev->minor = r; 467 rev->patchid = patch; 468 469 return 0; 470 } 471 } 472 473 /* and if that fails, fall back to legacy "qcom,chipid" property: */ 474 ret = of_property_read_u32(node, "qcom,chipid", &chipid); 475 if (ret) { 476 DRM_DEV_ERROR(dev, "could not parse qcom,chipid: %d\n", ret); 477 return ret; 478 } 479 480 rev->core = (chipid >> 24) & 0xff; 481 rev->major = (chipid >> 16) & 0xff; 482 rev->minor = (chipid >> 8) & 0xff; 483 rev->patchid = (chipid & 0xff); 484 485 dev_warn(dev, "Using legacy qcom,chipid binding!\n"); 486 dev_warn(dev, "Use compatible qcom,adreno-%u%u%u.%u instead.\n", 487 rev->core, rev->major, rev->minor, rev->patchid); 488 489 return 0; 490 } 491 492 static int adreno_bind(struct device *dev, struct device *master, void *data) 493 { 494 static struct adreno_platform_config config = {}; 495 const struct adreno_info *info; 496 struct msm_drm_private *priv = dev_get_drvdata(master); 497 struct drm_device *drm = priv->dev; 498 struct msm_gpu *gpu; 499 int ret; 500 501 ret = find_chipid(dev, &config.rev); 502 if (ret) 503 return ret; 504 505 dev->platform_data = &config; 506 priv->gpu_pdev = to_platform_device(dev); 507 508 info = adreno_info(config.rev); 509 510 if (!info) { 511 dev_warn(drm->dev, "Unknown GPU revision: %u.%u.%u.%u\n", 512 config.rev.core, config.rev.major, 513 config.rev.minor, config.rev.patchid); 514 return -ENXIO; 515 } 516 517 DBG("Found GPU: %u.%u.%u.%u", config.rev.core, config.rev.major, 518 config.rev.minor, config.rev.patchid); 519 520 priv->is_a2xx = config.rev.core == 2; 521 priv->has_cached_coherent = config.rev.core >= 6; 522 523 gpu = info->init(drm); 524 if (IS_ERR(gpu)) { 525 dev_warn(drm->dev, "failed to load adreno gpu\n"); 526 return PTR_ERR(gpu); 527 } 528 529 return 0; 530 } 531 532 static void adreno_unbind(struct device *dev, struct device *master, 533 void *data) 534 { 535 struct msm_drm_private *priv = dev_get_drvdata(master); 536 struct msm_gpu *gpu = dev_to_gpu(dev); 537 538 pm_runtime_force_suspend(dev); 539 gpu->funcs->destroy(gpu); 540 541 priv->gpu_pdev = NULL; 542 } 543 544 static const struct component_ops a3xx_ops = { 545 .bind = adreno_bind, 546 .unbind = adreno_unbind, 547 }; 548 549 static void adreno_device_register_headless(void) 550 { 551 /* on imx5, we don't have a top-level mdp/dpu node 552 * this creates a dummy node for the driver for that case 553 */ 554 struct platform_device_info dummy_info = { 555 .parent = NULL, 556 .name = "msm", 557 .id = -1, 558 .res = NULL, 559 .num_res = 0, 560 .data = NULL, 561 .size_data = 0, 562 .dma_mask = ~0, 563 }; 564 platform_device_register_full(&dummy_info); 565 } 566 567 static int adreno_probe(struct platform_device *pdev) 568 { 569 570 int ret; 571 572 ret = component_add(&pdev->dev, &a3xx_ops); 573 if (ret) 574 return ret; 575 576 if (of_device_is_compatible(pdev->dev.of_node, "amd,imageon")) 577 adreno_device_register_headless(); 578 579 return 0; 580 } 581 582 static int adreno_remove(struct platform_device *pdev) 583 { 584 component_del(&pdev->dev, &a3xx_ops); 585 return 0; 586 } 587 588 static void adreno_shutdown(struct platform_device *pdev) 589 { 590 pm_runtime_force_suspend(&pdev->dev); 591 } 592 593 static const struct of_device_id dt_match[] = { 594 { .compatible = "qcom,adreno" }, 595 { .compatible = "qcom,adreno-3xx" }, 596 /* for compatibility with imx5 gpu: */ 597 { .compatible = "amd,imageon" }, 598 /* for backwards compat w/ downstream kgsl DT files: */ 599 { .compatible = "qcom,kgsl-3d0" }, 600 {} 601 }; 602 603 #ifdef CONFIG_PM 604 static int adreno_resume(struct device *dev) 605 { 606 struct msm_gpu *gpu = dev_to_gpu(dev); 607 608 return gpu->funcs->pm_resume(gpu); 609 } 610 611 static int adreno_suspend(struct device *dev) 612 { 613 struct msm_gpu *gpu = dev_to_gpu(dev); 614 615 return gpu->funcs->pm_suspend(gpu); 616 } 617 #endif 618 619 static const struct dev_pm_ops adreno_pm_ops = { 620 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) 621 SET_RUNTIME_PM_OPS(adreno_suspend, adreno_resume, NULL) 622 }; 623 624 static struct platform_driver adreno_driver = { 625 .probe = adreno_probe, 626 .remove = adreno_remove, 627 .shutdown = adreno_shutdown, 628 .driver = { 629 .name = "adreno", 630 .of_match_table = dt_match, 631 .pm = &adreno_pm_ops, 632 }, 633 }; 634 635 void __init adreno_register(void) 636 { 637 platform_driver_register(&adreno_driver); 638 } 639 640 void __exit adreno_unregister(void) 641 { 642 platform_driver_unregister(&adreno_driver); 643 } 644