1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013-2014 Red Hat 4 * Author: Rob Clark <robdclark@gmail.com> 5 * 6 * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved. 7 */ 8 9 #include "adreno_gpu.h" 10 11 bool hang_debug = false; 12 MODULE_PARM_DESC(hang_debug, "Dump registers when hang is detected (can be slow!)"); 13 module_param_named(hang_debug, hang_debug, bool, 0600); 14 15 bool snapshot_debugbus = false; 16 MODULE_PARM_DESC(snapshot_debugbus, "Include debugbus sections in GPU devcoredump (if not fused off)"); 17 module_param_named(snapshot_debugbus, snapshot_debugbus, bool, 0600); 18 19 bool allow_vram_carveout = false; 20 MODULE_PARM_DESC(allow_vram_carveout, "Allow using VRAM Carveout, in place of IOMMU"); 21 module_param_named(allow_vram_carveout, allow_vram_carveout, bool, 0600); 22 23 static const struct adreno_info gpulist[] = { 24 { 25 .rev = ADRENO_REV(2, 0, 0, 0), 26 .revn = 200, 27 .name = "A200", 28 .fw = { 29 [ADRENO_FW_PM4] = "yamato_pm4.fw", 30 [ADRENO_FW_PFP] = "yamato_pfp.fw", 31 }, 32 .gmem = SZ_256K, 33 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 34 .init = a2xx_gpu_init, 35 }, { /* a200 on i.mx51 has only 128kib gmem */ 36 .rev = ADRENO_REV(2, 0, 0, 1), 37 .revn = 201, 38 .name = "A200", 39 .fw = { 40 [ADRENO_FW_PM4] = "yamato_pm4.fw", 41 [ADRENO_FW_PFP] = "yamato_pfp.fw", 42 }, 43 .gmem = SZ_128K, 44 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 45 .init = a2xx_gpu_init, 46 }, { 47 .rev = ADRENO_REV(2, 2, 0, ANY_ID), 48 .revn = 220, 49 .name = "A220", 50 .fw = { 51 [ADRENO_FW_PM4] = "leia_pm4_470.fw", 52 [ADRENO_FW_PFP] = "leia_pfp_470.fw", 53 }, 54 .gmem = SZ_512K, 55 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 56 .init = a2xx_gpu_init, 57 }, { 58 .rev = ADRENO_REV(3, 0, 5, ANY_ID), 59 .revn = 305, 60 .name = "A305", 61 .fw = { 62 [ADRENO_FW_PM4] = "a300_pm4.fw", 63 [ADRENO_FW_PFP] = "a300_pfp.fw", 64 }, 65 .gmem = SZ_256K, 66 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 67 .init = a3xx_gpu_init, 68 }, { 69 .rev = ADRENO_REV(3, 0, 6, 0), 70 .revn = 307, /* because a305c is revn==306 */ 71 .name = "A306", 72 .fw = { 73 [ADRENO_FW_PM4] = "a300_pm4.fw", 74 [ADRENO_FW_PFP] = "a300_pfp.fw", 75 }, 76 .gmem = SZ_128K, 77 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 78 .init = a3xx_gpu_init, 79 }, { 80 .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID), 81 .revn = 320, 82 .name = "A320", 83 .fw = { 84 [ADRENO_FW_PM4] = "a300_pm4.fw", 85 [ADRENO_FW_PFP] = "a300_pfp.fw", 86 }, 87 .gmem = SZ_512K, 88 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 89 .init = a3xx_gpu_init, 90 }, { 91 .rev = ADRENO_REV(3, 3, 0, ANY_ID), 92 .revn = 330, 93 .name = "A330", 94 .fw = { 95 [ADRENO_FW_PM4] = "a330_pm4.fw", 96 [ADRENO_FW_PFP] = "a330_pfp.fw", 97 }, 98 .gmem = SZ_1M, 99 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 100 .init = a3xx_gpu_init, 101 }, { 102 .rev = ADRENO_REV(4, 0, 5, ANY_ID), 103 .revn = 405, 104 .name = "A405", 105 .fw = { 106 [ADRENO_FW_PM4] = "a420_pm4.fw", 107 [ADRENO_FW_PFP] = "a420_pfp.fw", 108 }, 109 .gmem = SZ_256K, 110 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 111 .init = a4xx_gpu_init, 112 }, { 113 .rev = ADRENO_REV(4, 2, 0, ANY_ID), 114 .revn = 420, 115 .name = "A420", 116 .fw = { 117 [ADRENO_FW_PM4] = "a420_pm4.fw", 118 [ADRENO_FW_PFP] = "a420_pfp.fw", 119 }, 120 .gmem = (SZ_1M + SZ_512K), 121 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 122 .init = a4xx_gpu_init, 123 }, { 124 .rev = ADRENO_REV(4, 3, 0, ANY_ID), 125 .revn = 430, 126 .name = "A430", 127 .fw = { 128 [ADRENO_FW_PM4] = "a420_pm4.fw", 129 [ADRENO_FW_PFP] = "a420_pfp.fw", 130 }, 131 .gmem = (SZ_1M + SZ_512K), 132 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 133 .init = a4xx_gpu_init, 134 }, { 135 .rev = ADRENO_REV(5, 0, 6, ANY_ID), 136 .revn = 506, 137 .name = "A506", 138 .fw = { 139 [ADRENO_FW_PM4] = "a530_pm4.fw", 140 [ADRENO_FW_PFP] = "a530_pfp.fw", 141 }, 142 .gmem = (SZ_128K + SZ_8K), 143 /* 144 * Increase inactive period to 250 to avoid bouncing 145 * the GDSC which appears to make it grumpy 146 */ 147 .inactive_period = 250, 148 .quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI | 149 ADRENO_QUIRK_LMLOADKILL_DISABLE, 150 .init = a5xx_gpu_init, 151 .zapfw = "a506_zap.mdt", 152 }, { 153 .rev = ADRENO_REV(5, 0, 8, ANY_ID), 154 .revn = 508, 155 .name = "A508", 156 .fw = { 157 [ADRENO_FW_PM4] = "a530_pm4.fw", 158 [ADRENO_FW_PFP] = "a530_pfp.fw", 159 }, 160 .gmem = (SZ_128K + SZ_8K), 161 /* 162 * Increase inactive period to 250 to avoid bouncing 163 * the GDSC which appears to make it grumpy 164 */ 165 .inactive_period = 250, 166 .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE, 167 .init = a5xx_gpu_init, 168 .zapfw = "a508_zap.mdt", 169 }, { 170 .rev = ADRENO_REV(5, 0, 9, ANY_ID), 171 .revn = 509, 172 .name = "A509", 173 .fw = { 174 [ADRENO_FW_PM4] = "a530_pm4.fw", 175 [ADRENO_FW_PFP] = "a530_pfp.fw", 176 }, 177 .gmem = (SZ_256K + SZ_16K), 178 /* 179 * Increase inactive period to 250 to avoid bouncing 180 * the GDSC which appears to make it grumpy 181 */ 182 .inactive_period = 250, 183 .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE, 184 .init = a5xx_gpu_init, 185 /* Adreno 509 uses the same ZAP as 512 */ 186 .zapfw = "a512_zap.mdt", 187 }, { 188 .rev = ADRENO_REV(5, 1, 0, ANY_ID), 189 .revn = 510, 190 .name = "A510", 191 .fw = { 192 [ADRENO_FW_PM4] = "a530_pm4.fw", 193 [ADRENO_FW_PFP] = "a530_pfp.fw", 194 }, 195 .gmem = SZ_256K, 196 /* 197 * Increase inactive period to 250 to avoid bouncing 198 * the GDSC which appears to make it grumpy 199 */ 200 .inactive_period = 250, 201 .init = a5xx_gpu_init, 202 }, { 203 .rev = ADRENO_REV(5, 1, 2, ANY_ID), 204 .revn = 512, 205 .name = "A512", 206 .fw = { 207 [ADRENO_FW_PM4] = "a530_pm4.fw", 208 [ADRENO_FW_PFP] = "a530_pfp.fw", 209 }, 210 .gmem = (SZ_256K + SZ_16K), 211 /* 212 * Increase inactive period to 250 to avoid bouncing 213 * the GDSC which appears to make it grumpy 214 */ 215 .inactive_period = 250, 216 .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE, 217 .init = a5xx_gpu_init, 218 .zapfw = "a512_zap.mdt", 219 }, { 220 .rev = ADRENO_REV(5, 3, 0, 2), 221 .revn = 530, 222 .name = "A530", 223 .fw = { 224 [ADRENO_FW_PM4] = "a530_pm4.fw", 225 [ADRENO_FW_PFP] = "a530_pfp.fw", 226 [ADRENO_FW_GPMU] = "a530v3_gpmu.fw2", 227 }, 228 .gmem = SZ_1M, 229 /* 230 * Increase inactive period to 250 to avoid bouncing 231 * the GDSC which appears to make it grumpy 232 */ 233 .inactive_period = 250, 234 .quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI | 235 ADRENO_QUIRK_FAULT_DETECT_MASK, 236 .init = a5xx_gpu_init, 237 .zapfw = "a530_zap.mdt", 238 }, { 239 .rev = ADRENO_REV(5, 4, 0, ANY_ID), 240 .revn = 540, 241 .name = "A540", 242 .fw = { 243 [ADRENO_FW_PM4] = "a530_pm4.fw", 244 [ADRENO_FW_PFP] = "a530_pfp.fw", 245 [ADRENO_FW_GPMU] = "a540_gpmu.fw2", 246 }, 247 .gmem = SZ_1M, 248 /* 249 * Increase inactive period to 250 to avoid bouncing 250 * the GDSC which appears to make it grumpy 251 */ 252 .inactive_period = 250, 253 .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE, 254 .init = a5xx_gpu_init, 255 .zapfw = "a540_zap.mdt", 256 }, { 257 .rev = ADRENO_REV(6, 1, 8, ANY_ID), 258 .revn = 618, 259 .name = "A618", 260 .fw = { 261 [ADRENO_FW_SQE] = "a630_sqe.fw", 262 [ADRENO_FW_GMU] = "a630_gmu.bin", 263 }, 264 .gmem = SZ_512K, 265 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 266 .init = a6xx_gpu_init, 267 }, { 268 .rev = ADRENO_REV(6, 1, 9, ANY_ID), 269 .revn = 619, 270 .name = "A619", 271 .fw = { 272 [ADRENO_FW_SQE] = "a630_sqe.fw", 273 [ADRENO_FW_GMU] = "a619_gmu.bin", 274 }, 275 .gmem = SZ_512K, 276 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 277 .init = a6xx_gpu_init, 278 .zapfw = "a615_zap.mdt", 279 .hwcg = a615_hwcg, 280 }, { 281 .rev = ADRENO_REV(6, 3, 0, ANY_ID), 282 .revn = 630, 283 .name = "A630", 284 .fw = { 285 [ADRENO_FW_SQE] = "a630_sqe.fw", 286 [ADRENO_FW_GMU] = "a630_gmu.bin", 287 }, 288 .gmem = SZ_1M, 289 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 290 .init = a6xx_gpu_init, 291 .zapfw = "a630_zap.mdt", 292 .hwcg = a630_hwcg, 293 }, { 294 .rev = ADRENO_REV(6, 4, 0, ANY_ID), 295 .revn = 640, 296 .name = "A640", 297 .fw = { 298 [ADRENO_FW_SQE] = "a630_sqe.fw", 299 [ADRENO_FW_GMU] = "a640_gmu.bin", 300 }, 301 .gmem = SZ_1M, 302 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 303 .init = a6xx_gpu_init, 304 .zapfw = "a640_zap.mdt", 305 .hwcg = a640_hwcg, 306 }, { 307 .rev = ADRENO_REV(6, 5, 0, ANY_ID), 308 .revn = 650, 309 .name = "A650", 310 .fw = { 311 [ADRENO_FW_SQE] = "a650_sqe.fw", 312 [ADRENO_FW_GMU] = "a650_gmu.bin", 313 }, 314 .gmem = SZ_1M + SZ_128K, 315 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 316 .init = a6xx_gpu_init, 317 .zapfw = "a650_zap.mdt", 318 .hwcg = a650_hwcg, 319 .address_space_size = SZ_16G, 320 }, { 321 .rev = ADRENO_REV(6, 6, 0, ANY_ID), 322 .revn = 660, 323 .name = "A660", 324 .fw = { 325 [ADRENO_FW_SQE] = "a660_sqe.fw", 326 [ADRENO_FW_GMU] = "a660_gmu.bin", 327 }, 328 .gmem = SZ_1M + SZ_512K, 329 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 330 .init = a6xx_gpu_init, 331 .zapfw = "a660_zap.mdt", 332 .hwcg = a660_hwcg, 333 .address_space_size = SZ_16G, 334 }, { 335 .rev = ADRENO_REV(6, 3, 5, ANY_ID), 336 .fw = { 337 [ADRENO_FW_SQE] = "a660_sqe.fw", 338 [ADRENO_FW_GMU] = "a660_gmu.bin", 339 }, 340 .gmem = SZ_512K, 341 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 342 .init = a6xx_gpu_init, 343 .hwcg = a660_hwcg, 344 .address_space_size = SZ_16G, 345 }, { 346 .rev = ADRENO_REV(6, 8, 0, ANY_ID), 347 .revn = 680, 348 .name = "A680", 349 .fw = { 350 [ADRENO_FW_SQE] = "a630_sqe.fw", 351 [ADRENO_FW_GMU] = "a640_gmu.bin", 352 }, 353 .gmem = SZ_2M, 354 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 355 .init = a6xx_gpu_init, 356 .zapfw = "a640_zap.mdt", 357 .hwcg = a640_hwcg, 358 }, 359 }; 360 361 MODULE_FIRMWARE("qcom/a300_pm4.fw"); 362 MODULE_FIRMWARE("qcom/a300_pfp.fw"); 363 MODULE_FIRMWARE("qcom/a330_pm4.fw"); 364 MODULE_FIRMWARE("qcom/a330_pfp.fw"); 365 MODULE_FIRMWARE("qcom/a420_pm4.fw"); 366 MODULE_FIRMWARE("qcom/a420_pfp.fw"); 367 MODULE_FIRMWARE("qcom/a530_pm4.fw"); 368 MODULE_FIRMWARE("qcom/a530_pfp.fw"); 369 MODULE_FIRMWARE("qcom/a530v3_gpmu.fw2"); 370 MODULE_FIRMWARE("qcom/a530_zap.mdt"); 371 MODULE_FIRMWARE("qcom/a530_zap.b00"); 372 MODULE_FIRMWARE("qcom/a530_zap.b01"); 373 MODULE_FIRMWARE("qcom/a530_zap.b02"); 374 MODULE_FIRMWARE("qcom/a619_gmu.bin"); 375 MODULE_FIRMWARE("qcom/a630_sqe.fw"); 376 MODULE_FIRMWARE("qcom/a630_gmu.bin"); 377 MODULE_FIRMWARE("qcom/a630_zap.mbn"); 378 379 static inline bool _rev_match(uint8_t entry, uint8_t id) 380 { 381 return (entry == ANY_ID) || (entry == id); 382 } 383 384 bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2) 385 { 386 387 return _rev_match(rev1.core, rev2.core) && 388 _rev_match(rev1.major, rev2.major) && 389 _rev_match(rev1.minor, rev2.minor) && 390 _rev_match(rev1.patchid, rev2.patchid); 391 } 392 393 const struct adreno_info *adreno_info(struct adreno_rev rev) 394 { 395 int i; 396 397 /* identify gpu: */ 398 for (i = 0; i < ARRAY_SIZE(gpulist); i++) { 399 const struct adreno_info *info = &gpulist[i]; 400 if (adreno_cmp_rev(info->rev, rev)) 401 return info; 402 } 403 404 return NULL; 405 } 406 407 struct msm_gpu *adreno_load_gpu(struct drm_device *dev) 408 { 409 struct msm_drm_private *priv = dev->dev_private; 410 struct platform_device *pdev = priv->gpu_pdev; 411 struct msm_gpu *gpu = NULL; 412 struct adreno_gpu *adreno_gpu; 413 int ret; 414 415 if (pdev) 416 gpu = dev_to_gpu(&pdev->dev); 417 418 if (!gpu) { 419 dev_err_once(dev->dev, "no GPU device was found\n"); 420 return NULL; 421 } 422 423 adreno_gpu = to_adreno_gpu(gpu); 424 425 /* 426 * The number one reason for HW init to fail is if the firmware isn't 427 * loaded yet. Try that first and don't bother continuing on 428 * otherwise 429 */ 430 431 ret = adreno_load_fw(adreno_gpu); 432 if (ret) 433 return NULL; 434 435 if (gpu->funcs->ucode_load) { 436 ret = gpu->funcs->ucode_load(gpu); 437 if (ret) 438 return NULL; 439 } 440 441 /* 442 * Now that we have firmware loaded, and are ready to begin 443 * booting the gpu, go ahead and enable runpm: 444 */ 445 pm_runtime_enable(&pdev->dev); 446 447 ret = pm_runtime_get_sync(&pdev->dev); 448 if (ret < 0) { 449 pm_runtime_put_noidle(&pdev->dev); 450 DRM_DEV_ERROR(dev->dev, "Couldn't power up the GPU: %d\n", ret); 451 goto err_disable_rpm; 452 } 453 454 mutex_lock(&gpu->lock); 455 ret = msm_gpu_hw_init(gpu); 456 mutex_unlock(&gpu->lock); 457 if (ret) { 458 DRM_DEV_ERROR(dev->dev, "gpu hw init failed: %d\n", ret); 459 goto err_put_rpm; 460 } 461 462 pm_runtime_put_autosuspend(&pdev->dev); 463 464 #ifdef CONFIG_DEBUG_FS 465 if (gpu->funcs->debugfs_init) { 466 gpu->funcs->debugfs_init(gpu, dev->primary); 467 gpu->funcs->debugfs_init(gpu, dev->render); 468 } 469 #endif 470 471 return gpu; 472 473 err_put_rpm: 474 pm_runtime_put_sync_suspend(&pdev->dev); 475 err_disable_rpm: 476 pm_runtime_disable(&pdev->dev); 477 478 return NULL; 479 } 480 481 static int find_chipid(struct device *dev, struct adreno_rev *rev) 482 { 483 struct device_node *node = dev->of_node; 484 const char *compat; 485 int ret; 486 u32 chipid; 487 488 /* first search the compat strings for qcom,adreno-XYZ.W: */ 489 ret = of_property_read_string_index(node, "compatible", 0, &compat); 490 if (ret == 0) { 491 unsigned int r, patch; 492 493 if (sscanf(compat, "qcom,adreno-%u.%u", &r, &patch) == 2 || 494 sscanf(compat, "amd,imageon-%u.%u", &r, &patch) == 2) { 495 rev->core = r / 100; 496 r %= 100; 497 rev->major = r / 10; 498 r %= 10; 499 rev->minor = r; 500 rev->patchid = patch; 501 502 return 0; 503 } 504 } 505 506 /* and if that fails, fall back to legacy "qcom,chipid" property: */ 507 ret = of_property_read_u32(node, "qcom,chipid", &chipid); 508 if (ret) { 509 DRM_DEV_ERROR(dev, "could not parse qcom,chipid: %d\n", ret); 510 return ret; 511 } 512 513 rev->core = (chipid >> 24) & 0xff; 514 rev->major = (chipid >> 16) & 0xff; 515 rev->minor = (chipid >> 8) & 0xff; 516 rev->patchid = (chipid & 0xff); 517 518 dev_warn(dev, "Using legacy qcom,chipid binding!\n"); 519 dev_warn(dev, "Use compatible qcom,adreno-%u%u%u.%u instead.\n", 520 rev->core, rev->major, rev->minor, rev->patchid); 521 522 return 0; 523 } 524 525 static int adreno_bind(struct device *dev, struct device *master, void *data) 526 { 527 static struct adreno_platform_config config = {}; 528 const struct adreno_info *info; 529 struct msm_drm_private *priv = dev_get_drvdata(master); 530 struct drm_device *drm = priv->dev; 531 struct msm_gpu *gpu; 532 int ret; 533 534 ret = find_chipid(dev, &config.rev); 535 if (ret) 536 return ret; 537 538 dev->platform_data = &config; 539 priv->gpu_pdev = to_platform_device(dev); 540 541 info = adreno_info(config.rev); 542 543 if (!info) { 544 dev_warn(drm->dev, "Unknown GPU revision: %u.%u.%u.%u\n", 545 config.rev.core, config.rev.major, 546 config.rev.minor, config.rev.patchid); 547 return -ENXIO; 548 } 549 550 DBG("Found GPU: %u.%u.%u.%u", config.rev.core, config.rev.major, 551 config.rev.minor, config.rev.patchid); 552 553 priv->is_a2xx = config.rev.core == 2; 554 priv->has_cached_coherent = config.rev.core >= 6; 555 556 gpu = info->init(drm); 557 if (IS_ERR(gpu)) { 558 dev_warn(drm->dev, "failed to load adreno gpu\n"); 559 return PTR_ERR(gpu); 560 } 561 562 ret = dev_pm_opp_of_find_icc_paths(dev, NULL); 563 if (ret) 564 return ret; 565 566 return 0; 567 } 568 569 static int adreno_system_suspend(struct device *dev); 570 static void adreno_unbind(struct device *dev, struct device *master, 571 void *data) 572 { 573 struct msm_drm_private *priv = dev_get_drvdata(master); 574 struct msm_gpu *gpu = dev_to_gpu(dev); 575 576 if (pm_runtime_enabled(dev)) 577 WARN_ON_ONCE(adreno_system_suspend(dev)); 578 gpu->funcs->destroy(gpu); 579 580 priv->gpu_pdev = NULL; 581 } 582 583 static const struct component_ops a3xx_ops = { 584 .bind = adreno_bind, 585 .unbind = adreno_unbind, 586 }; 587 588 static void adreno_device_register_headless(void) 589 { 590 /* on imx5, we don't have a top-level mdp/dpu node 591 * this creates a dummy node for the driver for that case 592 */ 593 struct platform_device_info dummy_info = { 594 .parent = NULL, 595 .name = "msm", 596 .id = -1, 597 .res = NULL, 598 .num_res = 0, 599 .data = NULL, 600 .size_data = 0, 601 .dma_mask = ~0, 602 }; 603 platform_device_register_full(&dummy_info); 604 } 605 606 static int adreno_probe(struct platform_device *pdev) 607 { 608 609 int ret; 610 611 ret = component_add(&pdev->dev, &a3xx_ops); 612 if (ret) 613 return ret; 614 615 if (of_device_is_compatible(pdev->dev.of_node, "amd,imageon")) 616 adreno_device_register_headless(); 617 618 return 0; 619 } 620 621 static int adreno_remove(struct platform_device *pdev) 622 { 623 component_del(&pdev->dev, &a3xx_ops); 624 return 0; 625 } 626 627 static void adreno_shutdown(struct platform_device *pdev) 628 { 629 WARN_ON_ONCE(adreno_system_suspend(&pdev->dev)); 630 } 631 632 static const struct of_device_id dt_match[] = { 633 { .compatible = "qcom,adreno" }, 634 { .compatible = "qcom,adreno-3xx" }, 635 /* for compatibility with imx5 gpu: */ 636 { .compatible = "amd,imageon" }, 637 /* for backwards compat w/ downstream kgsl DT files: */ 638 { .compatible = "qcom,kgsl-3d0" }, 639 {} 640 }; 641 642 static int adreno_runtime_resume(struct device *dev) 643 { 644 struct msm_gpu *gpu = dev_to_gpu(dev); 645 646 return gpu->funcs->pm_resume(gpu); 647 } 648 649 static int adreno_runtime_suspend(struct device *dev) 650 { 651 struct msm_gpu *gpu = dev_to_gpu(dev); 652 653 /* 654 * We should be holding a runpm ref, which will prevent 655 * runtime suspend. In the system suspend path, we've 656 * already waited for active jobs to complete. 657 */ 658 WARN_ON_ONCE(gpu->active_submits); 659 660 return gpu->funcs->pm_suspend(gpu); 661 } 662 663 static void suspend_scheduler(struct msm_gpu *gpu) 664 { 665 int i; 666 667 /* 668 * Shut down the scheduler before we force suspend, so that 669 * suspend isn't racing with scheduler kthread feeding us 670 * more work. 671 * 672 * Note, we just want to park the thread, and let any jobs 673 * that are already on the hw queue complete normally, as 674 * opposed to the drm_sched_stop() path used for handling 675 * faulting/timed-out jobs. We can't really cancel any jobs 676 * already on the hw queue without racing with the GPU. 677 */ 678 for (i = 0; i < gpu->nr_rings; i++) { 679 struct drm_gpu_scheduler *sched = &gpu->rb[i]->sched; 680 kthread_park(sched->thread); 681 } 682 } 683 684 static void resume_scheduler(struct msm_gpu *gpu) 685 { 686 int i; 687 688 for (i = 0; i < gpu->nr_rings; i++) { 689 struct drm_gpu_scheduler *sched = &gpu->rb[i]->sched; 690 kthread_unpark(sched->thread); 691 } 692 } 693 694 static int adreno_system_suspend(struct device *dev) 695 { 696 struct msm_gpu *gpu = dev_to_gpu(dev); 697 int remaining, ret; 698 699 if (!gpu) 700 return 0; 701 702 suspend_scheduler(gpu); 703 704 remaining = wait_event_timeout(gpu->retire_event, 705 gpu->active_submits == 0, 706 msecs_to_jiffies(1000)); 707 if (remaining == 0) { 708 dev_err(dev, "Timeout waiting for GPU to suspend\n"); 709 ret = -EBUSY; 710 goto out; 711 } 712 713 ret = pm_runtime_force_suspend(dev); 714 out: 715 if (ret) 716 resume_scheduler(gpu); 717 718 return ret; 719 } 720 721 static int adreno_system_resume(struct device *dev) 722 { 723 struct msm_gpu *gpu = dev_to_gpu(dev); 724 725 if (!gpu) 726 return 0; 727 728 resume_scheduler(gpu); 729 return pm_runtime_force_resume(dev); 730 } 731 732 static const struct dev_pm_ops adreno_pm_ops = { 733 SYSTEM_SLEEP_PM_OPS(adreno_system_suspend, adreno_system_resume) 734 RUNTIME_PM_OPS(adreno_runtime_suspend, adreno_runtime_resume, NULL) 735 }; 736 737 static struct platform_driver adreno_driver = { 738 .probe = adreno_probe, 739 .remove = adreno_remove, 740 .shutdown = adreno_shutdown, 741 .driver = { 742 .name = "adreno", 743 .of_match_table = dt_match, 744 .pm = &adreno_pm_ops, 745 }, 746 }; 747 748 void __init adreno_register(void) 749 { 750 platform_driver_register(&adreno_driver); 751 } 752 753 void __exit adreno_unregister(void) 754 { 755 platform_driver_unregister(&adreno_driver); 756 } 757