1 #ifndef ADRENO_COMMON_XML
2 #define ADRENO_COMMON_XML
3 
4 /* Autogenerated file, DO NOT EDIT manually!
5 
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
9 
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    431 bytes, from 2016-04-26 17:56:44)
12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2016-02-10 17:07:21)
13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32907 bytes, from 2016-11-26 23:01:08)
14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  12025 bytes, from 2016-11-26 23:01:08)
15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  22544 bytes, from 2016-11-26 23:01:08)
16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  83840 bytes, from 2016-11-26 23:01:08)
17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          ( 110765 bytes, from 2016-11-26 23:01:48)
18 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml          (  90321 bytes, from 2016-11-28 16:50:05)
19 - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2015-09-24 17:30:00)
20 
21 Copyright (C) 2013-2016 by the following authors:
22 - Rob Clark <robdclark@gmail.com> (robclark)
23 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
24 
25 Permission is hereby granted, free of charge, to any person obtaining
26 a copy of this software and associated documentation files (the
27 "Software"), to deal in the Software without restriction, including
28 without limitation the rights to use, copy, modify, merge, publish,
29 distribute, sublicense, and/or sell copies of the Software, and to
30 permit persons to whom the Software is furnished to do so, subject to
31 the following conditions:
32 
33 The above copyright notice and this permission notice (including the
34 next paragraph) shall be included in all copies or substantial
35 portions of the Software.
36 
37 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
39 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
40 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
41 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
42 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
43 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
44 */
45 
46 
47 enum adreno_pa_su_sc_draw {
48 	PC_DRAW_POINTS = 0,
49 	PC_DRAW_LINES = 1,
50 	PC_DRAW_TRIANGLES = 2,
51 };
52 
53 enum adreno_compare_func {
54 	FUNC_NEVER = 0,
55 	FUNC_LESS = 1,
56 	FUNC_EQUAL = 2,
57 	FUNC_LEQUAL = 3,
58 	FUNC_GREATER = 4,
59 	FUNC_NOTEQUAL = 5,
60 	FUNC_GEQUAL = 6,
61 	FUNC_ALWAYS = 7,
62 };
63 
64 enum adreno_stencil_op {
65 	STENCIL_KEEP = 0,
66 	STENCIL_ZERO = 1,
67 	STENCIL_REPLACE = 2,
68 	STENCIL_INCR_CLAMP = 3,
69 	STENCIL_DECR_CLAMP = 4,
70 	STENCIL_INVERT = 5,
71 	STENCIL_INCR_WRAP = 6,
72 	STENCIL_DECR_WRAP = 7,
73 };
74 
75 enum adreno_rb_blend_factor {
76 	FACTOR_ZERO = 0,
77 	FACTOR_ONE = 1,
78 	FACTOR_SRC_COLOR = 4,
79 	FACTOR_ONE_MINUS_SRC_COLOR = 5,
80 	FACTOR_SRC_ALPHA = 6,
81 	FACTOR_ONE_MINUS_SRC_ALPHA = 7,
82 	FACTOR_DST_COLOR = 8,
83 	FACTOR_ONE_MINUS_DST_COLOR = 9,
84 	FACTOR_DST_ALPHA = 10,
85 	FACTOR_ONE_MINUS_DST_ALPHA = 11,
86 	FACTOR_CONSTANT_COLOR = 12,
87 	FACTOR_ONE_MINUS_CONSTANT_COLOR = 13,
88 	FACTOR_CONSTANT_ALPHA = 14,
89 	FACTOR_ONE_MINUS_CONSTANT_ALPHA = 15,
90 	FACTOR_SRC_ALPHA_SATURATE = 16,
91 	FACTOR_SRC1_COLOR = 20,
92 	FACTOR_ONE_MINUS_SRC1_COLOR = 21,
93 	FACTOR_SRC1_ALPHA = 22,
94 	FACTOR_ONE_MINUS_SRC1_ALPHA = 23,
95 };
96 
97 enum adreno_rb_surface_endian {
98 	ENDIAN_NONE = 0,
99 	ENDIAN_8IN16 = 1,
100 	ENDIAN_8IN32 = 2,
101 	ENDIAN_16IN32 = 3,
102 	ENDIAN_8IN64 = 4,
103 	ENDIAN_8IN128 = 5,
104 };
105 
106 enum adreno_rb_dither_mode {
107 	DITHER_DISABLE = 0,
108 	DITHER_ALWAYS = 1,
109 	DITHER_IF_ALPHA_OFF = 2,
110 };
111 
112 enum adreno_rb_depth_format {
113 	DEPTHX_16 = 0,
114 	DEPTHX_24_8 = 1,
115 	DEPTHX_32 = 2,
116 };
117 
118 enum adreno_rb_copy_control_mode {
119 	RB_COPY_RESOLVE = 1,
120 	RB_COPY_CLEAR = 2,
121 	RB_COPY_DEPTH_STENCIL = 5,
122 };
123 
124 enum a3xx_rop_code {
125 	ROP_CLEAR = 0,
126 	ROP_NOR = 1,
127 	ROP_AND_INVERTED = 2,
128 	ROP_COPY_INVERTED = 3,
129 	ROP_AND_REVERSE = 4,
130 	ROP_INVERT = 5,
131 	ROP_NAND = 7,
132 	ROP_AND = 8,
133 	ROP_EQUIV = 9,
134 	ROP_NOOP = 10,
135 	ROP_OR_INVERTED = 11,
136 	ROP_OR_REVERSE = 13,
137 	ROP_OR = 14,
138 	ROP_SET = 15,
139 };
140 
141 enum a3xx_render_mode {
142 	RB_RENDERING_PASS = 0,
143 	RB_TILING_PASS = 1,
144 	RB_RESOLVE_PASS = 2,
145 	RB_COMPUTE_PASS = 3,
146 };
147 
148 enum a3xx_msaa_samples {
149 	MSAA_ONE = 0,
150 	MSAA_TWO = 1,
151 	MSAA_FOUR = 2,
152 };
153 
154 enum a3xx_threadmode {
155 	MULTI = 0,
156 	SINGLE = 1,
157 };
158 
159 enum a3xx_instrbuffermode {
160 	CACHE = 0,
161 	BUFFER = 1,
162 };
163 
164 enum a3xx_threadsize {
165 	TWO_QUADS = 0,
166 	FOUR_QUADS = 1,
167 };
168 
169 enum a3xx_color_swap {
170 	WZYX = 0,
171 	WXYZ = 1,
172 	ZYXW = 2,
173 	XYZW = 3,
174 };
175 
176 enum a3xx_rb_blend_opcode {
177 	BLEND_DST_PLUS_SRC = 0,
178 	BLEND_SRC_MINUS_DST = 1,
179 	BLEND_DST_MINUS_SRC = 2,
180 	BLEND_MIN_DST_SRC = 3,
181 	BLEND_MAX_DST_SRC = 4,
182 };
183 
184 #define REG_AXXX_CP_RB_BASE					0x000001c0
185 
186 #define REG_AXXX_CP_RB_CNTL					0x000001c1
187 #define AXXX_CP_RB_CNTL_BUFSZ__MASK				0x0000003f
188 #define AXXX_CP_RB_CNTL_BUFSZ__SHIFT				0
189 static inline uint32_t AXXX_CP_RB_CNTL_BUFSZ(uint32_t val)
190 {
191 	return ((val) << AXXX_CP_RB_CNTL_BUFSZ__SHIFT) & AXXX_CP_RB_CNTL_BUFSZ__MASK;
192 }
193 #define AXXX_CP_RB_CNTL_BLKSZ__MASK				0x00003f00
194 #define AXXX_CP_RB_CNTL_BLKSZ__SHIFT				8
195 static inline uint32_t AXXX_CP_RB_CNTL_BLKSZ(uint32_t val)
196 {
197 	return ((val) << AXXX_CP_RB_CNTL_BLKSZ__SHIFT) & AXXX_CP_RB_CNTL_BLKSZ__MASK;
198 }
199 #define AXXX_CP_RB_CNTL_BUF_SWAP__MASK				0x00030000
200 #define AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT				16
201 static inline uint32_t AXXX_CP_RB_CNTL_BUF_SWAP(uint32_t val)
202 {
203 	return ((val) << AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT) & AXXX_CP_RB_CNTL_BUF_SWAP__MASK;
204 }
205 #define AXXX_CP_RB_CNTL_POLL_EN					0x00100000
206 #define AXXX_CP_RB_CNTL_NO_UPDATE				0x08000000
207 #define AXXX_CP_RB_CNTL_RPTR_WR_EN				0x80000000
208 
209 #define REG_AXXX_CP_RB_RPTR_ADDR				0x000001c3
210 #define AXXX_CP_RB_RPTR_ADDR_SWAP__MASK				0x00000003
211 #define AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT			0
212 static inline uint32_t AXXX_CP_RB_RPTR_ADDR_SWAP(uint32_t val)
213 {
214 	return ((val) << AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT) & AXXX_CP_RB_RPTR_ADDR_SWAP__MASK;
215 }
216 #define AXXX_CP_RB_RPTR_ADDR_ADDR__MASK				0xfffffffc
217 #define AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT			2
218 static inline uint32_t AXXX_CP_RB_RPTR_ADDR_ADDR(uint32_t val)
219 {
220 	return ((val >> 2) << AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT) & AXXX_CP_RB_RPTR_ADDR_ADDR__MASK;
221 }
222 
223 #define REG_AXXX_CP_RB_RPTR					0x000001c4
224 
225 #define REG_AXXX_CP_RB_WPTR					0x000001c5
226 
227 #define REG_AXXX_CP_RB_WPTR_DELAY				0x000001c6
228 
229 #define REG_AXXX_CP_RB_RPTR_WR					0x000001c7
230 
231 #define REG_AXXX_CP_RB_WPTR_BASE				0x000001c8
232 
233 #define REG_AXXX_CP_QUEUE_THRESHOLDS				0x000001d5
234 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK		0x0000000f
235 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT		0
236 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(uint32_t val)
237 {
238 	return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK;
239 }
240 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK		0x00000f00
241 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT		8
242 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(uint32_t val)
243 {
244 	return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK;
245 }
246 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK		0x000f0000
247 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT		16
248 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(uint32_t val)
249 {
250 	return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK;
251 }
252 
253 #define REG_AXXX_CP_MEQ_THRESHOLDS				0x000001d6
254 #define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK			0x001f0000
255 #define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT			16
256 static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_MEQ_END(uint32_t val)
257 {
258 	return ((val) << AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK;
259 }
260 #define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK			0x1f000000
261 #define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT			24
262 static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_ROQ_END(uint32_t val)
263 {
264 	return ((val) << AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK;
265 }
266 
267 #define REG_AXXX_CP_CSQ_AVAIL					0x000001d7
268 #define AXXX_CP_CSQ_AVAIL_RING__MASK				0x0000007f
269 #define AXXX_CP_CSQ_AVAIL_RING__SHIFT				0
270 static inline uint32_t AXXX_CP_CSQ_AVAIL_RING(uint32_t val)
271 {
272 	return ((val) << AXXX_CP_CSQ_AVAIL_RING__SHIFT) & AXXX_CP_CSQ_AVAIL_RING__MASK;
273 }
274 #define AXXX_CP_CSQ_AVAIL_IB1__MASK				0x00007f00
275 #define AXXX_CP_CSQ_AVAIL_IB1__SHIFT				8
276 static inline uint32_t AXXX_CP_CSQ_AVAIL_IB1(uint32_t val)
277 {
278 	return ((val) << AXXX_CP_CSQ_AVAIL_IB1__SHIFT) & AXXX_CP_CSQ_AVAIL_IB1__MASK;
279 }
280 #define AXXX_CP_CSQ_AVAIL_IB2__MASK				0x007f0000
281 #define AXXX_CP_CSQ_AVAIL_IB2__SHIFT				16
282 static inline uint32_t AXXX_CP_CSQ_AVAIL_IB2(uint32_t val)
283 {
284 	return ((val) << AXXX_CP_CSQ_AVAIL_IB2__SHIFT) & AXXX_CP_CSQ_AVAIL_IB2__MASK;
285 }
286 
287 #define REG_AXXX_CP_STQ_AVAIL					0x000001d8
288 #define AXXX_CP_STQ_AVAIL_ST__MASK				0x0000007f
289 #define AXXX_CP_STQ_AVAIL_ST__SHIFT				0
290 static inline uint32_t AXXX_CP_STQ_AVAIL_ST(uint32_t val)
291 {
292 	return ((val) << AXXX_CP_STQ_AVAIL_ST__SHIFT) & AXXX_CP_STQ_AVAIL_ST__MASK;
293 }
294 
295 #define REG_AXXX_CP_MEQ_AVAIL					0x000001d9
296 #define AXXX_CP_MEQ_AVAIL_MEQ__MASK				0x0000001f
297 #define AXXX_CP_MEQ_AVAIL_MEQ__SHIFT				0
298 static inline uint32_t AXXX_CP_MEQ_AVAIL_MEQ(uint32_t val)
299 {
300 	return ((val) << AXXX_CP_MEQ_AVAIL_MEQ__SHIFT) & AXXX_CP_MEQ_AVAIL_MEQ__MASK;
301 }
302 
303 #define REG_AXXX_SCRATCH_UMSK					0x000001dc
304 #define AXXX_SCRATCH_UMSK_UMSK__MASK				0x000000ff
305 #define AXXX_SCRATCH_UMSK_UMSK__SHIFT				0
306 static inline uint32_t AXXX_SCRATCH_UMSK_UMSK(uint32_t val)
307 {
308 	return ((val) << AXXX_SCRATCH_UMSK_UMSK__SHIFT) & AXXX_SCRATCH_UMSK_UMSK__MASK;
309 }
310 #define AXXX_SCRATCH_UMSK_SWAP__MASK				0x00030000
311 #define AXXX_SCRATCH_UMSK_SWAP__SHIFT				16
312 static inline uint32_t AXXX_SCRATCH_UMSK_SWAP(uint32_t val)
313 {
314 	return ((val) << AXXX_SCRATCH_UMSK_SWAP__SHIFT) & AXXX_SCRATCH_UMSK_SWAP__MASK;
315 }
316 
317 #define REG_AXXX_SCRATCH_ADDR					0x000001dd
318 
319 #define REG_AXXX_CP_ME_RDADDR					0x000001ea
320 
321 #define REG_AXXX_CP_STATE_DEBUG_INDEX				0x000001ec
322 
323 #define REG_AXXX_CP_STATE_DEBUG_DATA				0x000001ed
324 
325 #define REG_AXXX_CP_INT_CNTL					0x000001f2
326 
327 #define REG_AXXX_CP_INT_STATUS					0x000001f3
328 
329 #define REG_AXXX_CP_INT_ACK					0x000001f4
330 
331 #define REG_AXXX_CP_ME_CNTL					0x000001f6
332 #define AXXX_CP_ME_CNTL_BUSY					0x20000000
333 #define AXXX_CP_ME_CNTL_HALT					0x10000000
334 
335 #define REG_AXXX_CP_ME_STATUS					0x000001f7
336 
337 #define REG_AXXX_CP_ME_RAM_WADDR				0x000001f8
338 
339 #define REG_AXXX_CP_ME_RAM_RADDR				0x000001f9
340 
341 #define REG_AXXX_CP_ME_RAM_DATA					0x000001fa
342 
343 #define REG_AXXX_CP_DEBUG					0x000001fc
344 #define AXXX_CP_DEBUG_PREDICATE_DISABLE				0x00800000
345 #define AXXX_CP_DEBUG_PROG_END_PTR_ENABLE			0x01000000
346 #define AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE			0x02000000
347 #define AXXX_CP_DEBUG_PREFETCH_PASS_NOPS			0x04000000
348 #define AXXX_CP_DEBUG_DYNAMIC_CLK_DISABLE			0x08000000
349 #define AXXX_CP_DEBUG_PREFETCH_MATCH_DISABLE			0x10000000
350 #define AXXX_CP_DEBUG_SIMPLE_ME_FLOW_CONTROL			0x40000000
351 #define AXXX_CP_DEBUG_MIU_WRITE_PACK_DISABLE			0x80000000
352 
353 #define REG_AXXX_CP_CSQ_RB_STAT					0x000001fd
354 #define AXXX_CP_CSQ_RB_STAT_RPTR__MASK				0x0000007f
355 #define AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT				0
356 static inline uint32_t AXXX_CP_CSQ_RB_STAT_RPTR(uint32_t val)
357 {
358 	return ((val) << AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_RPTR__MASK;
359 }
360 #define AXXX_CP_CSQ_RB_STAT_WPTR__MASK				0x007f0000
361 #define AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT				16
362 static inline uint32_t AXXX_CP_CSQ_RB_STAT_WPTR(uint32_t val)
363 {
364 	return ((val) << AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_WPTR__MASK;
365 }
366 
367 #define REG_AXXX_CP_CSQ_IB1_STAT				0x000001fe
368 #define AXXX_CP_CSQ_IB1_STAT_RPTR__MASK				0x0000007f
369 #define AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT			0
370 static inline uint32_t AXXX_CP_CSQ_IB1_STAT_RPTR(uint32_t val)
371 {
372 	return ((val) << AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_RPTR__MASK;
373 }
374 #define AXXX_CP_CSQ_IB1_STAT_WPTR__MASK				0x007f0000
375 #define AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT			16
376 static inline uint32_t AXXX_CP_CSQ_IB1_STAT_WPTR(uint32_t val)
377 {
378 	return ((val) << AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_WPTR__MASK;
379 }
380 
381 #define REG_AXXX_CP_CSQ_IB2_STAT				0x000001ff
382 #define AXXX_CP_CSQ_IB2_STAT_RPTR__MASK				0x0000007f
383 #define AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT			0
384 static inline uint32_t AXXX_CP_CSQ_IB2_STAT_RPTR(uint32_t val)
385 {
386 	return ((val) << AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_RPTR__MASK;
387 }
388 #define AXXX_CP_CSQ_IB2_STAT_WPTR__MASK				0x007f0000
389 #define AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT			16
390 static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val)
391 {
392 	return ((val) << AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_WPTR__MASK;
393 }
394 
395 #define REG_AXXX_CP_NON_PREFETCH_CNTRS				0x00000440
396 
397 #define REG_AXXX_CP_STQ_ST_STAT					0x00000443
398 
399 #define REG_AXXX_CP_ST_BASE					0x0000044d
400 
401 #define REG_AXXX_CP_ST_BUFSZ					0x0000044e
402 
403 #define REG_AXXX_CP_MEQ_STAT					0x0000044f
404 
405 #define REG_AXXX_CP_MIU_TAG_STAT				0x00000452
406 
407 #define REG_AXXX_CP_BIN_MASK_LO					0x00000454
408 
409 #define REG_AXXX_CP_BIN_MASK_HI					0x00000455
410 
411 #define REG_AXXX_CP_BIN_SELECT_LO				0x00000456
412 
413 #define REG_AXXX_CP_BIN_SELECT_HI				0x00000457
414 
415 #define REG_AXXX_CP_IB1_BASE					0x00000458
416 
417 #define REG_AXXX_CP_IB1_BUFSZ					0x00000459
418 
419 #define REG_AXXX_CP_IB2_BASE					0x0000045a
420 
421 #define REG_AXXX_CP_IB2_BUFSZ					0x0000045b
422 
423 #define REG_AXXX_CP_STAT					0x0000047f
424 
425 #define REG_AXXX_CP_SCRATCH_REG0				0x00000578
426 
427 #define REG_AXXX_CP_SCRATCH_REG1				0x00000579
428 
429 #define REG_AXXX_CP_SCRATCH_REG2				0x0000057a
430 
431 #define REG_AXXX_CP_SCRATCH_REG3				0x0000057b
432 
433 #define REG_AXXX_CP_SCRATCH_REG4				0x0000057c
434 
435 #define REG_AXXX_CP_SCRATCH_REG5				0x0000057d
436 
437 #define REG_AXXX_CP_SCRATCH_REG6				0x0000057e
438 
439 #define REG_AXXX_CP_SCRATCH_REG7				0x0000057f
440 
441 #define REG_AXXX_CP_ME_VS_EVENT_SRC				0x00000600
442 
443 #define REG_AXXX_CP_ME_VS_EVENT_ADDR				0x00000601
444 
445 #define REG_AXXX_CP_ME_VS_EVENT_DATA				0x00000602
446 
447 #define REG_AXXX_CP_ME_VS_EVENT_ADDR_SWM			0x00000603
448 
449 #define REG_AXXX_CP_ME_VS_EVENT_DATA_SWM			0x00000604
450 
451 #define REG_AXXX_CP_ME_PS_EVENT_SRC				0x00000605
452 
453 #define REG_AXXX_CP_ME_PS_EVENT_ADDR				0x00000606
454 
455 #define REG_AXXX_CP_ME_PS_EVENT_DATA				0x00000607
456 
457 #define REG_AXXX_CP_ME_PS_EVENT_ADDR_SWM			0x00000608
458 
459 #define REG_AXXX_CP_ME_PS_EVENT_DATA_SWM			0x00000609
460 
461 #define REG_AXXX_CP_ME_CF_EVENT_SRC				0x0000060a
462 
463 #define REG_AXXX_CP_ME_CF_EVENT_ADDR				0x0000060b
464 
465 #define REG_AXXX_CP_ME_CF_EVENT_DATA				0x0000060c
466 
467 #define REG_AXXX_CP_ME_NRT_ADDR					0x0000060d
468 
469 #define REG_AXXX_CP_ME_NRT_DATA					0x0000060e
470 
471 #define REG_AXXX_CP_ME_VS_FETCH_DONE_SRC			0x00000612
472 
473 #define REG_AXXX_CP_ME_VS_FETCH_DONE_ADDR			0x00000613
474 
475 #define REG_AXXX_CP_ME_VS_FETCH_DONE_DATA			0x00000614
476 
477 
478 #endif /* ADRENO_COMMON_XML */
479