1 #ifndef ADRENO_COMMON_XML 2 #define ADRENO_COMMON_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2013-11-30 14:47:15) 12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32814 bytes, from 2013-11-30 15:07:33) 14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 8900 bytes, from 2013-10-22 23:57:49) 15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 10574 bytes, from 2013-11-13 05:44:45) 16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 53644 bytes, from 2013-11-30 15:07:33) 17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 8344 bytes, from 2013-11-30 14:49:47) 18 19 Copyright (C) 2013 by the following authors: 20 - Rob Clark <robdclark@gmail.com> (robclark) 21 22 Permission is hereby granted, free of charge, to any person obtaining 23 a copy of this software and associated documentation files (the 24 "Software"), to deal in the Software without restriction, including 25 without limitation the rights to use, copy, modify, merge, publish, 26 distribute, sublicense, and/or sell copies of the Software, and to 27 permit persons to whom the Software is furnished to do so, subject to 28 the following conditions: 29 30 The above copyright notice and this permission notice (including the 31 next paragraph) shall be included in all copies or substantial 32 portions of the Software. 33 34 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 35 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 36 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 37 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 38 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 39 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 40 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43 44 enum adreno_pa_su_sc_draw { 45 PC_DRAW_POINTS = 0, 46 PC_DRAW_LINES = 1, 47 PC_DRAW_TRIANGLES = 2, 48 }; 49 50 enum adreno_compare_func { 51 FUNC_NEVER = 0, 52 FUNC_LESS = 1, 53 FUNC_EQUAL = 2, 54 FUNC_LEQUAL = 3, 55 FUNC_GREATER = 4, 56 FUNC_NOTEQUAL = 5, 57 FUNC_GEQUAL = 6, 58 FUNC_ALWAYS = 7, 59 }; 60 61 enum adreno_stencil_op { 62 STENCIL_KEEP = 0, 63 STENCIL_ZERO = 1, 64 STENCIL_REPLACE = 2, 65 STENCIL_INCR_CLAMP = 3, 66 STENCIL_DECR_CLAMP = 4, 67 STENCIL_INVERT = 5, 68 STENCIL_INCR_WRAP = 6, 69 STENCIL_DECR_WRAP = 7, 70 }; 71 72 enum adreno_rb_blend_factor { 73 FACTOR_ZERO = 0, 74 FACTOR_ONE = 1, 75 FACTOR_SRC_COLOR = 4, 76 FACTOR_ONE_MINUS_SRC_COLOR = 5, 77 FACTOR_SRC_ALPHA = 6, 78 FACTOR_ONE_MINUS_SRC_ALPHA = 7, 79 FACTOR_DST_COLOR = 8, 80 FACTOR_ONE_MINUS_DST_COLOR = 9, 81 FACTOR_DST_ALPHA = 10, 82 FACTOR_ONE_MINUS_DST_ALPHA = 11, 83 FACTOR_CONSTANT_COLOR = 12, 84 FACTOR_ONE_MINUS_CONSTANT_COLOR = 13, 85 FACTOR_CONSTANT_ALPHA = 14, 86 FACTOR_ONE_MINUS_CONSTANT_ALPHA = 15, 87 FACTOR_SRC_ALPHA_SATURATE = 16, 88 }; 89 90 enum adreno_rb_blend_opcode { 91 BLEND_DST_PLUS_SRC = 0, 92 BLEND_SRC_MINUS_DST = 1, 93 BLEND_MIN_DST_SRC = 2, 94 BLEND_MAX_DST_SRC = 3, 95 BLEND_DST_MINUS_SRC = 4, 96 BLEND_DST_PLUS_SRC_BIAS = 5, 97 }; 98 99 enum adreno_rb_surface_endian { 100 ENDIAN_NONE = 0, 101 ENDIAN_8IN16 = 1, 102 ENDIAN_8IN32 = 2, 103 ENDIAN_16IN32 = 3, 104 ENDIAN_8IN64 = 4, 105 ENDIAN_8IN128 = 5, 106 }; 107 108 enum adreno_rb_dither_mode { 109 DITHER_DISABLE = 0, 110 DITHER_ALWAYS = 1, 111 DITHER_IF_ALPHA_OFF = 2, 112 }; 113 114 enum adreno_rb_depth_format { 115 DEPTHX_16 = 0, 116 DEPTHX_24_8 = 1, 117 }; 118 119 #define REG_AXXX_CP_RB_BASE 0x000001c0 120 121 #define REG_AXXX_CP_RB_CNTL 0x000001c1 122 #define AXXX_CP_RB_CNTL_BUFSZ__MASK 0x0000003f 123 #define AXXX_CP_RB_CNTL_BUFSZ__SHIFT 0 124 static inline uint32_t AXXX_CP_RB_CNTL_BUFSZ(uint32_t val) 125 { 126 return ((val) << AXXX_CP_RB_CNTL_BUFSZ__SHIFT) & AXXX_CP_RB_CNTL_BUFSZ__MASK; 127 } 128 #define AXXX_CP_RB_CNTL_BLKSZ__MASK 0x00003f00 129 #define AXXX_CP_RB_CNTL_BLKSZ__SHIFT 8 130 static inline uint32_t AXXX_CP_RB_CNTL_BLKSZ(uint32_t val) 131 { 132 return ((val) << AXXX_CP_RB_CNTL_BLKSZ__SHIFT) & AXXX_CP_RB_CNTL_BLKSZ__MASK; 133 } 134 #define AXXX_CP_RB_CNTL_BUF_SWAP__MASK 0x00030000 135 #define AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT 16 136 static inline uint32_t AXXX_CP_RB_CNTL_BUF_SWAP(uint32_t val) 137 { 138 return ((val) << AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT) & AXXX_CP_RB_CNTL_BUF_SWAP__MASK; 139 } 140 #define AXXX_CP_RB_CNTL_POLL_EN 0x00100000 141 #define AXXX_CP_RB_CNTL_NO_UPDATE 0x08000000 142 #define AXXX_CP_RB_CNTL_RPTR_WR_EN 0x80000000 143 144 #define REG_AXXX_CP_RB_RPTR_ADDR 0x000001c3 145 #define AXXX_CP_RB_RPTR_ADDR_SWAP__MASK 0x00000003 146 #define AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT 0 147 static inline uint32_t AXXX_CP_RB_RPTR_ADDR_SWAP(uint32_t val) 148 { 149 return ((val) << AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT) & AXXX_CP_RB_RPTR_ADDR_SWAP__MASK; 150 } 151 #define AXXX_CP_RB_RPTR_ADDR_ADDR__MASK 0xfffffffc 152 #define AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT 2 153 static inline uint32_t AXXX_CP_RB_RPTR_ADDR_ADDR(uint32_t val) 154 { 155 return ((val >> 2) << AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT) & AXXX_CP_RB_RPTR_ADDR_ADDR__MASK; 156 } 157 158 #define REG_AXXX_CP_RB_RPTR 0x000001c4 159 160 #define REG_AXXX_CP_RB_WPTR 0x000001c5 161 162 #define REG_AXXX_CP_RB_WPTR_DELAY 0x000001c6 163 164 #define REG_AXXX_CP_RB_RPTR_WR 0x000001c7 165 166 #define REG_AXXX_CP_RB_WPTR_BASE 0x000001c8 167 168 #define REG_AXXX_CP_QUEUE_THRESHOLDS 0x000001d5 169 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK 0x0000000f 170 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT 0 171 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(uint32_t val) 172 { 173 return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK; 174 } 175 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK 0x00000f00 176 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT 8 177 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(uint32_t val) 178 { 179 return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK; 180 } 181 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK 0x000f0000 182 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT 16 183 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(uint32_t val) 184 { 185 return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK; 186 } 187 188 #define REG_AXXX_CP_MEQ_THRESHOLDS 0x000001d6 189 #define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK 0x001f0000 190 #define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT 16 191 static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_MEQ_END(uint32_t val) 192 { 193 return ((val) << AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK; 194 } 195 #define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK 0x1f000000 196 #define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT 24 197 static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_ROQ_END(uint32_t val) 198 { 199 return ((val) << AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK; 200 } 201 202 #define REG_AXXX_CP_CSQ_AVAIL 0x000001d7 203 #define AXXX_CP_CSQ_AVAIL_RING__MASK 0x0000007f 204 #define AXXX_CP_CSQ_AVAIL_RING__SHIFT 0 205 static inline uint32_t AXXX_CP_CSQ_AVAIL_RING(uint32_t val) 206 { 207 return ((val) << AXXX_CP_CSQ_AVAIL_RING__SHIFT) & AXXX_CP_CSQ_AVAIL_RING__MASK; 208 } 209 #define AXXX_CP_CSQ_AVAIL_IB1__MASK 0x00007f00 210 #define AXXX_CP_CSQ_AVAIL_IB1__SHIFT 8 211 static inline uint32_t AXXX_CP_CSQ_AVAIL_IB1(uint32_t val) 212 { 213 return ((val) << AXXX_CP_CSQ_AVAIL_IB1__SHIFT) & AXXX_CP_CSQ_AVAIL_IB1__MASK; 214 } 215 #define AXXX_CP_CSQ_AVAIL_IB2__MASK 0x007f0000 216 #define AXXX_CP_CSQ_AVAIL_IB2__SHIFT 16 217 static inline uint32_t AXXX_CP_CSQ_AVAIL_IB2(uint32_t val) 218 { 219 return ((val) << AXXX_CP_CSQ_AVAIL_IB2__SHIFT) & AXXX_CP_CSQ_AVAIL_IB2__MASK; 220 } 221 222 #define REG_AXXX_CP_STQ_AVAIL 0x000001d8 223 #define AXXX_CP_STQ_AVAIL_ST__MASK 0x0000007f 224 #define AXXX_CP_STQ_AVAIL_ST__SHIFT 0 225 static inline uint32_t AXXX_CP_STQ_AVAIL_ST(uint32_t val) 226 { 227 return ((val) << AXXX_CP_STQ_AVAIL_ST__SHIFT) & AXXX_CP_STQ_AVAIL_ST__MASK; 228 } 229 230 #define REG_AXXX_CP_MEQ_AVAIL 0x000001d9 231 #define AXXX_CP_MEQ_AVAIL_MEQ__MASK 0x0000001f 232 #define AXXX_CP_MEQ_AVAIL_MEQ__SHIFT 0 233 static inline uint32_t AXXX_CP_MEQ_AVAIL_MEQ(uint32_t val) 234 { 235 return ((val) << AXXX_CP_MEQ_AVAIL_MEQ__SHIFT) & AXXX_CP_MEQ_AVAIL_MEQ__MASK; 236 } 237 238 #define REG_AXXX_SCRATCH_UMSK 0x000001dc 239 #define AXXX_SCRATCH_UMSK_UMSK__MASK 0x000000ff 240 #define AXXX_SCRATCH_UMSK_UMSK__SHIFT 0 241 static inline uint32_t AXXX_SCRATCH_UMSK_UMSK(uint32_t val) 242 { 243 return ((val) << AXXX_SCRATCH_UMSK_UMSK__SHIFT) & AXXX_SCRATCH_UMSK_UMSK__MASK; 244 } 245 #define AXXX_SCRATCH_UMSK_SWAP__MASK 0x00030000 246 #define AXXX_SCRATCH_UMSK_SWAP__SHIFT 16 247 static inline uint32_t AXXX_SCRATCH_UMSK_SWAP(uint32_t val) 248 { 249 return ((val) << AXXX_SCRATCH_UMSK_SWAP__SHIFT) & AXXX_SCRATCH_UMSK_SWAP__MASK; 250 } 251 252 #define REG_AXXX_SCRATCH_ADDR 0x000001dd 253 254 #define REG_AXXX_CP_ME_RDADDR 0x000001ea 255 256 #define REG_AXXX_CP_STATE_DEBUG_INDEX 0x000001ec 257 258 #define REG_AXXX_CP_STATE_DEBUG_DATA 0x000001ed 259 260 #define REG_AXXX_CP_INT_CNTL 0x000001f2 261 262 #define REG_AXXX_CP_INT_STATUS 0x000001f3 263 264 #define REG_AXXX_CP_INT_ACK 0x000001f4 265 266 #define REG_AXXX_CP_ME_CNTL 0x000001f6 267 268 #define REG_AXXX_CP_ME_STATUS 0x000001f7 269 270 #define REG_AXXX_CP_ME_RAM_WADDR 0x000001f8 271 272 #define REG_AXXX_CP_ME_RAM_RADDR 0x000001f9 273 274 #define REG_AXXX_CP_ME_RAM_DATA 0x000001fa 275 276 #define REG_AXXX_CP_DEBUG 0x000001fc 277 #define AXXX_CP_DEBUG_PREDICATE_DISABLE 0x00800000 278 #define AXXX_CP_DEBUG_PROG_END_PTR_ENABLE 0x01000000 279 #define AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE 0x02000000 280 #define AXXX_CP_DEBUG_PREFETCH_PASS_NOPS 0x04000000 281 #define AXXX_CP_DEBUG_DYNAMIC_CLK_DISABLE 0x08000000 282 #define AXXX_CP_DEBUG_PREFETCH_MATCH_DISABLE 0x10000000 283 #define AXXX_CP_DEBUG_SIMPLE_ME_FLOW_CONTROL 0x40000000 284 #define AXXX_CP_DEBUG_MIU_WRITE_PACK_DISABLE 0x80000000 285 286 #define REG_AXXX_CP_CSQ_RB_STAT 0x000001fd 287 #define AXXX_CP_CSQ_RB_STAT_RPTR__MASK 0x0000007f 288 #define AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT 0 289 static inline uint32_t AXXX_CP_CSQ_RB_STAT_RPTR(uint32_t val) 290 { 291 return ((val) << AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_RPTR__MASK; 292 } 293 #define AXXX_CP_CSQ_RB_STAT_WPTR__MASK 0x007f0000 294 #define AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT 16 295 static inline uint32_t AXXX_CP_CSQ_RB_STAT_WPTR(uint32_t val) 296 { 297 return ((val) << AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_WPTR__MASK; 298 } 299 300 #define REG_AXXX_CP_CSQ_IB1_STAT 0x000001fe 301 #define AXXX_CP_CSQ_IB1_STAT_RPTR__MASK 0x0000007f 302 #define AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT 0 303 static inline uint32_t AXXX_CP_CSQ_IB1_STAT_RPTR(uint32_t val) 304 { 305 return ((val) << AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_RPTR__MASK; 306 } 307 #define AXXX_CP_CSQ_IB1_STAT_WPTR__MASK 0x007f0000 308 #define AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT 16 309 static inline uint32_t AXXX_CP_CSQ_IB1_STAT_WPTR(uint32_t val) 310 { 311 return ((val) << AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_WPTR__MASK; 312 } 313 314 #define REG_AXXX_CP_CSQ_IB2_STAT 0x000001ff 315 #define AXXX_CP_CSQ_IB2_STAT_RPTR__MASK 0x0000007f 316 #define AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT 0 317 static inline uint32_t AXXX_CP_CSQ_IB2_STAT_RPTR(uint32_t val) 318 { 319 return ((val) << AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_RPTR__MASK; 320 } 321 #define AXXX_CP_CSQ_IB2_STAT_WPTR__MASK 0x007f0000 322 #define AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT 16 323 static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val) 324 { 325 return ((val) << AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_WPTR__MASK; 326 } 327 328 #define REG_AXXX_CP_NON_PREFETCH_CNTRS 0x00000440 329 330 #define REG_AXXX_CP_STQ_ST_STAT 0x00000443 331 332 #define REG_AXXX_CP_ST_BASE 0x0000044d 333 334 #define REG_AXXX_CP_ST_BUFSZ 0x0000044e 335 336 #define REG_AXXX_CP_MEQ_STAT 0x0000044f 337 338 #define REG_AXXX_CP_MIU_TAG_STAT 0x00000452 339 340 #define REG_AXXX_CP_BIN_MASK_LO 0x00000454 341 342 #define REG_AXXX_CP_BIN_MASK_HI 0x00000455 343 344 #define REG_AXXX_CP_BIN_SELECT_LO 0x00000456 345 346 #define REG_AXXX_CP_BIN_SELECT_HI 0x00000457 347 348 #define REG_AXXX_CP_IB1_BASE 0x00000458 349 350 #define REG_AXXX_CP_IB1_BUFSZ 0x00000459 351 352 #define REG_AXXX_CP_IB2_BASE 0x0000045a 353 354 #define REG_AXXX_CP_IB2_BUFSZ 0x0000045b 355 356 #define REG_AXXX_CP_STAT 0x0000047f 357 358 #define REG_AXXX_CP_SCRATCH_REG0 0x00000578 359 360 #define REG_AXXX_CP_SCRATCH_REG1 0x00000579 361 362 #define REG_AXXX_CP_SCRATCH_REG2 0x0000057a 363 364 #define REG_AXXX_CP_SCRATCH_REG3 0x0000057b 365 366 #define REG_AXXX_CP_SCRATCH_REG4 0x0000057c 367 368 #define REG_AXXX_CP_SCRATCH_REG5 0x0000057d 369 370 #define REG_AXXX_CP_SCRATCH_REG6 0x0000057e 371 372 #define REG_AXXX_CP_SCRATCH_REG7 0x0000057f 373 374 #define REG_AXXX_CP_ME_VS_EVENT_SRC 0x00000600 375 376 #define REG_AXXX_CP_ME_VS_EVENT_ADDR 0x00000601 377 378 #define REG_AXXX_CP_ME_VS_EVENT_DATA 0x00000602 379 380 #define REG_AXXX_CP_ME_VS_EVENT_ADDR_SWM 0x00000603 381 382 #define REG_AXXX_CP_ME_VS_EVENT_DATA_SWM 0x00000604 383 384 #define REG_AXXX_CP_ME_PS_EVENT_SRC 0x00000605 385 386 #define REG_AXXX_CP_ME_PS_EVENT_ADDR 0x00000606 387 388 #define REG_AXXX_CP_ME_PS_EVENT_DATA 0x00000607 389 390 #define REG_AXXX_CP_ME_PS_EVENT_ADDR_SWM 0x00000608 391 392 #define REG_AXXX_CP_ME_PS_EVENT_DATA_SWM 0x00000609 393 394 #define REG_AXXX_CP_ME_CF_EVENT_SRC 0x0000060a 395 396 #define REG_AXXX_CP_ME_CF_EVENT_ADDR 0x0000060b 397 398 #define REG_AXXX_CP_ME_CF_EVENT_DATA 0x0000060c 399 400 #define REG_AXXX_CP_ME_NRT_ADDR 0x0000060d 401 402 #define REG_AXXX_CP_ME_NRT_DATA 0x0000060e 403 404 #define REG_AXXX_CP_ME_VS_FETCH_DONE_SRC 0x00000612 405 406 #define REG_AXXX_CP_ME_VS_FETCH_DONE_ADDR 0x00000613 407 408 #define REG_AXXX_CP_ME_VS_FETCH_DONE_DATA 0x00000614 409 410 411 #endif /* ADRENO_COMMON_XML */ 412