1 #ifndef ADRENO_COMMON_XML 2 #define ADRENO_COMMON_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2013-11-30 14:47:15) 12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2014-06-02 15:21:30) 14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 9859 bytes, from 2014-06-02 15:21:30) 15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14960 bytes, from 2014-07-27 17:22:13) 16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 58020 bytes, from 2014-08-01 12:22:48) 17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 41068 bytes, from 2014-08-01 12:22:48) 18 19 Copyright (C) 2013-2014 by the following authors: 20 - Rob Clark <robdclark@gmail.com> (robclark) 21 22 Permission is hereby granted, free of charge, to any person obtaining 23 a copy of this software and associated documentation files (the 24 "Software"), to deal in the Software without restriction, including 25 without limitation the rights to use, copy, modify, merge, publish, 26 distribute, sublicense, and/or sell copies of the Software, and to 27 permit persons to whom the Software is furnished to do so, subject to 28 the following conditions: 29 30 The above copyright notice and this permission notice (including the 31 next paragraph) shall be included in all copies or substantial 32 portions of the Software. 33 34 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 35 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 36 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 37 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 38 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 39 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 40 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43 44 enum adreno_pa_su_sc_draw { 45 PC_DRAW_POINTS = 0, 46 PC_DRAW_LINES = 1, 47 PC_DRAW_TRIANGLES = 2, 48 }; 49 50 enum adreno_compare_func { 51 FUNC_NEVER = 0, 52 FUNC_LESS = 1, 53 FUNC_EQUAL = 2, 54 FUNC_LEQUAL = 3, 55 FUNC_GREATER = 4, 56 FUNC_NOTEQUAL = 5, 57 FUNC_GEQUAL = 6, 58 FUNC_ALWAYS = 7, 59 }; 60 61 enum adreno_stencil_op { 62 STENCIL_KEEP = 0, 63 STENCIL_ZERO = 1, 64 STENCIL_REPLACE = 2, 65 STENCIL_INCR_CLAMP = 3, 66 STENCIL_DECR_CLAMP = 4, 67 STENCIL_INVERT = 5, 68 STENCIL_INCR_WRAP = 6, 69 STENCIL_DECR_WRAP = 7, 70 }; 71 72 enum adreno_rb_blend_factor { 73 FACTOR_ZERO = 0, 74 FACTOR_ONE = 1, 75 FACTOR_SRC_COLOR = 4, 76 FACTOR_ONE_MINUS_SRC_COLOR = 5, 77 FACTOR_SRC_ALPHA = 6, 78 FACTOR_ONE_MINUS_SRC_ALPHA = 7, 79 FACTOR_DST_COLOR = 8, 80 FACTOR_ONE_MINUS_DST_COLOR = 9, 81 FACTOR_DST_ALPHA = 10, 82 FACTOR_ONE_MINUS_DST_ALPHA = 11, 83 FACTOR_CONSTANT_COLOR = 12, 84 FACTOR_ONE_MINUS_CONSTANT_COLOR = 13, 85 FACTOR_CONSTANT_ALPHA = 14, 86 FACTOR_ONE_MINUS_CONSTANT_ALPHA = 15, 87 FACTOR_SRC_ALPHA_SATURATE = 16, 88 }; 89 90 enum adreno_rb_surface_endian { 91 ENDIAN_NONE = 0, 92 ENDIAN_8IN16 = 1, 93 ENDIAN_8IN32 = 2, 94 ENDIAN_16IN32 = 3, 95 ENDIAN_8IN64 = 4, 96 ENDIAN_8IN128 = 5, 97 }; 98 99 enum adreno_rb_dither_mode { 100 DITHER_DISABLE = 0, 101 DITHER_ALWAYS = 1, 102 DITHER_IF_ALPHA_OFF = 2, 103 }; 104 105 enum adreno_rb_depth_format { 106 DEPTHX_16 = 0, 107 DEPTHX_24_8 = 1, 108 }; 109 110 enum adreno_rb_copy_control_mode { 111 RB_COPY_RESOLVE = 1, 112 RB_COPY_CLEAR = 2, 113 RB_COPY_DEPTH_STENCIL = 5, 114 }; 115 116 enum a3xx_render_mode { 117 RB_RENDERING_PASS = 0, 118 RB_TILING_PASS = 1, 119 RB_RESOLVE_PASS = 2, 120 RB_COMPUTE_PASS = 3, 121 }; 122 123 enum a3xx_msaa_samples { 124 MSAA_ONE = 0, 125 MSAA_TWO = 1, 126 MSAA_FOUR = 2, 127 }; 128 129 enum a3xx_threadmode { 130 MULTI = 0, 131 SINGLE = 1, 132 }; 133 134 enum a3xx_instrbuffermode { 135 BUFFER = 1, 136 }; 137 138 enum a3xx_threadsize { 139 TWO_QUADS = 0, 140 FOUR_QUADS = 1, 141 }; 142 143 #define REG_AXXX_CP_RB_BASE 0x000001c0 144 145 #define REG_AXXX_CP_RB_CNTL 0x000001c1 146 #define AXXX_CP_RB_CNTL_BUFSZ__MASK 0x0000003f 147 #define AXXX_CP_RB_CNTL_BUFSZ__SHIFT 0 148 static inline uint32_t AXXX_CP_RB_CNTL_BUFSZ(uint32_t val) 149 { 150 return ((val) << AXXX_CP_RB_CNTL_BUFSZ__SHIFT) & AXXX_CP_RB_CNTL_BUFSZ__MASK; 151 } 152 #define AXXX_CP_RB_CNTL_BLKSZ__MASK 0x00003f00 153 #define AXXX_CP_RB_CNTL_BLKSZ__SHIFT 8 154 static inline uint32_t AXXX_CP_RB_CNTL_BLKSZ(uint32_t val) 155 { 156 return ((val) << AXXX_CP_RB_CNTL_BLKSZ__SHIFT) & AXXX_CP_RB_CNTL_BLKSZ__MASK; 157 } 158 #define AXXX_CP_RB_CNTL_BUF_SWAP__MASK 0x00030000 159 #define AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT 16 160 static inline uint32_t AXXX_CP_RB_CNTL_BUF_SWAP(uint32_t val) 161 { 162 return ((val) << AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT) & AXXX_CP_RB_CNTL_BUF_SWAP__MASK; 163 } 164 #define AXXX_CP_RB_CNTL_POLL_EN 0x00100000 165 #define AXXX_CP_RB_CNTL_NO_UPDATE 0x08000000 166 #define AXXX_CP_RB_CNTL_RPTR_WR_EN 0x80000000 167 168 #define REG_AXXX_CP_RB_RPTR_ADDR 0x000001c3 169 #define AXXX_CP_RB_RPTR_ADDR_SWAP__MASK 0x00000003 170 #define AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT 0 171 static inline uint32_t AXXX_CP_RB_RPTR_ADDR_SWAP(uint32_t val) 172 { 173 return ((val) << AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT) & AXXX_CP_RB_RPTR_ADDR_SWAP__MASK; 174 } 175 #define AXXX_CP_RB_RPTR_ADDR_ADDR__MASK 0xfffffffc 176 #define AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT 2 177 static inline uint32_t AXXX_CP_RB_RPTR_ADDR_ADDR(uint32_t val) 178 { 179 return ((val >> 2) << AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT) & AXXX_CP_RB_RPTR_ADDR_ADDR__MASK; 180 } 181 182 #define REG_AXXX_CP_RB_RPTR 0x000001c4 183 184 #define REG_AXXX_CP_RB_WPTR 0x000001c5 185 186 #define REG_AXXX_CP_RB_WPTR_DELAY 0x000001c6 187 188 #define REG_AXXX_CP_RB_RPTR_WR 0x000001c7 189 190 #define REG_AXXX_CP_RB_WPTR_BASE 0x000001c8 191 192 #define REG_AXXX_CP_QUEUE_THRESHOLDS 0x000001d5 193 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK 0x0000000f 194 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT 0 195 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(uint32_t val) 196 { 197 return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK; 198 } 199 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK 0x00000f00 200 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT 8 201 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(uint32_t val) 202 { 203 return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK; 204 } 205 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK 0x000f0000 206 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT 16 207 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(uint32_t val) 208 { 209 return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK; 210 } 211 212 #define REG_AXXX_CP_MEQ_THRESHOLDS 0x000001d6 213 #define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK 0x001f0000 214 #define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT 16 215 static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_MEQ_END(uint32_t val) 216 { 217 return ((val) << AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK; 218 } 219 #define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK 0x1f000000 220 #define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT 24 221 static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_ROQ_END(uint32_t val) 222 { 223 return ((val) << AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK; 224 } 225 226 #define REG_AXXX_CP_CSQ_AVAIL 0x000001d7 227 #define AXXX_CP_CSQ_AVAIL_RING__MASK 0x0000007f 228 #define AXXX_CP_CSQ_AVAIL_RING__SHIFT 0 229 static inline uint32_t AXXX_CP_CSQ_AVAIL_RING(uint32_t val) 230 { 231 return ((val) << AXXX_CP_CSQ_AVAIL_RING__SHIFT) & AXXX_CP_CSQ_AVAIL_RING__MASK; 232 } 233 #define AXXX_CP_CSQ_AVAIL_IB1__MASK 0x00007f00 234 #define AXXX_CP_CSQ_AVAIL_IB1__SHIFT 8 235 static inline uint32_t AXXX_CP_CSQ_AVAIL_IB1(uint32_t val) 236 { 237 return ((val) << AXXX_CP_CSQ_AVAIL_IB1__SHIFT) & AXXX_CP_CSQ_AVAIL_IB1__MASK; 238 } 239 #define AXXX_CP_CSQ_AVAIL_IB2__MASK 0x007f0000 240 #define AXXX_CP_CSQ_AVAIL_IB2__SHIFT 16 241 static inline uint32_t AXXX_CP_CSQ_AVAIL_IB2(uint32_t val) 242 { 243 return ((val) << AXXX_CP_CSQ_AVAIL_IB2__SHIFT) & AXXX_CP_CSQ_AVAIL_IB2__MASK; 244 } 245 246 #define REG_AXXX_CP_STQ_AVAIL 0x000001d8 247 #define AXXX_CP_STQ_AVAIL_ST__MASK 0x0000007f 248 #define AXXX_CP_STQ_AVAIL_ST__SHIFT 0 249 static inline uint32_t AXXX_CP_STQ_AVAIL_ST(uint32_t val) 250 { 251 return ((val) << AXXX_CP_STQ_AVAIL_ST__SHIFT) & AXXX_CP_STQ_AVAIL_ST__MASK; 252 } 253 254 #define REG_AXXX_CP_MEQ_AVAIL 0x000001d9 255 #define AXXX_CP_MEQ_AVAIL_MEQ__MASK 0x0000001f 256 #define AXXX_CP_MEQ_AVAIL_MEQ__SHIFT 0 257 static inline uint32_t AXXX_CP_MEQ_AVAIL_MEQ(uint32_t val) 258 { 259 return ((val) << AXXX_CP_MEQ_AVAIL_MEQ__SHIFT) & AXXX_CP_MEQ_AVAIL_MEQ__MASK; 260 } 261 262 #define REG_AXXX_SCRATCH_UMSK 0x000001dc 263 #define AXXX_SCRATCH_UMSK_UMSK__MASK 0x000000ff 264 #define AXXX_SCRATCH_UMSK_UMSK__SHIFT 0 265 static inline uint32_t AXXX_SCRATCH_UMSK_UMSK(uint32_t val) 266 { 267 return ((val) << AXXX_SCRATCH_UMSK_UMSK__SHIFT) & AXXX_SCRATCH_UMSK_UMSK__MASK; 268 } 269 #define AXXX_SCRATCH_UMSK_SWAP__MASK 0x00030000 270 #define AXXX_SCRATCH_UMSK_SWAP__SHIFT 16 271 static inline uint32_t AXXX_SCRATCH_UMSK_SWAP(uint32_t val) 272 { 273 return ((val) << AXXX_SCRATCH_UMSK_SWAP__SHIFT) & AXXX_SCRATCH_UMSK_SWAP__MASK; 274 } 275 276 #define REG_AXXX_SCRATCH_ADDR 0x000001dd 277 278 #define REG_AXXX_CP_ME_RDADDR 0x000001ea 279 280 #define REG_AXXX_CP_STATE_DEBUG_INDEX 0x000001ec 281 282 #define REG_AXXX_CP_STATE_DEBUG_DATA 0x000001ed 283 284 #define REG_AXXX_CP_INT_CNTL 0x000001f2 285 286 #define REG_AXXX_CP_INT_STATUS 0x000001f3 287 288 #define REG_AXXX_CP_INT_ACK 0x000001f4 289 290 #define REG_AXXX_CP_ME_CNTL 0x000001f6 291 #define AXXX_CP_ME_CNTL_BUSY 0x20000000 292 #define AXXX_CP_ME_CNTL_HALT 0x10000000 293 294 #define REG_AXXX_CP_ME_STATUS 0x000001f7 295 296 #define REG_AXXX_CP_ME_RAM_WADDR 0x000001f8 297 298 #define REG_AXXX_CP_ME_RAM_RADDR 0x000001f9 299 300 #define REG_AXXX_CP_ME_RAM_DATA 0x000001fa 301 302 #define REG_AXXX_CP_DEBUG 0x000001fc 303 #define AXXX_CP_DEBUG_PREDICATE_DISABLE 0x00800000 304 #define AXXX_CP_DEBUG_PROG_END_PTR_ENABLE 0x01000000 305 #define AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE 0x02000000 306 #define AXXX_CP_DEBUG_PREFETCH_PASS_NOPS 0x04000000 307 #define AXXX_CP_DEBUG_DYNAMIC_CLK_DISABLE 0x08000000 308 #define AXXX_CP_DEBUG_PREFETCH_MATCH_DISABLE 0x10000000 309 #define AXXX_CP_DEBUG_SIMPLE_ME_FLOW_CONTROL 0x40000000 310 #define AXXX_CP_DEBUG_MIU_WRITE_PACK_DISABLE 0x80000000 311 312 #define REG_AXXX_CP_CSQ_RB_STAT 0x000001fd 313 #define AXXX_CP_CSQ_RB_STAT_RPTR__MASK 0x0000007f 314 #define AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT 0 315 static inline uint32_t AXXX_CP_CSQ_RB_STAT_RPTR(uint32_t val) 316 { 317 return ((val) << AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_RPTR__MASK; 318 } 319 #define AXXX_CP_CSQ_RB_STAT_WPTR__MASK 0x007f0000 320 #define AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT 16 321 static inline uint32_t AXXX_CP_CSQ_RB_STAT_WPTR(uint32_t val) 322 { 323 return ((val) << AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_WPTR__MASK; 324 } 325 326 #define REG_AXXX_CP_CSQ_IB1_STAT 0x000001fe 327 #define AXXX_CP_CSQ_IB1_STAT_RPTR__MASK 0x0000007f 328 #define AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT 0 329 static inline uint32_t AXXX_CP_CSQ_IB1_STAT_RPTR(uint32_t val) 330 { 331 return ((val) << AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_RPTR__MASK; 332 } 333 #define AXXX_CP_CSQ_IB1_STAT_WPTR__MASK 0x007f0000 334 #define AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT 16 335 static inline uint32_t AXXX_CP_CSQ_IB1_STAT_WPTR(uint32_t val) 336 { 337 return ((val) << AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_WPTR__MASK; 338 } 339 340 #define REG_AXXX_CP_CSQ_IB2_STAT 0x000001ff 341 #define AXXX_CP_CSQ_IB2_STAT_RPTR__MASK 0x0000007f 342 #define AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT 0 343 static inline uint32_t AXXX_CP_CSQ_IB2_STAT_RPTR(uint32_t val) 344 { 345 return ((val) << AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_RPTR__MASK; 346 } 347 #define AXXX_CP_CSQ_IB2_STAT_WPTR__MASK 0x007f0000 348 #define AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT 16 349 static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val) 350 { 351 return ((val) << AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_WPTR__MASK; 352 } 353 354 #define REG_AXXX_CP_NON_PREFETCH_CNTRS 0x00000440 355 356 #define REG_AXXX_CP_STQ_ST_STAT 0x00000443 357 358 #define REG_AXXX_CP_ST_BASE 0x0000044d 359 360 #define REG_AXXX_CP_ST_BUFSZ 0x0000044e 361 362 #define REG_AXXX_CP_MEQ_STAT 0x0000044f 363 364 #define REG_AXXX_CP_MIU_TAG_STAT 0x00000452 365 366 #define REG_AXXX_CP_BIN_MASK_LO 0x00000454 367 368 #define REG_AXXX_CP_BIN_MASK_HI 0x00000455 369 370 #define REG_AXXX_CP_BIN_SELECT_LO 0x00000456 371 372 #define REG_AXXX_CP_BIN_SELECT_HI 0x00000457 373 374 #define REG_AXXX_CP_IB1_BASE 0x00000458 375 376 #define REG_AXXX_CP_IB1_BUFSZ 0x00000459 377 378 #define REG_AXXX_CP_IB2_BASE 0x0000045a 379 380 #define REG_AXXX_CP_IB2_BUFSZ 0x0000045b 381 382 #define REG_AXXX_CP_STAT 0x0000047f 383 384 #define REG_AXXX_CP_SCRATCH_REG0 0x00000578 385 386 #define REG_AXXX_CP_SCRATCH_REG1 0x00000579 387 388 #define REG_AXXX_CP_SCRATCH_REG2 0x0000057a 389 390 #define REG_AXXX_CP_SCRATCH_REG3 0x0000057b 391 392 #define REG_AXXX_CP_SCRATCH_REG4 0x0000057c 393 394 #define REG_AXXX_CP_SCRATCH_REG5 0x0000057d 395 396 #define REG_AXXX_CP_SCRATCH_REG6 0x0000057e 397 398 #define REG_AXXX_CP_SCRATCH_REG7 0x0000057f 399 400 #define REG_AXXX_CP_ME_VS_EVENT_SRC 0x00000600 401 402 #define REG_AXXX_CP_ME_VS_EVENT_ADDR 0x00000601 403 404 #define REG_AXXX_CP_ME_VS_EVENT_DATA 0x00000602 405 406 #define REG_AXXX_CP_ME_VS_EVENT_ADDR_SWM 0x00000603 407 408 #define REG_AXXX_CP_ME_VS_EVENT_DATA_SWM 0x00000604 409 410 #define REG_AXXX_CP_ME_PS_EVENT_SRC 0x00000605 411 412 #define REG_AXXX_CP_ME_PS_EVENT_ADDR 0x00000606 413 414 #define REG_AXXX_CP_ME_PS_EVENT_DATA 0x00000607 415 416 #define REG_AXXX_CP_ME_PS_EVENT_ADDR_SWM 0x00000608 417 418 #define REG_AXXX_CP_ME_PS_EVENT_DATA_SWM 0x00000609 419 420 #define REG_AXXX_CP_ME_CF_EVENT_SRC 0x0000060a 421 422 #define REG_AXXX_CP_ME_CF_EVENT_ADDR 0x0000060b 423 424 #define REG_AXXX_CP_ME_CF_EVENT_DATA 0x0000060c 425 426 #define REG_AXXX_CP_ME_NRT_ADDR 0x0000060d 427 428 #define REG_AXXX_CP_ME_NRT_DATA 0x0000060e 429 430 #define REG_AXXX_CP_ME_VS_FETCH_DONE_SRC 0x00000612 431 432 #define REG_AXXX_CP_ME_VS_FETCH_DONE_ADDR 0x00000613 433 434 #define REG_AXXX_CP_ME_VS_FETCH_DONE_DATA 0x00000614 435 436 437 #endif /* ADRENO_COMMON_XML */ 438