1 #ifndef ADRENO_COMMON_XML 2 #define ADRENO_COMMON_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-01-30 18:25:22) 12 - /home/robclark/tmp/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2020-12-31 19:26:32) 13 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-06-21 15:24:24) 14 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14609 bytes, from 2021-11-24 23:05:10) 15 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 69086 bytes, from 2022-03-03 16:41:33) 16 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84231 bytes, from 2021-11-24 23:05:10) 17 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a4xx.xml ( 113358 bytes, from 2022-01-31 23:06:21) 18 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a5xx.xml ( 149512 bytes, from 2022-01-31 23:06:21) 19 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a6xx.xml ( 184954 bytes, from 2022-03-03 16:41:33) 20 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-07-22 15:21:56) 21 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-01-30 18:25:22) 22 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-07-22 15:21:56) 23 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-07-22 15:21:56) 24 25 Copyright (C) 2013-2021 by the following authors: 26 - Rob Clark <robdclark@gmail.com> (robclark) 27 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) 28 29 Permission is hereby granted, free of charge, to any person obtaining 30 a copy of this software and associated documentation files (the 31 "Software"), to deal in the Software without restriction, including 32 without limitation the rights to use, copy, modify, merge, publish, 33 distribute, sublicense, and/or sell copies of the Software, and to 34 permit persons to whom the Software is furnished to do so, subject to 35 the following conditions: 36 37 The above copyright notice and this permission notice (including the 38 next paragraph) shall be included in all copies or substantial 39 portions of the Software. 40 41 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 42 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 43 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 44 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 45 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 46 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 47 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 48 */ 49 50 51 enum chip { 52 A2XX = 0, 53 A3XX = 0, 54 A4XX = 0, 55 A5XX = 0, 56 A6XX = 0, 57 }; 58 59 enum adreno_pa_su_sc_draw { 60 PC_DRAW_POINTS = 0, 61 PC_DRAW_LINES = 1, 62 PC_DRAW_TRIANGLES = 2, 63 }; 64 65 enum adreno_compare_func { 66 FUNC_NEVER = 0, 67 FUNC_LESS = 1, 68 FUNC_EQUAL = 2, 69 FUNC_LEQUAL = 3, 70 FUNC_GREATER = 4, 71 FUNC_NOTEQUAL = 5, 72 FUNC_GEQUAL = 6, 73 FUNC_ALWAYS = 7, 74 }; 75 76 enum adreno_stencil_op { 77 STENCIL_KEEP = 0, 78 STENCIL_ZERO = 1, 79 STENCIL_REPLACE = 2, 80 STENCIL_INCR_CLAMP = 3, 81 STENCIL_DECR_CLAMP = 4, 82 STENCIL_INVERT = 5, 83 STENCIL_INCR_WRAP = 6, 84 STENCIL_DECR_WRAP = 7, 85 }; 86 87 enum adreno_rb_blend_factor { 88 FACTOR_ZERO = 0, 89 FACTOR_ONE = 1, 90 FACTOR_SRC_COLOR = 4, 91 FACTOR_ONE_MINUS_SRC_COLOR = 5, 92 FACTOR_SRC_ALPHA = 6, 93 FACTOR_ONE_MINUS_SRC_ALPHA = 7, 94 FACTOR_DST_COLOR = 8, 95 FACTOR_ONE_MINUS_DST_COLOR = 9, 96 FACTOR_DST_ALPHA = 10, 97 FACTOR_ONE_MINUS_DST_ALPHA = 11, 98 FACTOR_CONSTANT_COLOR = 12, 99 FACTOR_ONE_MINUS_CONSTANT_COLOR = 13, 100 FACTOR_CONSTANT_ALPHA = 14, 101 FACTOR_ONE_MINUS_CONSTANT_ALPHA = 15, 102 FACTOR_SRC_ALPHA_SATURATE = 16, 103 FACTOR_SRC1_COLOR = 20, 104 FACTOR_ONE_MINUS_SRC1_COLOR = 21, 105 FACTOR_SRC1_ALPHA = 22, 106 FACTOR_ONE_MINUS_SRC1_ALPHA = 23, 107 }; 108 109 enum adreno_rb_surface_endian { 110 ENDIAN_NONE = 0, 111 ENDIAN_8IN16 = 1, 112 ENDIAN_8IN32 = 2, 113 ENDIAN_16IN32 = 3, 114 ENDIAN_8IN64 = 4, 115 ENDIAN_8IN128 = 5, 116 }; 117 118 enum adreno_rb_dither_mode { 119 DITHER_DISABLE = 0, 120 DITHER_ALWAYS = 1, 121 DITHER_IF_ALPHA_OFF = 2, 122 }; 123 124 enum adreno_rb_depth_format { 125 DEPTHX_16 = 0, 126 DEPTHX_24_8 = 1, 127 DEPTHX_32 = 2, 128 }; 129 130 enum adreno_rb_copy_control_mode { 131 RB_COPY_RESOLVE = 1, 132 RB_COPY_CLEAR = 2, 133 RB_COPY_DEPTH_STENCIL = 5, 134 }; 135 136 enum a3xx_rop_code { 137 ROP_CLEAR = 0, 138 ROP_NOR = 1, 139 ROP_AND_INVERTED = 2, 140 ROP_COPY_INVERTED = 3, 141 ROP_AND_REVERSE = 4, 142 ROP_INVERT = 5, 143 ROP_NAND = 7, 144 ROP_AND = 8, 145 ROP_EQUIV = 9, 146 ROP_NOOP = 10, 147 ROP_OR_INVERTED = 11, 148 ROP_OR_REVERSE = 13, 149 ROP_OR = 14, 150 ROP_SET = 15, 151 }; 152 153 enum a3xx_render_mode { 154 RB_RENDERING_PASS = 0, 155 RB_TILING_PASS = 1, 156 RB_RESOLVE_PASS = 2, 157 RB_COMPUTE_PASS = 3, 158 }; 159 160 enum a3xx_msaa_samples { 161 MSAA_ONE = 0, 162 MSAA_TWO = 1, 163 MSAA_FOUR = 2, 164 MSAA_EIGHT = 3, 165 }; 166 167 enum a3xx_threadmode { 168 MULTI = 0, 169 SINGLE = 1, 170 }; 171 172 enum a3xx_instrbuffermode { 173 CACHE = 0, 174 BUFFER = 1, 175 }; 176 177 enum a3xx_threadsize { 178 TWO_QUADS = 0, 179 FOUR_QUADS = 1, 180 }; 181 182 enum a3xx_color_swap { 183 WZYX = 0, 184 WXYZ = 1, 185 ZYXW = 2, 186 XYZW = 3, 187 }; 188 189 enum a3xx_rb_blend_opcode { 190 BLEND_DST_PLUS_SRC = 0, 191 BLEND_SRC_MINUS_DST = 1, 192 BLEND_DST_MINUS_SRC = 2, 193 BLEND_MIN_DST_SRC = 3, 194 BLEND_MAX_DST_SRC = 4, 195 }; 196 197 enum a4xx_tess_spacing { 198 EQUAL_SPACING = 0, 199 ODD_SPACING = 2, 200 EVEN_SPACING = 3, 201 }; 202 203 enum a5xx_address_mode { 204 ADDR_32B = 0, 205 ADDR_64B = 1, 206 }; 207 208 enum a5xx_line_mode { 209 BRESENHAM = 0, 210 RECTANGULAR = 1, 211 }; 212 213 #define REG_AXXX_CP_RB_BASE 0x000001c0 214 215 #define REG_AXXX_CP_RB_CNTL 0x000001c1 216 #define AXXX_CP_RB_CNTL_BUFSZ__MASK 0x0000003f 217 #define AXXX_CP_RB_CNTL_BUFSZ__SHIFT 0 218 static inline uint32_t AXXX_CP_RB_CNTL_BUFSZ(uint32_t val) 219 { 220 return ((val) << AXXX_CP_RB_CNTL_BUFSZ__SHIFT) & AXXX_CP_RB_CNTL_BUFSZ__MASK; 221 } 222 #define AXXX_CP_RB_CNTL_BLKSZ__MASK 0x00003f00 223 #define AXXX_CP_RB_CNTL_BLKSZ__SHIFT 8 224 static inline uint32_t AXXX_CP_RB_CNTL_BLKSZ(uint32_t val) 225 { 226 return ((val) << AXXX_CP_RB_CNTL_BLKSZ__SHIFT) & AXXX_CP_RB_CNTL_BLKSZ__MASK; 227 } 228 #define AXXX_CP_RB_CNTL_BUF_SWAP__MASK 0x00030000 229 #define AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT 16 230 static inline uint32_t AXXX_CP_RB_CNTL_BUF_SWAP(uint32_t val) 231 { 232 return ((val) << AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT) & AXXX_CP_RB_CNTL_BUF_SWAP__MASK; 233 } 234 #define AXXX_CP_RB_CNTL_POLL_EN 0x00100000 235 #define AXXX_CP_RB_CNTL_NO_UPDATE 0x08000000 236 #define AXXX_CP_RB_CNTL_RPTR_WR_EN 0x80000000 237 238 #define REG_AXXX_CP_RB_RPTR_ADDR 0x000001c3 239 #define AXXX_CP_RB_RPTR_ADDR_SWAP__MASK 0x00000003 240 #define AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT 0 241 static inline uint32_t AXXX_CP_RB_RPTR_ADDR_SWAP(uint32_t val) 242 { 243 return ((val) << AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT) & AXXX_CP_RB_RPTR_ADDR_SWAP__MASK; 244 } 245 #define AXXX_CP_RB_RPTR_ADDR_ADDR__MASK 0xfffffffc 246 #define AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT 2 247 static inline uint32_t AXXX_CP_RB_RPTR_ADDR_ADDR(uint32_t val) 248 { 249 return ((val >> 2) << AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT) & AXXX_CP_RB_RPTR_ADDR_ADDR__MASK; 250 } 251 252 #define REG_AXXX_CP_RB_RPTR 0x000001c4 253 254 #define REG_AXXX_CP_RB_WPTR 0x000001c5 255 256 #define REG_AXXX_CP_RB_WPTR_DELAY 0x000001c6 257 258 #define REG_AXXX_CP_RB_RPTR_WR 0x000001c7 259 260 #define REG_AXXX_CP_RB_WPTR_BASE 0x000001c8 261 262 #define REG_AXXX_CP_QUEUE_THRESHOLDS 0x000001d5 263 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK 0x0000000f 264 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT 0 265 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(uint32_t val) 266 { 267 return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK; 268 } 269 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK 0x00000f00 270 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT 8 271 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(uint32_t val) 272 { 273 return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK; 274 } 275 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK 0x000f0000 276 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT 16 277 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(uint32_t val) 278 { 279 return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK; 280 } 281 282 #define REG_AXXX_CP_MEQ_THRESHOLDS 0x000001d6 283 #define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK 0x001f0000 284 #define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT 16 285 static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_MEQ_END(uint32_t val) 286 { 287 return ((val) << AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK; 288 } 289 #define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK 0x1f000000 290 #define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT 24 291 static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_ROQ_END(uint32_t val) 292 { 293 return ((val) << AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK; 294 } 295 296 #define REG_AXXX_CP_CSQ_AVAIL 0x000001d7 297 #define AXXX_CP_CSQ_AVAIL_RING__MASK 0x0000007f 298 #define AXXX_CP_CSQ_AVAIL_RING__SHIFT 0 299 static inline uint32_t AXXX_CP_CSQ_AVAIL_RING(uint32_t val) 300 { 301 return ((val) << AXXX_CP_CSQ_AVAIL_RING__SHIFT) & AXXX_CP_CSQ_AVAIL_RING__MASK; 302 } 303 #define AXXX_CP_CSQ_AVAIL_IB1__MASK 0x00007f00 304 #define AXXX_CP_CSQ_AVAIL_IB1__SHIFT 8 305 static inline uint32_t AXXX_CP_CSQ_AVAIL_IB1(uint32_t val) 306 { 307 return ((val) << AXXX_CP_CSQ_AVAIL_IB1__SHIFT) & AXXX_CP_CSQ_AVAIL_IB1__MASK; 308 } 309 #define AXXX_CP_CSQ_AVAIL_IB2__MASK 0x007f0000 310 #define AXXX_CP_CSQ_AVAIL_IB2__SHIFT 16 311 static inline uint32_t AXXX_CP_CSQ_AVAIL_IB2(uint32_t val) 312 { 313 return ((val) << AXXX_CP_CSQ_AVAIL_IB2__SHIFT) & AXXX_CP_CSQ_AVAIL_IB2__MASK; 314 } 315 316 #define REG_AXXX_CP_STQ_AVAIL 0x000001d8 317 #define AXXX_CP_STQ_AVAIL_ST__MASK 0x0000007f 318 #define AXXX_CP_STQ_AVAIL_ST__SHIFT 0 319 static inline uint32_t AXXX_CP_STQ_AVAIL_ST(uint32_t val) 320 { 321 return ((val) << AXXX_CP_STQ_AVAIL_ST__SHIFT) & AXXX_CP_STQ_AVAIL_ST__MASK; 322 } 323 324 #define REG_AXXX_CP_MEQ_AVAIL 0x000001d9 325 #define AXXX_CP_MEQ_AVAIL_MEQ__MASK 0x0000001f 326 #define AXXX_CP_MEQ_AVAIL_MEQ__SHIFT 0 327 static inline uint32_t AXXX_CP_MEQ_AVAIL_MEQ(uint32_t val) 328 { 329 return ((val) << AXXX_CP_MEQ_AVAIL_MEQ__SHIFT) & AXXX_CP_MEQ_AVAIL_MEQ__MASK; 330 } 331 332 #define REG_AXXX_SCRATCH_UMSK 0x000001dc 333 #define AXXX_SCRATCH_UMSK_UMSK__MASK 0x000000ff 334 #define AXXX_SCRATCH_UMSK_UMSK__SHIFT 0 335 static inline uint32_t AXXX_SCRATCH_UMSK_UMSK(uint32_t val) 336 { 337 return ((val) << AXXX_SCRATCH_UMSK_UMSK__SHIFT) & AXXX_SCRATCH_UMSK_UMSK__MASK; 338 } 339 #define AXXX_SCRATCH_UMSK_SWAP__MASK 0x00030000 340 #define AXXX_SCRATCH_UMSK_SWAP__SHIFT 16 341 static inline uint32_t AXXX_SCRATCH_UMSK_SWAP(uint32_t val) 342 { 343 return ((val) << AXXX_SCRATCH_UMSK_SWAP__SHIFT) & AXXX_SCRATCH_UMSK_SWAP__MASK; 344 } 345 346 #define REG_AXXX_SCRATCH_ADDR 0x000001dd 347 348 #define REG_AXXX_CP_ME_RDADDR 0x000001ea 349 350 #define REG_AXXX_CP_STATE_DEBUG_INDEX 0x000001ec 351 352 #define REG_AXXX_CP_STATE_DEBUG_DATA 0x000001ed 353 354 #define REG_AXXX_CP_INT_CNTL 0x000001f2 355 #define AXXX_CP_INT_CNTL_SW_INT_MASK 0x00080000 356 #define AXXX_CP_INT_CNTL_T0_PACKET_IN_IB_MASK 0x00800000 357 #define AXXX_CP_INT_CNTL_OPCODE_ERROR_MASK 0x01000000 358 #define AXXX_CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK 0x02000000 359 #define AXXX_CP_INT_CNTL_RESERVED_BIT_ERROR_MASK 0x04000000 360 #define AXXX_CP_INT_CNTL_IB_ERROR_MASK 0x08000000 361 #define AXXX_CP_INT_CNTL_IB2_INT_MASK 0x20000000 362 #define AXXX_CP_INT_CNTL_IB1_INT_MASK 0x40000000 363 #define AXXX_CP_INT_CNTL_RB_INT_MASK 0x80000000 364 365 #define REG_AXXX_CP_INT_STATUS 0x000001f3 366 367 #define REG_AXXX_CP_INT_ACK 0x000001f4 368 369 #define REG_AXXX_CP_ME_CNTL 0x000001f6 370 #define AXXX_CP_ME_CNTL_BUSY 0x20000000 371 #define AXXX_CP_ME_CNTL_HALT 0x10000000 372 373 #define REG_AXXX_CP_ME_STATUS 0x000001f7 374 375 #define REG_AXXX_CP_ME_RAM_WADDR 0x000001f8 376 377 #define REG_AXXX_CP_ME_RAM_RADDR 0x000001f9 378 379 #define REG_AXXX_CP_ME_RAM_DATA 0x000001fa 380 381 #define REG_AXXX_CP_DEBUG 0x000001fc 382 #define AXXX_CP_DEBUG_PREDICATE_DISABLE 0x00800000 383 #define AXXX_CP_DEBUG_PROG_END_PTR_ENABLE 0x01000000 384 #define AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE 0x02000000 385 #define AXXX_CP_DEBUG_PREFETCH_PASS_NOPS 0x04000000 386 #define AXXX_CP_DEBUG_DYNAMIC_CLK_DISABLE 0x08000000 387 #define AXXX_CP_DEBUG_PREFETCH_MATCH_DISABLE 0x10000000 388 #define AXXX_CP_DEBUG_SIMPLE_ME_FLOW_CONTROL 0x40000000 389 #define AXXX_CP_DEBUG_MIU_WRITE_PACK_DISABLE 0x80000000 390 391 #define REG_AXXX_CP_CSQ_RB_STAT 0x000001fd 392 #define AXXX_CP_CSQ_RB_STAT_RPTR__MASK 0x0000007f 393 #define AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT 0 394 static inline uint32_t AXXX_CP_CSQ_RB_STAT_RPTR(uint32_t val) 395 { 396 return ((val) << AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_RPTR__MASK; 397 } 398 #define AXXX_CP_CSQ_RB_STAT_WPTR__MASK 0x007f0000 399 #define AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT 16 400 static inline uint32_t AXXX_CP_CSQ_RB_STAT_WPTR(uint32_t val) 401 { 402 return ((val) << AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_WPTR__MASK; 403 } 404 405 #define REG_AXXX_CP_CSQ_IB1_STAT 0x000001fe 406 #define AXXX_CP_CSQ_IB1_STAT_RPTR__MASK 0x0000007f 407 #define AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT 0 408 static inline uint32_t AXXX_CP_CSQ_IB1_STAT_RPTR(uint32_t val) 409 { 410 return ((val) << AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_RPTR__MASK; 411 } 412 #define AXXX_CP_CSQ_IB1_STAT_WPTR__MASK 0x007f0000 413 #define AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT 16 414 static inline uint32_t AXXX_CP_CSQ_IB1_STAT_WPTR(uint32_t val) 415 { 416 return ((val) << AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_WPTR__MASK; 417 } 418 419 #define REG_AXXX_CP_CSQ_IB2_STAT 0x000001ff 420 #define AXXX_CP_CSQ_IB2_STAT_RPTR__MASK 0x0000007f 421 #define AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT 0 422 static inline uint32_t AXXX_CP_CSQ_IB2_STAT_RPTR(uint32_t val) 423 { 424 return ((val) << AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_RPTR__MASK; 425 } 426 #define AXXX_CP_CSQ_IB2_STAT_WPTR__MASK 0x007f0000 427 #define AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT 16 428 static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val) 429 { 430 return ((val) << AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_WPTR__MASK; 431 } 432 433 #define REG_AXXX_CP_NON_PREFETCH_CNTRS 0x00000440 434 435 #define REG_AXXX_CP_STQ_ST_STAT 0x00000443 436 437 #define REG_AXXX_CP_ST_BASE 0x0000044d 438 439 #define REG_AXXX_CP_ST_BUFSZ 0x0000044e 440 441 #define REG_AXXX_CP_MEQ_STAT 0x0000044f 442 443 #define REG_AXXX_CP_MIU_TAG_STAT 0x00000452 444 445 #define REG_AXXX_CP_BIN_MASK_LO 0x00000454 446 447 #define REG_AXXX_CP_BIN_MASK_HI 0x00000455 448 449 #define REG_AXXX_CP_BIN_SELECT_LO 0x00000456 450 451 #define REG_AXXX_CP_BIN_SELECT_HI 0x00000457 452 453 #define REG_AXXX_CP_IB1_BASE 0x00000458 454 455 #define REG_AXXX_CP_IB1_BUFSZ 0x00000459 456 457 #define REG_AXXX_CP_IB2_BASE 0x0000045a 458 459 #define REG_AXXX_CP_IB2_BUFSZ 0x0000045b 460 461 #define REG_AXXX_CP_STAT 0x0000047f 462 #define AXXX_CP_STAT_CP_BUSY__MASK 0x80000000 463 #define AXXX_CP_STAT_CP_BUSY__SHIFT 31 464 static inline uint32_t AXXX_CP_STAT_CP_BUSY(uint32_t val) 465 { 466 return ((val) << AXXX_CP_STAT_CP_BUSY__SHIFT) & AXXX_CP_STAT_CP_BUSY__MASK; 467 } 468 #define AXXX_CP_STAT_VS_EVENT_FIFO_BUSY__MASK 0x40000000 469 #define AXXX_CP_STAT_VS_EVENT_FIFO_BUSY__SHIFT 30 470 static inline uint32_t AXXX_CP_STAT_VS_EVENT_FIFO_BUSY(uint32_t val) 471 { 472 return ((val) << AXXX_CP_STAT_VS_EVENT_FIFO_BUSY__SHIFT) & AXXX_CP_STAT_VS_EVENT_FIFO_BUSY__MASK; 473 } 474 #define AXXX_CP_STAT_PS_EVENT_FIFO_BUSY__MASK 0x20000000 475 #define AXXX_CP_STAT_PS_EVENT_FIFO_BUSY__SHIFT 29 476 static inline uint32_t AXXX_CP_STAT_PS_EVENT_FIFO_BUSY(uint32_t val) 477 { 478 return ((val) << AXXX_CP_STAT_PS_EVENT_FIFO_BUSY__SHIFT) & AXXX_CP_STAT_PS_EVENT_FIFO_BUSY__MASK; 479 } 480 #define AXXX_CP_STAT_CF_EVENT_FIFO_BUSY__MASK 0x10000000 481 #define AXXX_CP_STAT_CF_EVENT_FIFO_BUSY__SHIFT 28 482 static inline uint32_t AXXX_CP_STAT_CF_EVENT_FIFO_BUSY(uint32_t val) 483 { 484 return ((val) << AXXX_CP_STAT_CF_EVENT_FIFO_BUSY__SHIFT) & AXXX_CP_STAT_CF_EVENT_FIFO_BUSY__MASK; 485 } 486 #define AXXX_CP_STAT_RB_EVENT_FIFO_BUSY__MASK 0x08000000 487 #define AXXX_CP_STAT_RB_EVENT_FIFO_BUSY__SHIFT 27 488 static inline uint32_t AXXX_CP_STAT_RB_EVENT_FIFO_BUSY(uint32_t val) 489 { 490 return ((val) << AXXX_CP_STAT_RB_EVENT_FIFO_BUSY__SHIFT) & AXXX_CP_STAT_RB_EVENT_FIFO_BUSY__MASK; 491 } 492 #define AXXX_CP_STAT_ME_BUSY__MASK 0x04000000 493 #define AXXX_CP_STAT_ME_BUSY__SHIFT 26 494 static inline uint32_t AXXX_CP_STAT_ME_BUSY(uint32_t val) 495 { 496 return ((val) << AXXX_CP_STAT_ME_BUSY__SHIFT) & AXXX_CP_STAT_ME_BUSY__MASK; 497 } 498 #define AXXX_CP_STAT_MIU_WR_C_BUSY__MASK 0x02000000 499 #define AXXX_CP_STAT_MIU_WR_C_BUSY__SHIFT 25 500 static inline uint32_t AXXX_CP_STAT_MIU_WR_C_BUSY(uint32_t val) 501 { 502 return ((val) << AXXX_CP_STAT_MIU_WR_C_BUSY__SHIFT) & AXXX_CP_STAT_MIU_WR_C_BUSY__MASK; 503 } 504 #define AXXX_CP_STAT_CP_3D_BUSY__MASK 0x00800000 505 #define AXXX_CP_STAT_CP_3D_BUSY__SHIFT 23 506 static inline uint32_t AXXX_CP_STAT_CP_3D_BUSY(uint32_t val) 507 { 508 return ((val) << AXXX_CP_STAT_CP_3D_BUSY__SHIFT) & AXXX_CP_STAT_CP_3D_BUSY__MASK; 509 } 510 #define AXXX_CP_STAT_CP_NRT_BUSY__MASK 0x00400000 511 #define AXXX_CP_STAT_CP_NRT_BUSY__SHIFT 22 512 static inline uint32_t AXXX_CP_STAT_CP_NRT_BUSY(uint32_t val) 513 { 514 return ((val) << AXXX_CP_STAT_CP_NRT_BUSY__SHIFT) & AXXX_CP_STAT_CP_NRT_BUSY__MASK; 515 } 516 #define AXXX_CP_STAT_RBIU_SCRATCH_BUSY__MASK 0x00200000 517 #define AXXX_CP_STAT_RBIU_SCRATCH_BUSY__SHIFT 21 518 static inline uint32_t AXXX_CP_STAT_RBIU_SCRATCH_BUSY(uint32_t val) 519 { 520 return ((val) << AXXX_CP_STAT_RBIU_SCRATCH_BUSY__SHIFT) & AXXX_CP_STAT_RBIU_SCRATCH_BUSY__MASK; 521 } 522 #define AXXX_CP_STAT_RCIU_ME_BUSY__MASK 0x00100000 523 #define AXXX_CP_STAT_RCIU_ME_BUSY__SHIFT 20 524 static inline uint32_t AXXX_CP_STAT_RCIU_ME_BUSY(uint32_t val) 525 { 526 return ((val) << AXXX_CP_STAT_RCIU_ME_BUSY__SHIFT) & AXXX_CP_STAT_RCIU_ME_BUSY__MASK; 527 } 528 #define AXXX_CP_STAT_RCIU_PFP_BUSY__MASK 0x00080000 529 #define AXXX_CP_STAT_RCIU_PFP_BUSY__SHIFT 19 530 static inline uint32_t AXXX_CP_STAT_RCIU_PFP_BUSY(uint32_t val) 531 { 532 return ((val) << AXXX_CP_STAT_RCIU_PFP_BUSY__SHIFT) & AXXX_CP_STAT_RCIU_PFP_BUSY__MASK; 533 } 534 #define AXXX_CP_STAT_MEQ_RING_BUSY__MASK 0x00040000 535 #define AXXX_CP_STAT_MEQ_RING_BUSY__SHIFT 18 536 static inline uint32_t AXXX_CP_STAT_MEQ_RING_BUSY(uint32_t val) 537 { 538 return ((val) << AXXX_CP_STAT_MEQ_RING_BUSY__SHIFT) & AXXX_CP_STAT_MEQ_RING_BUSY__MASK; 539 } 540 #define AXXX_CP_STAT_PFP_BUSY__MASK 0x00020000 541 #define AXXX_CP_STAT_PFP_BUSY__SHIFT 17 542 static inline uint32_t AXXX_CP_STAT_PFP_BUSY(uint32_t val) 543 { 544 return ((val) << AXXX_CP_STAT_PFP_BUSY__SHIFT) & AXXX_CP_STAT_PFP_BUSY__MASK; 545 } 546 #define AXXX_CP_STAT_ST_QUEUE_BUSY__MASK 0x00010000 547 #define AXXX_CP_STAT_ST_QUEUE_BUSY__SHIFT 16 548 static inline uint32_t AXXX_CP_STAT_ST_QUEUE_BUSY(uint32_t val) 549 { 550 return ((val) << AXXX_CP_STAT_ST_QUEUE_BUSY__SHIFT) & AXXX_CP_STAT_ST_QUEUE_BUSY__MASK; 551 } 552 #define AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY__MASK 0x00002000 553 #define AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY__SHIFT 13 554 static inline uint32_t AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY(uint32_t val) 555 { 556 return ((val) << AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY__SHIFT) & AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY__MASK; 557 } 558 #define AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY__MASK 0x00001000 559 #define AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY__SHIFT 12 560 static inline uint32_t AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY(uint32_t val) 561 { 562 return ((val) << AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY__SHIFT) & AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY__MASK; 563 } 564 #define AXXX_CP_STAT_RING_QUEUE_BUSY__MASK 0x00000800 565 #define AXXX_CP_STAT_RING_QUEUE_BUSY__SHIFT 11 566 static inline uint32_t AXXX_CP_STAT_RING_QUEUE_BUSY(uint32_t val) 567 { 568 return ((val) << AXXX_CP_STAT_RING_QUEUE_BUSY__SHIFT) & AXXX_CP_STAT_RING_QUEUE_BUSY__MASK; 569 } 570 #define AXXX_CP_STAT_CSF_BUSY__MASK 0x00000400 571 #define AXXX_CP_STAT_CSF_BUSY__SHIFT 10 572 static inline uint32_t AXXX_CP_STAT_CSF_BUSY(uint32_t val) 573 { 574 return ((val) << AXXX_CP_STAT_CSF_BUSY__SHIFT) & AXXX_CP_STAT_CSF_BUSY__MASK; 575 } 576 #define AXXX_CP_STAT_CSF_ST_BUSY__MASK 0x00000200 577 #define AXXX_CP_STAT_CSF_ST_BUSY__SHIFT 9 578 static inline uint32_t AXXX_CP_STAT_CSF_ST_BUSY(uint32_t val) 579 { 580 return ((val) << AXXX_CP_STAT_CSF_ST_BUSY__SHIFT) & AXXX_CP_STAT_CSF_ST_BUSY__MASK; 581 } 582 #define AXXX_CP_STAT_EVENT_BUSY__MASK 0x00000100 583 #define AXXX_CP_STAT_EVENT_BUSY__SHIFT 8 584 static inline uint32_t AXXX_CP_STAT_EVENT_BUSY(uint32_t val) 585 { 586 return ((val) << AXXX_CP_STAT_EVENT_BUSY__SHIFT) & AXXX_CP_STAT_EVENT_BUSY__MASK; 587 } 588 #define AXXX_CP_STAT_CSF_INDIRECT2_BUSY__MASK 0x00000080 589 #define AXXX_CP_STAT_CSF_INDIRECT2_BUSY__SHIFT 7 590 static inline uint32_t AXXX_CP_STAT_CSF_INDIRECT2_BUSY(uint32_t val) 591 { 592 return ((val) << AXXX_CP_STAT_CSF_INDIRECT2_BUSY__SHIFT) & AXXX_CP_STAT_CSF_INDIRECT2_BUSY__MASK; 593 } 594 #define AXXX_CP_STAT_CSF_INDIRECTS_BUSY__MASK 0x00000040 595 #define AXXX_CP_STAT_CSF_INDIRECTS_BUSY__SHIFT 6 596 static inline uint32_t AXXX_CP_STAT_CSF_INDIRECTS_BUSY(uint32_t val) 597 { 598 return ((val) << AXXX_CP_STAT_CSF_INDIRECTS_BUSY__SHIFT) & AXXX_CP_STAT_CSF_INDIRECTS_BUSY__MASK; 599 } 600 #define AXXX_CP_STAT_CSF_RING_BUSY__MASK 0x00000020 601 #define AXXX_CP_STAT_CSF_RING_BUSY__SHIFT 5 602 static inline uint32_t AXXX_CP_STAT_CSF_RING_BUSY(uint32_t val) 603 { 604 return ((val) << AXXX_CP_STAT_CSF_RING_BUSY__SHIFT) & AXXX_CP_STAT_CSF_RING_BUSY__MASK; 605 } 606 #define AXXX_CP_STAT_RCIU_BUSY__MASK 0x00000010 607 #define AXXX_CP_STAT_RCIU_BUSY__SHIFT 4 608 static inline uint32_t AXXX_CP_STAT_RCIU_BUSY(uint32_t val) 609 { 610 return ((val) << AXXX_CP_STAT_RCIU_BUSY__SHIFT) & AXXX_CP_STAT_RCIU_BUSY__MASK; 611 } 612 #define AXXX_CP_STAT_RBIU_BUSY__MASK 0x00000008 613 #define AXXX_CP_STAT_RBIU_BUSY__SHIFT 3 614 static inline uint32_t AXXX_CP_STAT_RBIU_BUSY(uint32_t val) 615 { 616 return ((val) << AXXX_CP_STAT_RBIU_BUSY__SHIFT) & AXXX_CP_STAT_RBIU_BUSY__MASK; 617 } 618 #define AXXX_CP_STAT_MIU_RD_RETURN_BUSY__MASK 0x00000004 619 #define AXXX_CP_STAT_MIU_RD_RETURN_BUSY__SHIFT 2 620 static inline uint32_t AXXX_CP_STAT_MIU_RD_RETURN_BUSY(uint32_t val) 621 { 622 return ((val) << AXXX_CP_STAT_MIU_RD_RETURN_BUSY__SHIFT) & AXXX_CP_STAT_MIU_RD_RETURN_BUSY__MASK; 623 } 624 #define AXXX_CP_STAT_MIU_RD_REQ_BUSY__MASK 0x00000002 625 #define AXXX_CP_STAT_MIU_RD_REQ_BUSY__SHIFT 1 626 static inline uint32_t AXXX_CP_STAT_MIU_RD_REQ_BUSY(uint32_t val) 627 { 628 return ((val) << AXXX_CP_STAT_MIU_RD_REQ_BUSY__SHIFT) & AXXX_CP_STAT_MIU_RD_REQ_BUSY__MASK; 629 } 630 #define AXXX_CP_STAT_MIU_WR_BUSY 0x00000001 631 632 #define REG_AXXX_CP_SCRATCH_REG0 0x00000578 633 634 #define REG_AXXX_CP_SCRATCH_REG1 0x00000579 635 636 #define REG_AXXX_CP_SCRATCH_REG2 0x0000057a 637 638 #define REG_AXXX_CP_SCRATCH_REG3 0x0000057b 639 640 #define REG_AXXX_CP_SCRATCH_REG4 0x0000057c 641 642 #define REG_AXXX_CP_SCRATCH_REG5 0x0000057d 643 644 #define REG_AXXX_CP_SCRATCH_REG6 0x0000057e 645 646 #define REG_AXXX_CP_SCRATCH_REG7 0x0000057f 647 648 #define REG_AXXX_CP_ME_VS_EVENT_SRC 0x00000600 649 650 #define REG_AXXX_CP_ME_VS_EVENT_ADDR 0x00000601 651 652 #define REG_AXXX_CP_ME_VS_EVENT_DATA 0x00000602 653 654 #define REG_AXXX_CP_ME_VS_EVENT_ADDR_SWM 0x00000603 655 656 #define REG_AXXX_CP_ME_VS_EVENT_DATA_SWM 0x00000604 657 658 #define REG_AXXX_CP_ME_PS_EVENT_SRC 0x00000605 659 660 #define REG_AXXX_CP_ME_PS_EVENT_ADDR 0x00000606 661 662 #define REG_AXXX_CP_ME_PS_EVENT_DATA 0x00000607 663 664 #define REG_AXXX_CP_ME_PS_EVENT_ADDR_SWM 0x00000608 665 666 #define REG_AXXX_CP_ME_PS_EVENT_DATA_SWM 0x00000609 667 668 #define REG_AXXX_CP_ME_CF_EVENT_SRC 0x0000060a 669 670 #define REG_AXXX_CP_ME_CF_EVENT_ADDR 0x0000060b 671 672 #define REG_AXXX_CP_ME_CF_EVENT_DATA 0x0000060c 673 674 #define REG_AXXX_CP_ME_NRT_ADDR 0x0000060d 675 676 #define REG_AXXX_CP_ME_NRT_DATA 0x0000060e 677 678 #define REG_AXXX_CP_ME_VS_FETCH_DONE_SRC 0x00000612 679 680 #define REG_AXXX_CP_ME_VS_FETCH_DONE_ADDR 0x00000613 681 682 #define REG_AXXX_CP_ME_VS_FETCH_DONE_DATA 0x00000614 683 684 685 #endif /* ADRENO_COMMON_XML */ 686