1 #ifndef ADRENO_COMMON_XML 2 #define ADRENO_COMMON_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 398 bytes, from 2015-09-24 17:25:31) 12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07) 13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14) 14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10755 bytes, from 2015-09-14 20:46:55) 15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27) 16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 67771 bytes, from 2015-09-14 20:46:55) 17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63970 bytes, from 2015-09-14 20:50:12) 18 - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00) 19 20 Copyright (C) 2013-2015 by the following authors: 21 - Rob Clark <robdclark@gmail.com> (robclark) 22 23 Permission is hereby granted, free of charge, to any person obtaining 24 a copy of this software and associated documentation files (the 25 "Software"), to deal in the Software without restriction, including 26 without limitation the rights to use, copy, modify, merge, publish, 27 distribute, sublicense, and/or sell copies of the Software, and to 28 permit persons to whom the Software is furnished to do so, subject to 29 the following conditions: 30 31 The above copyright notice and this permission notice (including the 32 next paragraph) shall be included in all copies or substantial 33 portions of the Software. 34 35 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 37 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 38 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 39 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 40 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 41 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 42 */ 43 44 45 enum adreno_pa_su_sc_draw { 46 PC_DRAW_POINTS = 0, 47 PC_DRAW_LINES = 1, 48 PC_DRAW_TRIANGLES = 2, 49 }; 50 51 enum adreno_compare_func { 52 FUNC_NEVER = 0, 53 FUNC_LESS = 1, 54 FUNC_EQUAL = 2, 55 FUNC_LEQUAL = 3, 56 FUNC_GREATER = 4, 57 FUNC_NOTEQUAL = 5, 58 FUNC_GEQUAL = 6, 59 FUNC_ALWAYS = 7, 60 }; 61 62 enum adreno_stencil_op { 63 STENCIL_KEEP = 0, 64 STENCIL_ZERO = 1, 65 STENCIL_REPLACE = 2, 66 STENCIL_INCR_CLAMP = 3, 67 STENCIL_DECR_CLAMP = 4, 68 STENCIL_INVERT = 5, 69 STENCIL_INCR_WRAP = 6, 70 STENCIL_DECR_WRAP = 7, 71 }; 72 73 enum adreno_rb_blend_factor { 74 FACTOR_ZERO = 0, 75 FACTOR_ONE = 1, 76 FACTOR_SRC_COLOR = 4, 77 FACTOR_ONE_MINUS_SRC_COLOR = 5, 78 FACTOR_SRC_ALPHA = 6, 79 FACTOR_ONE_MINUS_SRC_ALPHA = 7, 80 FACTOR_DST_COLOR = 8, 81 FACTOR_ONE_MINUS_DST_COLOR = 9, 82 FACTOR_DST_ALPHA = 10, 83 FACTOR_ONE_MINUS_DST_ALPHA = 11, 84 FACTOR_CONSTANT_COLOR = 12, 85 FACTOR_ONE_MINUS_CONSTANT_COLOR = 13, 86 FACTOR_CONSTANT_ALPHA = 14, 87 FACTOR_ONE_MINUS_CONSTANT_ALPHA = 15, 88 FACTOR_SRC_ALPHA_SATURATE = 16, 89 FACTOR_SRC1_COLOR = 20, 90 FACTOR_ONE_MINUS_SRC1_COLOR = 21, 91 FACTOR_SRC1_ALPHA = 22, 92 FACTOR_ONE_MINUS_SRC1_ALPHA = 23, 93 }; 94 95 enum adreno_rb_surface_endian { 96 ENDIAN_NONE = 0, 97 ENDIAN_8IN16 = 1, 98 ENDIAN_8IN32 = 2, 99 ENDIAN_16IN32 = 3, 100 ENDIAN_8IN64 = 4, 101 ENDIAN_8IN128 = 5, 102 }; 103 104 enum adreno_rb_dither_mode { 105 DITHER_DISABLE = 0, 106 DITHER_ALWAYS = 1, 107 DITHER_IF_ALPHA_OFF = 2, 108 }; 109 110 enum adreno_rb_depth_format { 111 DEPTHX_16 = 0, 112 DEPTHX_24_8 = 1, 113 DEPTHX_32 = 2, 114 }; 115 116 enum adreno_rb_copy_control_mode { 117 RB_COPY_RESOLVE = 1, 118 RB_COPY_CLEAR = 2, 119 RB_COPY_DEPTH_STENCIL = 5, 120 }; 121 122 enum a3xx_render_mode { 123 RB_RENDERING_PASS = 0, 124 RB_TILING_PASS = 1, 125 RB_RESOLVE_PASS = 2, 126 RB_COMPUTE_PASS = 3, 127 }; 128 129 enum a3xx_msaa_samples { 130 MSAA_ONE = 0, 131 MSAA_TWO = 1, 132 MSAA_FOUR = 2, 133 }; 134 135 enum a3xx_threadmode { 136 MULTI = 0, 137 SINGLE = 1, 138 }; 139 140 enum a3xx_instrbuffermode { 141 CACHE = 0, 142 BUFFER = 1, 143 }; 144 145 enum a3xx_threadsize { 146 TWO_QUADS = 0, 147 FOUR_QUADS = 1, 148 }; 149 150 enum a3xx_color_swap { 151 WZYX = 0, 152 WXYZ = 1, 153 ZYXW = 2, 154 XYZW = 3, 155 }; 156 157 #define REG_AXXX_CP_RB_BASE 0x000001c0 158 159 #define REG_AXXX_CP_RB_CNTL 0x000001c1 160 #define AXXX_CP_RB_CNTL_BUFSZ__MASK 0x0000003f 161 #define AXXX_CP_RB_CNTL_BUFSZ__SHIFT 0 162 static inline uint32_t AXXX_CP_RB_CNTL_BUFSZ(uint32_t val) 163 { 164 return ((val) << AXXX_CP_RB_CNTL_BUFSZ__SHIFT) & AXXX_CP_RB_CNTL_BUFSZ__MASK; 165 } 166 #define AXXX_CP_RB_CNTL_BLKSZ__MASK 0x00003f00 167 #define AXXX_CP_RB_CNTL_BLKSZ__SHIFT 8 168 static inline uint32_t AXXX_CP_RB_CNTL_BLKSZ(uint32_t val) 169 { 170 return ((val) << AXXX_CP_RB_CNTL_BLKSZ__SHIFT) & AXXX_CP_RB_CNTL_BLKSZ__MASK; 171 } 172 #define AXXX_CP_RB_CNTL_BUF_SWAP__MASK 0x00030000 173 #define AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT 16 174 static inline uint32_t AXXX_CP_RB_CNTL_BUF_SWAP(uint32_t val) 175 { 176 return ((val) << AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT) & AXXX_CP_RB_CNTL_BUF_SWAP__MASK; 177 } 178 #define AXXX_CP_RB_CNTL_POLL_EN 0x00100000 179 #define AXXX_CP_RB_CNTL_NO_UPDATE 0x08000000 180 #define AXXX_CP_RB_CNTL_RPTR_WR_EN 0x80000000 181 182 #define REG_AXXX_CP_RB_RPTR_ADDR 0x000001c3 183 #define AXXX_CP_RB_RPTR_ADDR_SWAP__MASK 0x00000003 184 #define AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT 0 185 static inline uint32_t AXXX_CP_RB_RPTR_ADDR_SWAP(uint32_t val) 186 { 187 return ((val) << AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT) & AXXX_CP_RB_RPTR_ADDR_SWAP__MASK; 188 } 189 #define AXXX_CP_RB_RPTR_ADDR_ADDR__MASK 0xfffffffc 190 #define AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT 2 191 static inline uint32_t AXXX_CP_RB_RPTR_ADDR_ADDR(uint32_t val) 192 { 193 return ((val >> 2) << AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT) & AXXX_CP_RB_RPTR_ADDR_ADDR__MASK; 194 } 195 196 #define REG_AXXX_CP_RB_RPTR 0x000001c4 197 198 #define REG_AXXX_CP_RB_WPTR 0x000001c5 199 200 #define REG_AXXX_CP_RB_WPTR_DELAY 0x000001c6 201 202 #define REG_AXXX_CP_RB_RPTR_WR 0x000001c7 203 204 #define REG_AXXX_CP_RB_WPTR_BASE 0x000001c8 205 206 #define REG_AXXX_CP_QUEUE_THRESHOLDS 0x000001d5 207 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK 0x0000000f 208 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT 0 209 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(uint32_t val) 210 { 211 return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK; 212 } 213 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK 0x00000f00 214 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT 8 215 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(uint32_t val) 216 { 217 return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK; 218 } 219 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK 0x000f0000 220 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT 16 221 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(uint32_t val) 222 { 223 return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK; 224 } 225 226 #define REG_AXXX_CP_MEQ_THRESHOLDS 0x000001d6 227 #define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK 0x001f0000 228 #define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT 16 229 static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_MEQ_END(uint32_t val) 230 { 231 return ((val) << AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK; 232 } 233 #define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK 0x1f000000 234 #define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT 24 235 static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_ROQ_END(uint32_t val) 236 { 237 return ((val) << AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK; 238 } 239 240 #define REG_AXXX_CP_CSQ_AVAIL 0x000001d7 241 #define AXXX_CP_CSQ_AVAIL_RING__MASK 0x0000007f 242 #define AXXX_CP_CSQ_AVAIL_RING__SHIFT 0 243 static inline uint32_t AXXX_CP_CSQ_AVAIL_RING(uint32_t val) 244 { 245 return ((val) << AXXX_CP_CSQ_AVAIL_RING__SHIFT) & AXXX_CP_CSQ_AVAIL_RING__MASK; 246 } 247 #define AXXX_CP_CSQ_AVAIL_IB1__MASK 0x00007f00 248 #define AXXX_CP_CSQ_AVAIL_IB1__SHIFT 8 249 static inline uint32_t AXXX_CP_CSQ_AVAIL_IB1(uint32_t val) 250 { 251 return ((val) << AXXX_CP_CSQ_AVAIL_IB1__SHIFT) & AXXX_CP_CSQ_AVAIL_IB1__MASK; 252 } 253 #define AXXX_CP_CSQ_AVAIL_IB2__MASK 0x007f0000 254 #define AXXX_CP_CSQ_AVAIL_IB2__SHIFT 16 255 static inline uint32_t AXXX_CP_CSQ_AVAIL_IB2(uint32_t val) 256 { 257 return ((val) << AXXX_CP_CSQ_AVAIL_IB2__SHIFT) & AXXX_CP_CSQ_AVAIL_IB2__MASK; 258 } 259 260 #define REG_AXXX_CP_STQ_AVAIL 0x000001d8 261 #define AXXX_CP_STQ_AVAIL_ST__MASK 0x0000007f 262 #define AXXX_CP_STQ_AVAIL_ST__SHIFT 0 263 static inline uint32_t AXXX_CP_STQ_AVAIL_ST(uint32_t val) 264 { 265 return ((val) << AXXX_CP_STQ_AVAIL_ST__SHIFT) & AXXX_CP_STQ_AVAIL_ST__MASK; 266 } 267 268 #define REG_AXXX_CP_MEQ_AVAIL 0x000001d9 269 #define AXXX_CP_MEQ_AVAIL_MEQ__MASK 0x0000001f 270 #define AXXX_CP_MEQ_AVAIL_MEQ__SHIFT 0 271 static inline uint32_t AXXX_CP_MEQ_AVAIL_MEQ(uint32_t val) 272 { 273 return ((val) << AXXX_CP_MEQ_AVAIL_MEQ__SHIFT) & AXXX_CP_MEQ_AVAIL_MEQ__MASK; 274 } 275 276 #define REG_AXXX_SCRATCH_UMSK 0x000001dc 277 #define AXXX_SCRATCH_UMSK_UMSK__MASK 0x000000ff 278 #define AXXX_SCRATCH_UMSK_UMSK__SHIFT 0 279 static inline uint32_t AXXX_SCRATCH_UMSK_UMSK(uint32_t val) 280 { 281 return ((val) << AXXX_SCRATCH_UMSK_UMSK__SHIFT) & AXXX_SCRATCH_UMSK_UMSK__MASK; 282 } 283 #define AXXX_SCRATCH_UMSK_SWAP__MASK 0x00030000 284 #define AXXX_SCRATCH_UMSK_SWAP__SHIFT 16 285 static inline uint32_t AXXX_SCRATCH_UMSK_SWAP(uint32_t val) 286 { 287 return ((val) << AXXX_SCRATCH_UMSK_SWAP__SHIFT) & AXXX_SCRATCH_UMSK_SWAP__MASK; 288 } 289 290 #define REG_AXXX_SCRATCH_ADDR 0x000001dd 291 292 #define REG_AXXX_CP_ME_RDADDR 0x000001ea 293 294 #define REG_AXXX_CP_STATE_DEBUG_INDEX 0x000001ec 295 296 #define REG_AXXX_CP_STATE_DEBUG_DATA 0x000001ed 297 298 #define REG_AXXX_CP_INT_CNTL 0x000001f2 299 300 #define REG_AXXX_CP_INT_STATUS 0x000001f3 301 302 #define REG_AXXX_CP_INT_ACK 0x000001f4 303 304 #define REG_AXXX_CP_ME_CNTL 0x000001f6 305 #define AXXX_CP_ME_CNTL_BUSY 0x20000000 306 #define AXXX_CP_ME_CNTL_HALT 0x10000000 307 308 #define REG_AXXX_CP_ME_STATUS 0x000001f7 309 310 #define REG_AXXX_CP_ME_RAM_WADDR 0x000001f8 311 312 #define REG_AXXX_CP_ME_RAM_RADDR 0x000001f9 313 314 #define REG_AXXX_CP_ME_RAM_DATA 0x000001fa 315 316 #define REG_AXXX_CP_DEBUG 0x000001fc 317 #define AXXX_CP_DEBUG_PREDICATE_DISABLE 0x00800000 318 #define AXXX_CP_DEBUG_PROG_END_PTR_ENABLE 0x01000000 319 #define AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE 0x02000000 320 #define AXXX_CP_DEBUG_PREFETCH_PASS_NOPS 0x04000000 321 #define AXXX_CP_DEBUG_DYNAMIC_CLK_DISABLE 0x08000000 322 #define AXXX_CP_DEBUG_PREFETCH_MATCH_DISABLE 0x10000000 323 #define AXXX_CP_DEBUG_SIMPLE_ME_FLOW_CONTROL 0x40000000 324 #define AXXX_CP_DEBUG_MIU_WRITE_PACK_DISABLE 0x80000000 325 326 #define REG_AXXX_CP_CSQ_RB_STAT 0x000001fd 327 #define AXXX_CP_CSQ_RB_STAT_RPTR__MASK 0x0000007f 328 #define AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT 0 329 static inline uint32_t AXXX_CP_CSQ_RB_STAT_RPTR(uint32_t val) 330 { 331 return ((val) << AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_RPTR__MASK; 332 } 333 #define AXXX_CP_CSQ_RB_STAT_WPTR__MASK 0x007f0000 334 #define AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT 16 335 static inline uint32_t AXXX_CP_CSQ_RB_STAT_WPTR(uint32_t val) 336 { 337 return ((val) << AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_WPTR__MASK; 338 } 339 340 #define REG_AXXX_CP_CSQ_IB1_STAT 0x000001fe 341 #define AXXX_CP_CSQ_IB1_STAT_RPTR__MASK 0x0000007f 342 #define AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT 0 343 static inline uint32_t AXXX_CP_CSQ_IB1_STAT_RPTR(uint32_t val) 344 { 345 return ((val) << AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_RPTR__MASK; 346 } 347 #define AXXX_CP_CSQ_IB1_STAT_WPTR__MASK 0x007f0000 348 #define AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT 16 349 static inline uint32_t AXXX_CP_CSQ_IB1_STAT_WPTR(uint32_t val) 350 { 351 return ((val) << AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_WPTR__MASK; 352 } 353 354 #define REG_AXXX_CP_CSQ_IB2_STAT 0x000001ff 355 #define AXXX_CP_CSQ_IB2_STAT_RPTR__MASK 0x0000007f 356 #define AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT 0 357 static inline uint32_t AXXX_CP_CSQ_IB2_STAT_RPTR(uint32_t val) 358 { 359 return ((val) << AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_RPTR__MASK; 360 } 361 #define AXXX_CP_CSQ_IB2_STAT_WPTR__MASK 0x007f0000 362 #define AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT 16 363 static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val) 364 { 365 return ((val) << AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_WPTR__MASK; 366 } 367 368 #define REG_AXXX_CP_NON_PREFETCH_CNTRS 0x00000440 369 370 #define REG_AXXX_CP_STQ_ST_STAT 0x00000443 371 372 #define REG_AXXX_CP_ST_BASE 0x0000044d 373 374 #define REG_AXXX_CP_ST_BUFSZ 0x0000044e 375 376 #define REG_AXXX_CP_MEQ_STAT 0x0000044f 377 378 #define REG_AXXX_CP_MIU_TAG_STAT 0x00000452 379 380 #define REG_AXXX_CP_BIN_MASK_LO 0x00000454 381 382 #define REG_AXXX_CP_BIN_MASK_HI 0x00000455 383 384 #define REG_AXXX_CP_BIN_SELECT_LO 0x00000456 385 386 #define REG_AXXX_CP_BIN_SELECT_HI 0x00000457 387 388 #define REG_AXXX_CP_IB1_BASE 0x00000458 389 390 #define REG_AXXX_CP_IB1_BUFSZ 0x00000459 391 392 #define REG_AXXX_CP_IB2_BASE 0x0000045a 393 394 #define REG_AXXX_CP_IB2_BUFSZ 0x0000045b 395 396 #define REG_AXXX_CP_STAT 0x0000047f 397 398 #define REG_AXXX_CP_SCRATCH_REG0 0x00000578 399 400 #define REG_AXXX_CP_SCRATCH_REG1 0x00000579 401 402 #define REG_AXXX_CP_SCRATCH_REG2 0x0000057a 403 404 #define REG_AXXX_CP_SCRATCH_REG3 0x0000057b 405 406 #define REG_AXXX_CP_SCRATCH_REG4 0x0000057c 407 408 #define REG_AXXX_CP_SCRATCH_REG5 0x0000057d 409 410 #define REG_AXXX_CP_SCRATCH_REG6 0x0000057e 411 412 #define REG_AXXX_CP_SCRATCH_REG7 0x0000057f 413 414 #define REG_AXXX_CP_ME_VS_EVENT_SRC 0x00000600 415 416 #define REG_AXXX_CP_ME_VS_EVENT_ADDR 0x00000601 417 418 #define REG_AXXX_CP_ME_VS_EVENT_DATA 0x00000602 419 420 #define REG_AXXX_CP_ME_VS_EVENT_ADDR_SWM 0x00000603 421 422 #define REG_AXXX_CP_ME_VS_EVENT_DATA_SWM 0x00000604 423 424 #define REG_AXXX_CP_ME_PS_EVENT_SRC 0x00000605 425 426 #define REG_AXXX_CP_ME_PS_EVENT_ADDR 0x00000606 427 428 #define REG_AXXX_CP_ME_PS_EVENT_DATA 0x00000607 429 430 #define REG_AXXX_CP_ME_PS_EVENT_ADDR_SWM 0x00000608 431 432 #define REG_AXXX_CP_ME_PS_EVENT_DATA_SWM 0x00000609 433 434 #define REG_AXXX_CP_ME_CF_EVENT_SRC 0x0000060a 435 436 #define REG_AXXX_CP_ME_CF_EVENT_ADDR 0x0000060b 437 438 #define REG_AXXX_CP_ME_CF_EVENT_DATA 0x0000060c 439 440 #define REG_AXXX_CP_ME_NRT_ADDR 0x0000060d 441 442 #define REG_AXXX_CP_ME_NRT_DATA 0x0000060e 443 444 #define REG_AXXX_CP_ME_VS_FETCH_DONE_SRC 0x00000612 445 446 #define REG_AXXX_CP_ME_VS_FETCH_DONE_ADDR 0x00000613 447 448 #define REG_AXXX_CP_ME_VS_FETCH_DONE_DATA 0x00000614 449 450 451 #endif /* ADRENO_COMMON_XML */ 452