1 #ifndef ADRENO_COMMON_XML 2 #define ADRENO_COMMON_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13) 12 - /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13) 13 - /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 42463 bytes, from 2018-11-19 13:44:03) 14 - /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14201 bytes, from 2018-12-02 17:29:54) 15 - /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 43052 bytes, from 2018-12-02 17:29:54) 16 - /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13) 17 - /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13) 18 - /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-12-02 17:29:54) 19 - /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 140790 bytes, from 2018-12-02 17:29:54) 20 - /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07) 21 - /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13) 22 23 Copyright (C) 2013-2018 by the following authors: 24 - Rob Clark <robdclark@gmail.com> (robclark) 25 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) 26 27 Permission is hereby granted, free of charge, to any person obtaining 28 a copy of this software and associated documentation files (the 29 "Software"), to deal in the Software without restriction, including 30 without limitation the rights to use, copy, modify, merge, publish, 31 distribute, sublicense, and/or sell copies of the Software, and to 32 permit persons to whom the Software is furnished to do so, subject to 33 the following conditions: 34 35 The above copyright notice and this permission notice (including the 36 next paragraph) shall be included in all copies or substantial 37 portions of the Software. 38 39 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 40 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 41 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 42 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 43 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 44 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 45 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 46 */ 47 48 49 enum chip { 50 A2XX = 0, 51 A3XX = 0, 52 A4XX = 0, 53 A5XX = 0, 54 A6XX = 0, 55 }; 56 57 enum adreno_pa_su_sc_draw { 58 PC_DRAW_POINTS = 0, 59 PC_DRAW_LINES = 1, 60 PC_DRAW_TRIANGLES = 2, 61 }; 62 63 enum adreno_compare_func { 64 FUNC_NEVER = 0, 65 FUNC_LESS = 1, 66 FUNC_EQUAL = 2, 67 FUNC_LEQUAL = 3, 68 FUNC_GREATER = 4, 69 FUNC_NOTEQUAL = 5, 70 FUNC_GEQUAL = 6, 71 FUNC_ALWAYS = 7, 72 }; 73 74 enum adreno_stencil_op { 75 STENCIL_KEEP = 0, 76 STENCIL_ZERO = 1, 77 STENCIL_REPLACE = 2, 78 STENCIL_INCR_CLAMP = 3, 79 STENCIL_DECR_CLAMP = 4, 80 STENCIL_INVERT = 5, 81 STENCIL_INCR_WRAP = 6, 82 STENCIL_DECR_WRAP = 7, 83 }; 84 85 enum adreno_rb_blend_factor { 86 FACTOR_ZERO = 0, 87 FACTOR_ONE = 1, 88 FACTOR_SRC_COLOR = 4, 89 FACTOR_ONE_MINUS_SRC_COLOR = 5, 90 FACTOR_SRC_ALPHA = 6, 91 FACTOR_ONE_MINUS_SRC_ALPHA = 7, 92 FACTOR_DST_COLOR = 8, 93 FACTOR_ONE_MINUS_DST_COLOR = 9, 94 FACTOR_DST_ALPHA = 10, 95 FACTOR_ONE_MINUS_DST_ALPHA = 11, 96 FACTOR_CONSTANT_COLOR = 12, 97 FACTOR_ONE_MINUS_CONSTANT_COLOR = 13, 98 FACTOR_CONSTANT_ALPHA = 14, 99 FACTOR_ONE_MINUS_CONSTANT_ALPHA = 15, 100 FACTOR_SRC_ALPHA_SATURATE = 16, 101 FACTOR_SRC1_COLOR = 20, 102 FACTOR_ONE_MINUS_SRC1_COLOR = 21, 103 FACTOR_SRC1_ALPHA = 22, 104 FACTOR_ONE_MINUS_SRC1_ALPHA = 23, 105 }; 106 107 enum adreno_rb_surface_endian { 108 ENDIAN_NONE = 0, 109 ENDIAN_8IN16 = 1, 110 ENDIAN_8IN32 = 2, 111 ENDIAN_16IN32 = 3, 112 ENDIAN_8IN64 = 4, 113 ENDIAN_8IN128 = 5, 114 }; 115 116 enum adreno_rb_dither_mode { 117 DITHER_DISABLE = 0, 118 DITHER_ALWAYS = 1, 119 DITHER_IF_ALPHA_OFF = 2, 120 }; 121 122 enum adreno_rb_depth_format { 123 DEPTHX_16 = 0, 124 DEPTHX_24_8 = 1, 125 DEPTHX_32 = 2, 126 }; 127 128 enum adreno_rb_copy_control_mode { 129 RB_COPY_RESOLVE = 1, 130 RB_COPY_CLEAR = 2, 131 RB_COPY_DEPTH_STENCIL = 5, 132 }; 133 134 enum a3xx_rop_code { 135 ROP_CLEAR = 0, 136 ROP_NOR = 1, 137 ROP_AND_INVERTED = 2, 138 ROP_COPY_INVERTED = 3, 139 ROP_AND_REVERSE = 4, 140 ROP_INVERT = 5, 141 ROP_NAND = 7, 142 ROP_AND = 8, 143 ROP_EQUIV = 9, 144 ROP_NOOP = 10, 145 ROP_OR_INVERTED = 11, 146 ROP_OR_REVERSE = 13, 147 ROP_OR = 14, 148 ROP_SET = 15, 149 }; 150 151 enum a3xx_render_mode { 152 RB_RENDERING_PASS = 0, 153 RB_TILING_PASS = 1, 154 RB_RESOLVE_PASS = 2, 155 RB_COMPUTE_PASS = 3, 156 }; 157 158 enum a3xx_msaa_samples { 159 MSAA_ONE = 0, 160 MSAA_TWO = 1, 161 MSAA_FOUR = 2, 162 }; 163 164 enum a3xx_threadmode { 165 MULTI = 0, 166 SINGLE = 1, 167 }; 168 169 enum a3xx_instrbuffermode { 170 CACHE = 0, 171 BUFFER = 1, 172 }; 173 174 enum a3xx_threadsize { 175 TWO_QUADS = 0, 176 FOUR_QUADS = 1, 177 }; 178 179 enum a3xx_color_swap { 180 WZYX = 0, 181 WXYZ = 1, 182 ZYXW = 2, 183 XYZW = 3, 184 }; 185 186 enum a3xx_rb_blend_opcode { 187 BLEND_DST_PLUS_SRC = 0, 188 BLEND_SRC_MINUS_DST = 1, 189 BLEND_DST_MINUS_SRC = 2, 190 BLEND_MIN_DST_SRC = 3, 191 BLEND_MAX_DST_SRC = 4, 192 }; 193 194 enum a4xx_tess_spacing { 195 EQUAL_SPACING = 0, 196 ODD_SPACING = 2, 197 EVEN_SPACING = 3, 198 }; 199 200 #define REG_AXXX_CP_RB_BASE 0x000001c0 201 202 #define REG_AXXX_CP_RB_CNTL 0x000001c1 203 #define AXXX_CP_RB_CNTL_BUFSZ__MASK 0x0000003f 204 #define AXXX_CP_RB_CNTL_BUFSZ__SHIFT 0 205 static inline uint32_t AXXX_CP_RB_CNTL_BUFSZ(uint32_t val) 206 { 207 return ((val) << AXXX_CP_RB_CNTL_BUFSZ__SHIFT) & AXXX_CP_RB_CNTL_BUFSZ__MASK; 208 } 209 #define AXXX_CP_RB_CNTL_BLKSZ__MASK 0x00003f00 210 #define AXXX_CP_RB_CNTL_BLKSZ__SHIFT 8 211 static inline uint32_t AXXX_CP_RB_CNTL_BLKSZ(uint32_t val) 212 { 213 return ((val) << AXXX_CP_RB_CNTL_BLKSZ__SHIFT) & AXXX_CP_RB_CNTL_BLKSZ__MASK; 214 } 215 #define AXXX_CP_RB_CNTL_BUF_SWAP__MASK 0x00030000 216 #define AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT 16 217 static inline uint32_t AXXX_CP_RB_CNTL_BUF_SWAP(uint32_t val) 218 { 219 return ((val) << AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT) & AXXX_CP_RB_CNTL_BUF_SWAP__MASK; 220 } 221 #define AXXX_CP_RB_CNTL_POLL_EN 0x00100000 222 #define AXXX_CP_RB_CNTL_NO_UPDATE 0x08000000 223 #define AXXX_CP_RB_CNTL_RPTR_WR_EN 0x80000000 224 225 #define REG_AXXX_CP_RB_RPTR_ADDR 0x000001c3 226 #define AXXX_CP_RB_RPTR_ADDR_SWAP__MASK 0x00000003 227 #define AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT 0 228 static inline uint32_t AXXX_CP_RB_RPTR_ADDR_SWAP(uint32_t val) 229 { 230 return ((val) << AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT) & AXXX_CP_RB_RPTR_ADDR_SWAP__MASK; 231 } 232 #define AXXX_CP_RB_RPTR_ADDR_ADDR__MASK 0xfffffffc 233 #define AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT 2 234 static inline uint32_t AXXX_CP_RB_RPTR_ADDR_ADDR(uint32_t val) 235 { 236 return ((val >> 2) << AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT) & AXXX_CP_RB_RPTR_ADDR_ADDR__MASK; 237 } 238 239 #define REG_AXXX_CP_RB_RPTR 0x000001c4 240 241 #define REG_AXXX_CP_RB_WPTR 0x000001c5 242 243 #define REG_AXXX_CP_RB_WPTR_DELAY 0x000001c6 244 245 #define REG_AXXX_CP_RB_RPTR_WR 0x000001c7 246 247 #define REG_AXXX_CP_RB_WPTR_BASE 0x000001c8 248 249 #define REG_AXXX_CP_QUEUE_THRESHOLDS 0x000001d5 250 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK 0x0000000f 251 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT 0 252 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(uint32_t val) 253 { 254 return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK; 255 } 256 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK 0x00000f00 257 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT 8 258 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(uint32_t val) 259 { 260 return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK; 261 } 262 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK 0x000f0000 263 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT 16 264 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(uint32_t val) 265 { 266 return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK; 267 } 268 269 #define REG_AXXX_CP_MEQ_THRESHOLDS 0x000001d6 270 #define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK 0x001f0000 271 #define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT 16 272 static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_MEQ_END(uint32_t val) 273 { 274 return ((val) << AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK; 275 } 276 #define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK 0x1f000000 277 #define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT 24 278 static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_ROQ_END(uint32_t val) 279 { 280 return ((val) << AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK; 281 } 282 283 #define REG_AXXX_CP_CSQ_AVAIL 0x000001d7 284 #define AXXX_CP_CSQ_AVAIL_RING__MASK 0x0000007f 285 #define AXXX_CP_CSQ_AVAIL_RING__SHIFT 0 286 static inline uint32_t AXXX_CP_CSQ_AVAIL_RING(uint32_t val) 287 { 288 return ((val) << AXXX_CP_CSQ_AVAIL_RING__SHIFT) & AXXX_CP_CSQ_AVAIL_RING__MASK; 289 } 290 #define AXXX_CP_CSQ_AVAIL_IB1__MASK 0x00007f00 291 #define AXXX_CP_CSQ_AVAIL_IB1__SHIFT 8 292 static inline uint32_t AXXX_CP_CSQ_AVAIL_IB1(uint32_t val) 293 { 294 return ((val) << AXXX_CP_CSQ_AVAIL_IB1__SHIFT) & AXXX_CP_CSQ_AVAIL_IB1__MASK; 295 } 296 #define AXXX_CP_CSQ_AVAIL_IB2__MASK 0x007f0000 297 #define AXXX_CP_CSQ_AVAIL_IB2__SHIFT 16 298 static inline uint32_t AXXX_CP_CSQ_AVAIL_IB2(uint32_t val) 299 { 300 return ((val) << AXXX_CP_CSQ_AVAIL_IB2__SHIFT) & AXXX_CP_CSQ_AVAIL_IB2__MASK; 301 } 302 303 #define REG_AXXX_CP_STQ_AVAIL 0x000001d8 304 #define AXXX_CP_STQ_AVAIL_ST__MASK 0x0000007f 305 #define AXXX_CP_STQ_AVAIL_ST__SHIFT 0 306 static inline uint32_t AXXX_CP_STQ_AVAIL_ST(uint32_t val) 307 { 308 return ((val) << AXXX_CP_STQ_AVAIL_ST__SHIFT) & AXXX_CP_STQ_AVAIL_ST__MASK; 309 } 310 311 #define REG_AXXX_CP_MEQ_AVAIL 0x000001d9 312 #define AXXX_CP_MEQ_AVAIL_MEQ__MASK 0x0000001f 313 #define AXXX_CP_MEQ_AVAIL_MEQ__SHIFT 0 314 static inline uint32_t AXXX_CP_MEQ_AVAIL_MEQ(uint32_t val) 315 { 316 return ((val) << AXXX_CP_MEQ_AVAIL_MEQ__SHIFT) & AXXX_CP_MEQ_AVAIL_MEQ__MASK; 317 } 318 319 #define REG_AXXX_SCRATCH_UMSK 0x000001dc 320 #define AXXX_SCRATCH_UMSK_UMSK__MASK 0x000000ff 321 #define AXXX_SCRATCH_UMSK_UMSK__SHIFT 0 322 static inline uint32_t AXXX_SCRATCH_UMSK_UMSK(uint32_t val) 323 { 324 return ((val) << AXXX_SCRATCH_UMSK_UMSK__SHIFT) & AXXX_SCRATCH_UMSK_UMSK__MASK; 325 } 326 #define AXXX_SCRATCH_UMSK_SWAP__MASK 0x00030000 327 #define AXXX_SCRATCH_UMSK_SWAP__SHIFT 16 328 static inline uint32_t AXXX_SCRATCH_UMSK_SWAP(uint32_t val) 329 { 330 return ((val) << AXXX_SCRATCH_UMSK_SWAP__SHIFT) & AXXX_SCRATCH_UMSK_SWAP__MASK; 331 } 332 333 #define REG_AXXX_SCRATCH_ADDR 0x000001dd 334 335 #define REG_AXXX_CP_ME_RDADDR 0x000001ea 336 337 #define REG_AXXX_CP_STATE_DEBUG_INDEX 0x000001ec 338 339 #define REG_AXXX_CP_STATE_DEBUG_DATA 0x000001ed 340 341 #define REG_AXXX_CP_INT_CNTL 0x000001f2 342 #define AXXX_CP_INT_CNTL_SW_INT_MASK 0x00080000 343 #define AXXX_CP_INT_CNTL_T0_PACKET_IN_IB_MASK 0x00800000 344 #define AXXX_CP_INT_CNTL_OPCODE_ERROR_MASK 0x01000000 345 #define AXXX_CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK 0x02000000 346 #define AXXX_CP_INT_CNTL_RESERVED_BIT_ERROR_MASK 0x04000000 347 #define AXXX_CP_INT_CNTL_IB_ERROR_MASK 0x08000000 348 #define AXXX_CP_INT_CNTL_IB2_INT_MASK 0x20000000 349 #define AXXX_CP_INT_CNTL_IB1_INT_MASK 0x40000000 350 #define AXXX_CP_INT_CNTL_RB_INT_MASK 0x80000000 351 352 #define REG_AXXX_CP_INT_STATUS 0x000001f3 353 354 #define REG_AXXX_CP_INT_ACK 0x000001f4 355 356 #define REG_AXXX_CP_ME_CNTL 0x000001f6 357 #define AXXX_CP_ME_CNTL_BUSY 0x20000000 358 #define AXXX_CP_ME_CNTL_HALT 0x10000000 359 360 #define REG_AXXX_CP_ME_STATUS 0x000001f7 361 362 #define REG_AXXX_CP_ME_RAM_WADDR 0x000001f8 363 364 #define REG_AXXX_CP_ME_RAM_RADDR 0x000001f9 365 366 #define REG_AXXX_CP_ME_RAM_DATA 0x000001fa 367 368 #define REG_AXXX_CP_DEBUG 0x000001fc 369 #define AXXX_CP_DEBUG_PREDICATE_DISABLE 0x00800000 370 #define AXXX_CP_DEBUG_PROG_END_PTR_ENABLE 0x01000000 371 #define AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE 0x02000000 372 #define AXXX_CP_DEBUG_PREFETCH_PASS_NOPS 0x04000000 373 #define AXXX_CP_DEBUG_DYNAMIC_CLK_DISABLE 0x08000000 374 #define AXXX_CP_DEBUG_PREFETCH_MATCH_DISABLE 0x10000000 375 #define AXXX_CP_DEBUG_SIMPLE_ME_FLOW_CONTROL 0x40000000 376 #define AXXX_CP_DEBUG_MIU_WRITE_PACK_DISABLE 0x80000000 377 378 #define REG_AXXX_CP_CSQ_RB_STAT 0x000001fd 379 #define AXXX_CP_CSQ_RB_STAT_RPTR__MASK 0x0000007f 380 #define AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT 0 381 static inline uint32_t AXXX_CP_CSQ_RB_STAT_RPTR(uint32_t val) 382 { 383 return ((val) << AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_RPTR__MASK; 384 } 385 #define AXXX_CP_CSQ_RB_STAT_WPTR__MASK 0x007f0000 386 #define AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT 16 387 static inline uint32_t AXXX_CP_CSQ_RB_STAT_WPTR(uint32_t val) 388 { 389 return ((val) << AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_WPTR__MASK; 390 } 391 392 #define REG_AXXX_CP_CSQ_IB1_STAT 0x000001fe 393 #define AXXX_CP_CSQ_IB1_STAT_RPTR__MASK 0x0000007f 394 #define AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT 0 395 static inline uint32_t AXXX_CP_CSQ_IB1_STAT_RPTR(uint32_t val) 396 { 397 return ((val) << AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_RPTR__MASK; 398 } 399 #define AXXX_CP_CSQ_IB1_STAT_WPTR__MASK 0x007f0000 400 #define AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT 16 401 static inline uint32_t AXXX_CP_CSQ_IB1_STAT_WPTR(uint32_t val) 402 { 403 return ((val) << AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_WPTR__MASK; 404 } 405 406 #define REG_AXXX_CP_CSQ_IB2_STAT 0x000001ff 407 #define AXXX_CP_CSQ_IB2_STAT_RPTR__MASK 0x0000007f 408 #define AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT 0 409 static inline uint32_t AXXX_CP_CSQ_IB2_STAT_RPTR(uint32_t val) 410 { 411 return ((val) << AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_RPTR__MASK; 412 } 413 #define AXXX_CP_CSQ_IB2_STAT_WPTR__MASK 0x007f0000 414 #define AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT 16 415 static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val) 416 { 417 return ((val) << AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_WPTR__MASK; 418 } 419 420 #define REG_AXXX_CP_NON_PREFETCH_CNTRS 0x00000440 421 422 #define REG_AXXX_CP_STQ_ST_STAT 0x00000443 423 424 #define REG_AXXX_CP_ST_BASE 0x0000044d 425 426 #define REG_AXXX_CP_ST_BUFSZ 0x0000044e 427 428 #define REG_AXXX_CP_MEQ_STAT 0x0000044f 429 430 #define REG_AXXX_CP_MIU_TAG_STAT 0x00000452 431 432 #define REG_AXXX_CP_BIN_MASK_LO 0x00000454 433 434 #define REG_AXXX_CP_BIN_MASK_HI 0x00000455 435 436 #define REG_AXXX_CP_BIN_SELECT_LO 0x00000456 437 438 #define REG_AXXX_CP_BIN_SELECT_HI 0x00000457 439 440 #define REG_AXXX_CP_IB1_BASE 0x00000458 441 442 #define REG_AXXX_CP_IB1_BUFSZ 0x00000459 443 444 #define REG_AXXX_CP_IB2_BASE 0x0000045a 445 446 #define REG_AXXX_CP_IB2_BUFSZ 0x0000045b 447 448 #define REG_AXXX_CP_STAT 0x0000047f 449 #define AXXX_CP_STAT_CP_BUSY 0x80000000 450 #define AXXX_CP_STAT_VS_EVENT_FIFO_BUSY 0x40000000 451 #define AXXX_CP_STAT_PS_EVENT_FIFO_BUSY 0x20000000 452 #define AXXX_CP_STAT_CF_EVENT_FIFO_BUSY 0x10000000 453 #define AXXX_CP_STAT_RB_EVENT_FIFO_BUSY 0x08000000 454 #define AXXX_CP_STAT_ME_BUSY 0x04000000 455 #define AXXX_CP_STAT_MIU_WR_C_BUSY 0x02000000 456 #define AXXX_CP_STAT_CP_3D_BUSY 0x00800000 457 #define AXXX_CP_STAT_CP_NRT_BUSY 0x00400000 458 #define AXXX_CP_STAT_RBIU_SCRATCH_BUSY 0x00200000 459 #define AXXX_CP_STAT_RCIU_ME_BUSY 0x00100000 460 #define AXXX_CP_STAT_RCIU_PFP_BUSY 0x00080000 461 #define AXXX_CP_STAT_MEQ_RING_BUSY 0x00040000 462 #define AXXX_CP_STAT_PFP_BUSY 0x00020000 463 #define AXXX_CP_STAT_ST_QUEUE_BUSY 0x00010000 464 #define AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY 0x00002000 465 #define AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY 0x00001000 466 #define AXXX_CP_STAT_RING_QUEUE_BUSY 0x00000800 467 #define AXXX_CP_STAT_CSF_BUSY 0x00000400 468 #define AXXX_CP_STAT_CSF_ST_BUSY 0x00000200 469 #define AXXX_CP_STAT_EVENT_BUSY 0x00000100 470 #define AXXX_CP_STAT_CSF_INDIRECT2_BUSY 0x00000080 471 #define AXXX_CP_STAT_CSF_INDIRECTS_BUSY 0x00000040 472 #define AXXX_CP_STAT_CSF_RING_BUSY 0x00000020 473 #define AXXX_CP_STAT_RCIU_BUSY 0x00000010 474 #define AXXX_CP_STAT_RBIU_BUSY 0x00000008 475 #define AXXX_CP_STAT_MIU_RD_RETURN_BUSY 0x00000004 476 #define AXXX_CP_STAT_MIU_RD_REQ_BUSY 0x00000002 477 #define AXXX_CP_STAT_MIU_WR_BUSY 0x00000001 478 479 #define REG_AXXX_CP_SCRATCH_REG0 0x00000578 480 481 #define REG_AXXX_CP_SCRATCH_REG1 0x00000579 482 483 #define REG_AXXX_CP_SCRATCH_REG2 0x0000057a 484 485 #define REG_AXXX_CP_SCRATCH_REG3 0x0000057b 486 487 #define REG_AXXX_CP_SCRATCH_REG4 0x0000057c 488 489 #define REG_AXXX_CP_SCRATCH_REG5 0x0000057d 490 491 #define REG_AXXX_CP_SCRATCH_REG6 0x0000057e 492 493 #define REG_AXXX_CP_SCRATCH_REG7 0x0000057f 494 495 #define REG_AXXX_CP_ME_VS_EVENT_SRC 0x00000600 496 497 #define REG_AXXX_CP_ME_VS_EVENT_ADDR 0x00000601 498 499 #define REG_AXXX_CP_ME_VS_EVENT_DATA 0x00000602 500 501 #define REG_AXXX_CP_ME_VS_EVENT_ADDR_SWM 0x00000603 502 503 #define REG_AXXX_CP_ME_VS_EVENT_DATA_SWM 0x00000604 504 505 #define REG_AXXX_CP_ME_PS_EVENT_SRC 0x00000605 506 507 #define REG_AXXX_CP_ME_PS_EVENT_ADDR 0x00000606 508 509 #define REG_AXXX_CP_ME_PS_EVENT_DATA 0x00000607 510 511 #define REG_AXXX_CP_ME_PS_EVENT_ADDR_SWM 0x00000608 512 513 #define REG_AXXX_CP_ME_PS_EVENT_DATA_SWM 0x00000609 514 515 #define REG_AXXX_CP_ME_CF_EVENT_SRC 0x0000060a 516 517 #define REG_AXXX_CP_ME_CF_EVENT_ADDR 0x0000060b 518 519 #define REG_AXXX_CP_ME_CF_EVENT_DATA 0x0000060c 520 521 #define REG_AXXX_CP_ME_NRT_ADDR 0x0000060d 522 523 #define REG_AXXX_CP_ME_NRT_DATA 0x0000060e 524 525 #define REG_AXXX_CP_ME_VS_FETCH_DONE_SRC 0x00000612 526 527 #define REG_AXXX_CP_ME_VS_FETCH_DONE_ADDR 0x00000613 528 529 #define REG_AXXX_CP_ME_VS_FETCH_DONE_DATA 0x00000614 530 531 532 #endif /* ADRENO_COMMON_XML */ 533