1 #ifndef ADRENO_COMMON_XML
2 #define ADRENO_COMMON_XML
3 
4 /* Autogenerated file, DO NOT EDIT manually!
5 
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
9 
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml                     (    594 bytes, from 2023-03-10 18:32:52)
12 - /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml        (   1572 bytes, from 2022-07-23 20:21:46)
13 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml                (  91929 bytes, from 2023-02-28 23:52:27)
14 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml       (  15434 bytes, from 2023-03-10 18:32:53)
15 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml          (  74995 bytes, from 2023-03-20 18:06:23)
16 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml                (  84231 bytes, from 2022-08-02 16:38:43)
17 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml                ( 113474 bytes, from 2022-08-02 16:38:43)
18 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml                ( 149590 bytes, from 2023-02-14 19:37:12)
19 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml                ( 198949 bytes, from 2023-03-20 18:06:23)
20 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml            (  11404 bytes, from 2023-03-10 18:32:53)
21 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml               (   1773 bytes, from 2022-08-02 16:38:43)
22 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml (   9055 bytes, from 2023-03-10 18:32:52)
23 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml    (   2976 bytes, from 2023-03-10 18:32:52)
24 
25 Copyright (C) 2013-2023 by the following authors:
26 - Rob Clark <robdclark@gmail.com> (robclark)
27 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
28 
29 Permission is hereby granted, free of charge, to any person obtaining
30 a copy of this software and associated documentation files (the
31 "Software"), to deal in the Software without restriction, including
32 without limitation the rights to use, copy, modify, merge, publish,
33 distribute, sublicense, and/or sell copies of the Software, and to
34 permit persons to whom the Software is furnished to do so, subject to
35 the following conditions:
36 
37 The above copyright notice and this permission notice (including the
38 next paragraph) shall be included in all copies or substantial
39 portions of the Software.
40 
41 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
42 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
43 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
44 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
45 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
46 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
47 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
48 */
49 
50 
51 enum chip {
52 	A2XX = 2,
53 	A3XX = 3,
54 	A4XX = 4,
55 	A5XX = 5,
56 	A6XX = 6,
57 	A7XX = 7,
58 };
59 
60 enum adreno_pa_su_sc_draw {
61 	PC_DRAW_POINTS = 0,
62 	PC_DRAW_LINES = 1,
63 	PC_DRAW_TRIANGLES = 2,
64 };
65 
66 enum adreno_compare_func {
67 	FUNC_NEVER = 0,
68 	FUNC_LESS = 1,
69 	FUNC_EQUAL = 2,
70 	FUNC_LEQUAL = 3,
71 	FUNC_GREATER = 4,
72 	FUNC_NOTEQUAL = 5,
73 	FUNC_GEQUAL = 6,
74 	FUNC_ALWAYS = 7,
75 };
76 
77 enum adreno_stencil_op {
78 	STENCIL_KEEP = 0,
79 	STENCIL_ZERO = 1,
80 	STENCIL_REPLACE = 2,
81 	STENCIL_INCR_CLAMP = 3,
82 	STENCIL_DECR_CLAMP = 4,
83 	STENCIL_INVERT = 5,
84 	STENCIL_INCR_WRAP = 6,
85 	STENCIL_DECR_WRAP = 7,
86 };
87 
88 enum adreno_rb_blend_factor {
89 	FACTOR_ZERO = 0,
90 	FACTOR_ONE = 1,
91 	FACTOR_SRC_COLOR = 4,
92 	FACTOR_ONE_MINUS_SRC_COLOR = 5,
93 	FACTOR_SRC_ALPHA = 6,
94 	FACTOR_ONE_MINUS_SRC_ALPHA = 7,
95 	FACTOR_DST_COLOR = 8,
96 	FACTOR_ONE_MINUS_DST_COLOR = 9,
97 	FACTOR_DST_ALPHA = 10,
98 	FACTOR_ONE_MINUS_DST_ALPHA = 11,
99 	FACTOR_CONSTANT_COLOR = 12,
100 	FACTOR_ONE_MINUS_CONSTANT_COLOR = 13,
101 	FACTOR_CONSTANT_ALPHA = 14,
102 	FACTOR_ONE_MINUS_CONSTANT_ALPHA = 15,
103 	FACTOR_SRC_ALPHA_SATURATE = 16,
104 	FACTOR_SRC1_COLOR = 20,
105 	FACTOR_ONE_MINUS_SRC1_COLOR = 21,
106 	FACTOR_SRC1_ALPHA = 22,
107 	FACTOR_ONE_MINUS_SRC1_ALPHA = 23,
108 };
109 
110 enum adreno_rb_surface_endian {
111 	ENDIAN_NONE = 0,
112 	ENDIAN_8IN16 = 1,
113 	ENDIAN_8IN32 = 2,
114 	ENDIAN_16IN32 = 3,
115 	ENDIAN_8IN64 = 4,
116 	ENDIAN_8IN128 = 5,
117 };
118 
119 enum adreno_rb_dither_mode {
120 	DITHER_DISABLE = 0,
121 	DITHER_ALWAYS = 1,
122 	DITHER_IF_ALPHA_OFF = 2,
123 };
124 
125 enum adreno_rb_depth_format {
126 	DEPTHX_16 = 0,
127 	DEPTHX_24_8 = 1,
128 	DEPTHX_32 = 2,
129 };
130 
131 enum adreno_rb_copy_control_mode {
132 	RB_COPY_RESOLVE = 1,
133 	RB_COPY_CLEAR = 2,
134 	RB_COPY_DEPTH_STENCIL = 5,
135 };
136 
137 enum a3xx_rop_code {
138 	ROP_CLEAR = 0,
139 	ROP_NOR = 1,
140 	ROP_AND_INVERTED = 2,
141 	ROP_COPY_INVERTED = 3,
142 	ROP_AND_REVERSE = 4,
143 	ROP_INVERT = 5,
144 	ROP_NAND = 7,
145 	ROP_AND = 8,
146 	ROP_EQUIV = 9,
147 	ROP_NOOP = 10,
148 	ROP_OR_INVERTED = 11,
149 	ROP_OR_REVERSE = 13,
150 	ROP_OR = 14,
151 	ROP_SET = 15,
152 };
153 
154 enum a3xx_render_mode {
155 	RB_RENDERING_PASS = 0,
156 	RB_TILING_PASS = 1,
157 	RB_RESOLVE_PASS = 2,
158 	RB_COMPUTE_PASS = 3,
159 };
160 
161 enum a3xx_msaa_samples {
162 	MSAA_ONE = 0,
163 	MSAA_TWO = 1,
164 	MSAA_FOUR = 2,
165 	MSAA_EIGHT = 3,
166 };
167 
168 enum a3xx_threadmode {
169 	MULTI = 0,
170 	SINGLE = 1,
171 };
172 
173 enum a3xx_instrbuffermode {
174 	CACHE = 0,
175 	BUFFER = 1,
176 };
177 
178 enum a3xx_threadsize {
179 	TWO_QUADS = 0,
180 	FOUR_QUADS = 1,
181 };
182 
183 enum a3xx_color_swap {
184 	WZYX = 0,
185 	WXYZ = 1,
186 	ZYXW = 2,
187 	XYZW = 3,
188 };
189 
190 enum a3xx_rb_blend_opcode {
191 	BLEND_DST_PLUS_SRC = 0,
192 	BLEND_SRC_MINUS_DST = 1,
193 	BLEND_DST_MINUS_SRC = 2,
194 	BLEND_MIN_DST_SRC = 3,
195 	BLEND_MAX_DST_SRC = 4,
196 };
197 
198 enum a4xx_tess_spacing {
199 	EQUAL_SPACING = 0,
200 	ODD_SPACING = 2,
201 	EVEN_SPACING = 3,
202 };
203 
204 enum a5xx_address_mode {
205 	ADDR_32B = 0,
206 	ADDR_64B = 1,
207 };
208 
209 enum a5xx_line_mode {
210 	BRESENHAM = 0,
211 	RECTANGULAR = 1,
212 };
213 
214 enum a6xx_tex_prefetch_cmd {
215 	TEX_PREFETCH_UNK0 = 0,
216 	TEX_PREFETCH_SAM = 1,
217 	TEX_PREFETCH_GATHER4R = 2,
218 	TEX_PREFETCH_GATHER4G = 3,
219 	TEX_PREFETCH_GATHER4B = 4,
220 	TEX_PREFETCH_GATHER4A = 5,
221 	TEX_PREFETCH_UNK6 = 6,
222 	TEX_PREFETCH_UNK7 = 7,
223 };
224 
225 #define REG_AXXX_CP_RB_BASE					0x000001c0
226 
227 #define REG_AXXX_CP_RB_CNTL					0x000001c1
228 #define AXXX_CP_RB_CNTL_BUFSZ__MASK				0x0000003f
229 #define AXXX_CP_RB_CNTL_BUFSZ__SHIFT				0
230 static inline uint32_t AXXX_CP_RB_CNTL_BUFSZ(uint32_t val)
231 {
232 	return ((val) << AXXX_CP_RB_CNTL_BUFSZ__SHIFT) & AXXX_CP_RB_CNTL_BUFSZ__MASK;
233 }
234 #define AXXX_CP_RB_CNTL_BLKSZ__MASK				0x00003f00
235 #define AXXX_CP_RB_CNTL_BLKSZ__SHIFT				8
236 static inline uint32_t AXXX_CP_RB_CNTL_BLKSZ(uint32_t val)
237 {
238 	return ((val) << AXXX_CP_RB_CNTL_BLKSZ__SHIFT) & AXXX_CP_RB_CNTL_BLKSZ__MASK;
239 }
240 #define AXXX_CP_RB_CNTL_BUF_SWAP__MASK				0x00030000
241 #define AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT				16
242 static inline uint32_t AXXX_CP_RB_CNTL_BUF_SWAP(uint32_t val)
243 {
244 	return ((val) << AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT) & AXXX_CP_RB_CNTL_BUF_SWAP__MASK;
245 }
246 #define AXXX_CP_RB_CNTL_POLL_EN					0x00100000
247 #define AXXX_CP_RB_CNTL_NO_UPDATE				0x08000000
248 #define AXXX_CP_RB_CNTL_RPTR_WR_EN				0x80000000
249 
250 #define REG_AXXX_CP_RB_RPTR_ADDR				0x000001c3
251 #define AXXX_CP_RB_RPTR_ADDR_SWAP__MASK				0x00000003
252 #define AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT			0
253 static inline uint32_t AXXX_CP_RB_RPTR_ADDR_SWAP(uint32_t val)
254 {
255 	return ((val) << AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT) & AXXX_CP_RB_RPTR_ADDR_SWAP__MASK;
256 }
257 #define AXXX_CP_RB_RPTR_ADDR_ADDR__MASK				0xfffffffc
258 #define AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT			2
259 static inline uint32_t AXXX_CP_RB_RPTR_ADDR_ADDR(uint32_t val)
260 {
261 	return ((val >> 2) << AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT) & AXXX_CP_RB_RPTR_ADDR_ADDR__MASK;
262 }
263 
264 #define REG_AXXX_CP_RB_RPTR					0x000001c4
265 
266 #define REG_AXXX_CP_RB_WPTR					0x000001c5
267 
268 #define REG_AXXX_CP_RB_WPTR_DELAY				0x000001c6
269 
270 #define REG_AXXX_CP_RB_RPTR_WR					0x000001c7
271 
272 #define REG_AXXX_CP_RB_WPTR_BASE				0x000001c8
273 
274 #define REG_AXXX_CP_QUEUE_THRESHOLDS				0x000001d5
275 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK		0x0000000f
276 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT		0
277 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(uint32_t val)
278 {
279 	return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK;
280 }
281 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK		0x00000f00
282 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT		8
283 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(uint32_t val)
284 {
285 	return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK;
286 }
287 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK		0x000f0000
288 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT		16
289 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(uint32_t val)
290 {
291 	return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK;
292 }
293 
294 #define REG_AXXX_CP_MEQ_THRESHOLDS				0x000001d6
295 #define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK			0x001f0000
296 #define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT			16
297 static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_MEQ_END(uint32_t val)
298 {
299 	return ((val) << AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK;
300 }
301 #define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK			0x1f000000
302 #define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT			24
303 static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_ROQ_END(uint32_t val)
304 {
305 	return ((val) << AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK;
306 }
307 
308 #define REG_AXXX_CP_CSQ_AVAIL					0x000001d7
309 #define AXXX_CP_CSQ_AVAIL_RING__MASK				0x0000007f
310 #define AXXX_CP_CSQ_AVAIL_RING__SHIFT				0
311 static inline uint32_t AXXX_CP_CSQ_AVAIL_RING(uint32_t val)
312 {
313 	return ((val) << AXXX_CP_CSQ_AVAIL_RING__SHIFT) & AXXX_CP_CSQ_AVAIL_RING__MASK;
314 }
315 #define AXXX_CP_CSQ_AVAIL_IB1__MASK				0x00007f00
316 #define AXXX_CP_CSQ_AVAIL_IB1__SHIFT				8
317 static inline uint32_t AXXX_CP_CSQ_AVAIL_IB1(uint32_t val)
318 {
319 	return ((val) << AXXX_CP_CSQ_AVAIL_IB1__SHIFT) & AXXX_CP_CSQ_AVAIL_IB1__MASK;
320 }
321 #define AXXX_CP_CSQ_AVAIL_IB2__MASK				0x007f0000
322 #define AXXX_CP_CSQ_AVAIL_IB2__SHIFT				16
323 static inline uint32_t AXXX_CP_CSQ_AVAIL_IB2(uint32_t val)
324 {
325 	return ((val) << AXXX_CP_CSQ_AVAIL_IB2__SHIFT) & AXXX_CP_CSQ_AVAIL_IB2__MASK;
326 }
327 
328 #define REG_AXXX_CP_STQ_AVAIL					0x000001d8
329 #define AXXX_CP_STQ_AVAIL_ST__MASK				0x0000007f
330 #define AXXX_CP_STQ_AVAIL_ST__SHIFT				0
331 static inline uint32_t AXXX_CP_STQ_AVAIL_ST(uint32_t val)
332 {
333 	return ((val) << AXXX_CP_STQ_AVAIL_ST__SHIFT) & AXXX_CP_STQ_AVAIL_ST__MASK;
334 }
335 
336 #define REG_AXXX_CP_MEQ_AVAIL					0x000001d9
337 #define AXXX_CP_MEQ_AVAIL_MEQ__MASK				0x0000001f
338 #define AXXX_CP_MEQ_AVAIL_MEQ__SHIFT				0
339 static inline uint32_t AXXX_CP_MEQ_AVAIL_MEQ(uint32_t val)
340 {
341 	return ((val) << AXXX_CP_MEQ_AVAIL_MEQ__SHIFT) & AXXX_CP_MEQ_AVAIL_MEQ__MASK;
342 }
343 
344 #define REG_AXXX_SCRATCH_UMSK					0x000001dc
345 #define AXXX_SCRATCH_UMSK_UMSK__MASK				0x000000ff
346 #define AXXX_SCRATCH_UMSK_UMSK__SHIFT				0
347 static inline uint32_t AXXX_SCRATCH_UMSK_UMSK(uint32_t val)
348 {
349 	return ((val) << AXXX_SCRATCH_UMSK_UMSK__SHIFT) & AXXX_SCRATCH_UMSK_UMSK__MASK;
350 }
351 #define AXXX_SCRATCH_UMSK_SWAP__MASK				0x00030000
352 #define AXXX_SCRATCH_UMSK_SWAP__SHIFT				16
353 static inline uint32_t AXXX_SCRATCH_UMSK_SWAP(uint32_t val)
354 {
355 	return ((val) << AXXX_SCRATCH_UMSK_SWAP__SHIFT) & AXXX_SCRATCH_UMSK_SWAP__MASK;
356 }
357 
358 #define REG_AXXX_SCRATCH_ADDR					0x000001dd
359 
360 #define REG_AXXX_CP_ME_RDADDR					0x000001ea
361 
362 #define REG_AXXX_CP_STATE_DEBUG_INDEX				0x000001ec
363 
364 #define REG_AXXX_CP_STATE_DEBUG_DATA				0x000001ed
365 
366 #define REG_AXXX_CP_INT_CNTL					0x000001f2
367 #define AXXX_CP_INT_CNTL_SW_INT_MASK				0x00080000
368 #define AXXX_CP_INT_CNTL_T0_PACKET_IN_IB_MASK			0x00800000
369 #define AXXX_CP_INT_CNTL_OPCODE_ERROR_MASK			0x01000000
370 #define AXXX_CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK		0x02000000
371 #define AXXX_CP_INT_CNTL_RESERVED_BIT_ERROR_MASK		0x04000000
372 #define AXXX_CP_INT_CNTL_IB_ERROR_MASK				0x08000000
373 #define AXXX_CP_INT_CNTL_IB2_INT_MASK				0x20000000
374 #define AXXX_CP_INT_CNTL_IB1_INT_MASK				0x40000000
375 #define AXXX_CP_INT_CNTL_RB_INT_MASK				0x80000000
376 
377 #define REG_AXXX_CP_INT_STATUS					0x000001f3
378 
379 #define REG_AXXX_CP_INT_ACK					0x000001f4
380 
381 #define REG_AXXX_CP_ME_CNTL					0x000001f6
382 #define AXXX_CP_ME_CNTL_BUSY					0x20000000
383 #define AXXX_CP_ME_CNTL_HALT					0x10000000
384 
385 #define REG_AXXX_CP_ME_STATUS					0x000001f7
386 
387 #define REG_AXXX_CP_ME_RAM_WADDR				0x000001f8
388 
389 #define REG_AXXX_CP_ME_RAM_RADDR				0x000001f9
390 
391 #define REG_AXXX_CP_ME_RAM_DATA					0x000001fa
392 
393 #define REG_AXXX_CP_DEBUG					0x000001fc
394 #define AXXX_CP_DEBUG_PREDICATE_DISABLE				0x00800000
395 #define AXXX_CP_DEBUG_PROG_END_PTR_ENABLE			0x01000000
396 #define AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE			0x02000000
397 #define AXXX_CP_DEBUG_PREFETCH_PASS_NOPS			0x04000000
398 #define AXXX_CP_DEBUG_DYNAMIC_CLK_DISABLE			0x08000000
399 #define AXXX_CP_DEBUG_PREFETCH_MATCH_DISABLE			0x10000000
400 #define AXXX_CP_DEBUG_SIMPLE_ME_FLOW_CONTROL			0x40000000
401 #define AXXX_CP_DEBUG_MIU_WRITE_PACK_DISABLE			0x80000000
402 
403 #define REG_AXXX_CP_CSQ_RB_STAT					0x000001fd
404 #define AXXX_CP_CSQ_RB_STAT_RPTR__MASK				0x0000007f
405 #define AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT				0
406 static inline uint32_t AXXX_CP_CSQ_RB_STAT_RPTR(uint32_t val)
407 {
408 	return ((val) << AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_RPTR__MASK;
409 }
410 #define AXXX_CP_CSQ_RB_STAT_WPTR__MASK				0x007f0000
411 #define AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT				16
412 static inline uint32_t AXXX_CP_CSQ_RB_STAT_WPTR(uint32_t val)
413 {
414 	return ((val) << AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_WPTR__MASK;
415 }
416 
417 #define REG_AXXX_CP_CSQ_IB1_STAT				0x000001fe
418 #define AXXX_CP_CSQ_IB1_STAT_RPTR__MASK				0x0000007f
419 #define AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT			0
420 static inline uint32_t AXXX_CP_CSQ_IB1_STAT_RPTR(uint32_t val)
421 {
422 	return ((val) << AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_RPTR__MASK;
423 }
424 #define AXXX_CP_CSQ_IB1_STAT_WPTR__MASK				0x007f0000
425 #define AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT			16
426 static inline uint32_t AXXX_CP_CSQ_IB1_STAT_WPTR(uint32_t val)
427 {
428 	return ((val) << AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_WPTR__MASK;
429 }
430 
431 #define REG_AXXX_CP_CSQ_IB2_STAT				0x000001ff
432 #define AXXX_CP_CSQ_IB2_STAT_RPTR__MASK				0x0000007f
433 #define AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT			0
434 static inline uint32_t AXXX_CP_CSQ_IB2_STAT_RPTR(uint32_t val)
435 {
436 	return ((val) << AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_RPTR__MASK;
437 }
438 #define AXXX_CP_CSQ_IB2_STAT_WPTR__MASK				0x007f0000
439 #define AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT			16
440 static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val)
441 {
442 	return ((val) << AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_WPTR__MASK;
443 }
444 
445 #define REG_AXXX_CP_NON_PREFETCH_CNTRS				0x00000440
446 
447 #define REG_AXXX_CP_STQ_ST_STAT					0x00000443
448 
449 #define REG_AXXX_CP_ST_BASE					0x0000044d
450 
451 #define REG_AXXX_CP_ST_BUFSZ					0x0000044e
452 
453 #define REG_AXXX_CP_MEQ_STAT					0x0000044f
454 
455 #define REG_AXXX_CP_MIU_TAG_STAT				0x00000452
456 
457 #define REG_AXXX_CP_BIN_MASK_LO					0x00000454
458 
459 #define REG_AXXX_CP_BIN_MASK_HI					0x00000455
460 
461 #define REG_AXXX_CP_BIN_SELECT_LO				0x00000456
462 
463 #define REG_AXXX_CP_BIN_SELECT_HI				0x00000457
464 
465 #define REG_AXXX_CP_IB1_BASE					0x00000458
466 
467 #define REG_AXXX_CP_IB1_BUFSZ					0x00000459
468 
469 #define REG_AXXX_CP_IB2_BASE					0x0000045a
470 
471 #define REG_AXXX_CP_IB2_BUFSZ					0x0000045b
472 
473 #define REG_AXXX_CP_STAT					0x0000047f
474 #define AXXX_CP_STAT_CP_BUSY__MASK				0x80000000
475 #define AXXX_CP_STAT_CP_BUSY__SHIFT				31
476 static inline uint32_t AXXX_CP_STAT_CP_BUSY(uint32_t val)
477 {
478 	return ((val) << AXXX_CP_STAT_CP_BUSY__SHIFT) & AXXX_CP_STAT_CP_BUSY__MASK;
479 }
480 #define AXXX_CP_STAT_VS_EVENT_FIFO_BUSY__MASK			0x40000000
481 #define AXXX_CP_STAT_VS_EVENT_FIFO_BUSY__SHIFT			30
482 static inline uint32_t AXXX_CP_STAT_VS_EVENT_FIFO_BUSY(uint32_t val)
483 {
484 	return ((val) << AXXX_CP_STAT_VS_EVENT_FIFO_BUSY__SHIFT) & AXXX_CP_STAT_VS_EVENT_FIFO_BUSY__MASK;
485 }
486 #define AXXX_CP_STAT_PS_EVENT_FIFO_BUSY__MASK			0x20000000
487 #define AXXX_CP_STAT_PS_EVENT_FIFO_BUSY__SHIFT			29
488 static inline uint32_t AXXX_CP_STAT_PS_EVENT_FIFO_BUSY(uint32_t val)
489 {
490 	return ((val) << AXXX_CP_STAT_PS_EVENT_FIFO_BUSY__SHIFT) & AXXX_CP_STAT_PS_EVENT_FIFO_BUSY__MASK;
491 }
492 #define AXXX_CP_STAT_CF_EVENT_FIFO_BUSY__MASK			0x10000000
493 #define AXXX_CP_STAT_CF_EVENT_FIFO_BUSY__SHIFT			28
494 static inline uint32_t AXXX_CP_STAT_CF_EVENT_FIFO_BUSY(uint32_t val)
495 {
496 	return ((val) << AXXX_CP_STAT_CF_EVENT_FIFO_BUSY__SHIFT) & AXXX_CP_STAT_CF_EVENT_FIFO_BUSY__MASK;
497 }
498 #define AXXX_CP_STAT_RB_EVENT_FIFO_BUSY__MASK			0x08000000
499 #define AXXX_CP_STAT_RB_EVENT_FIFO_BUSY__SHIFT			27
500 static inline uint32_t AXXX_CP_STAT_RB_EVENT_FIFO_BUSY(uint32_t val)
501 {
502 	return ((val) << AXXX_CP_STAT_RB_EVENT_FIFO_BUSY__SHIFT) & AXXX_CP_STAT_RB_EVENT_FIFO_BUSY__MASK;
503 }
504 #define AXXX_CP_STAT_ME_BUSY__MASK				0x04000000
505 #define AXXX_CP_STAT_ME_BUSY__SHIFT				26
506 static inline uint32_t AXXX_CP_STAT_ME_BUSY(uint32_t val)
507 {
508 	return ((val) << AXXX_CP_STAT_ME_BUSY__SHIFT) & AXXX_CP_STAT_ME_BUSY__MASK;
509 }
510 #define AXXX_CP_STAT_MIU_WR_C_BUSY__MASK			0x02000000
511 #define AXXX_CP_STAT_MIU_WR_C_BUSY__SHIFT			25
512 static inline uint32_t AXXX_CP_STAT_MIU_WR_C_BUSY(uint32_t val)
513 {
514 	return ((val) << AXXX_CP_STAT_MIU_WR_C_BUSY__SHIFT) & AXXX_CP_STAT_MIU_WR_C_BUSY__MASK;
515 }
516 #define AXXX_CP_STAT_CP_3D_BUSY__MASK				0x00800000
517 #define AXXX_CP_STAT_CP_3D_BUSY__SHIFT				23
518 static inline uint32_t AXXX_CP_STAT_CP_3D_BUSY(uint32_t val)
519 {
520 	return ((val) << AXXX_CP_STAT_CP_3D_BUSY__SHIFT) & AXXX_CP_STAT_CP_3D_BUSY__MASK;
521 }
522 #define AXXX_CP_STAT_CP_NRT_BUSY__MASK				0x00400000
523 #define AXXX_CP_STAT_CP_NRT_BUSY__SHIFT				22
524 static inline uint32_t AXXX_CP_STAT_CP_NRT_BUSY(uint32_t val)
525 {
526 	return ((val) << AXXX_CP_STAT_CP_NRT_BUSY__SHIFT) & AXXX_CP_STAT_CP_NRT_BUSY__MASK;
527 }
528 #define AXXX_CP_STAT_RBIU_SCRATCH_BUSY__MASK			0x00200000
529 #define AXXX_CP_STAT_RBIU_SCRATCH_BUSY__SHIFT			21
530 static inline uint32_t AXXX_CP_STAT_RBIU_SCRATCH_BUSY(uint32_t val)
531 {
532 	return ((val) << AXXX_CP_STAT_RBIU_SCRATCH_BUSY__SHIFT) & AXXX_CP_STAT_RBIU_SCRATCH_BUSY__MASK;
533 }
534 #define AXXX_CP_STAT_RCIU_ME_BUSY__MASK				0x00100000
535 #define AXXX_CP_STAT_RCIU_ME_BUSY__SHIFT			20
536 static inline uint32_t AXXX_CP_STAT_RCIU_ME_BUSY(uint32_t val)
537 {
538 	return ((val) << AXXX_CP_STAT_RCIU_ME_BUSY__SHIFT) & AXXX_CP_STAT_RCIU_ME_BUSY__MASK;
539 }
540 #define AXXX_CP_STAT_RCIU_PFP_BUSY__MASK			0x00080000
541 #define AXXX_CP_STAT_RCIU_PFP_BUSY__SHIFT			19
542 static inline uint32_t AXXX_CP_STAT_RCIU_PFP_BUSY(uint32_t val)
543 {
544 	return ((val) << AXXX_CP_STAT_RCIU_PFP_BUSY__SHIFT) & AXXX_CP_STAT_RCIU_PFP_BUSY__MASK;
545 }
546 #define AXXX_CP_STAT_MEQ_RING_BUSY__MASK			0x00040000
547 #define AXXX_CP_STAT_MEQ_RING_BUSY__SHIFT			18
548 static inline uint32_t AXXX_CP_STAT_MEQ_RING_BUSY(uint32_t val)
549 {
550 	return ((val) << AXXX_CP_STAT_MEQ_RING_BUSY__SHIFT) & AXXX_CP_STAT_MEQ_RING_BUSY__MASK;
551 }
552 #define AXXX_CP_STAT_PFP_BUSY__MASK				0x00020000
553 #define AXXX_CP_STAT_PFP_BUSY__SHIFT				17
554 static inline uint32_t AXXX_CP_STAT_PFP_BUSY(uint32_t val)
555 {
556 	return ((val) << AXXX_CP_STAT_PFP_BUSY__SHIFT) & AXXX_CP_STAT_PFP_BUSY__MASK;
557 }
558 #define AXXX_CP_STAT_ST_QUEUE_BUSY__MASK			0x00010000
559 #define AXXX_CP_STAT_ST_QUEUE_BUSY__SHIFT			16
560 static inline uint32_t AXXX_CP_STAT_ST_QUEUE_BUSY(uint32_t val)
561 {
562 	return ((val) << AXXX_CP_STAT_ST_QUEUE_BUSY__SHIFT) & AXXX_CP_STAT_ST_QUEUE_BUSY__MASK;
563 }
564 #define AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY__MASK			0x00002000
565 #define AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY__SHIFT		13
566 static inline uint32_t AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY(uint32_t val)
567 {
568 	return ((val) << AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY__SHIFT) & AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY__MASK;
569 }
570 #define AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY__MASK			0x00001000
571 #define AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY__SHIFT		12
572 static inline uint32_t AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY(uint32_t val)
573 {
574 	return ((val) << AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY__SHIFT) & AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY__MASK;
575 }
576 #define AXXX_CP_STAT_RING_QUEUE_BUSY__MASK			0x00000800
577 #define AXXX_CP_STAT_RING_QUEUE_BUSY__SHIFT			11
578 static inline uint32_t AXXX_CP_STAT_RING_QUEUE_BUSY(uint32_t val)
579 {
580 	return ((val) << AXXX_CP_STAT_RING_QUEUE_BUSY__SHIFT) & AXXX_CP_STAT_RING_QUEUE_BUSY__MASK;
581 }
582 #define AXXX_CP_STAT_CSF_BUSY__MASK				0x00000400
583 #define AXXX_CP_STAT_CSF_BUSY__SHIFT				10
584 static inline uint32_t AXXX_CP_STAT_CSF_BUSY(uint32_t val)
585 {
586 	return ((val) << AXXX_CP_STAT_CSF_BUSY__SHIFT) & AXXX_CP_STAT_CSF_BUSY__MASK;
587 }
588 #define AXXX_CP_STAT_CSF_ST_BUSY__MASK				0x00000200
589 #define AXXX_CP_STAT_CSF_ST_BUSY__SHIFT				9
590 static inline uint32_t AXXX_CP_STAT_CSF_ST_BUSY(uint32_t val)
591 {
592 	return ((val) << AXXX_CP_STAT_CSF_ST_BUSY__SHIFT) & AXXX_CP_STAT_CSF_ST_BUSY__MASK;
593 }
594 #define AXXX_CP_STAT_EVENT_BUSY__MASK				0x00000100
595 #define AXXX_CP_STAT_EVENT_BUSY__SHIFT				8
596 static inline uint32_t AXXX_CP_STAT_EVENT_BUSY(uint32_t val)
597 {
598 	return ((val) << AXXX_CP_STAT_EVENT_BUSY__SHIFT) & AXXX_CP_STAT_EVENT_BUSY__MASK;
599 }
600 #define AXXX_CP_STAT_CSF_INDIRECT2_BUSY__MASK			0x00000080
601 #define AXXX_CP_STAT_CSF_INDIRECT2_BUSY__SHIFT			7
602 static inline uint32_t AXXX_CP_STAT_CSF_INDIRECT2_BUSY(uint32_t val)
603 {
604 	return ((val) << AXXX_CP_STAT_CSF_INDIRECT2_BUSY__SHIFT) & AXXX_CP_STAT_CSF_INDIRECT2_BUSY__MASK;
605 }
606 #define AXXX_CP_STAT_CSF_INDIRECTS_BUSY__MASK			0x00000040
607 #define AXXX_CP_STAT_CSF_INDIRECTS_BUSY__SHIFT			6
608 static inline uint32_t AXXX_CP_STAT_CSF_INDIRECTS_BUSY(uint32_t val)
609 {
610 	return ((val) << AXXX_CP_STAT_CSF_INDIRECTS_BUSY__SHIFT) & AXXX_CP_STAT_CSF_INDIRECTS_BUSY__MASK;
611 }
612 #define AXXX_CP_STAT_CSF_RING_BUSY__MASK			0x00000020
613 #define AXXX_CP_STAT_CSF_RING_BUSY__SHIFT			5
614 static inline uint32_t AXXX_CP_STAT_CSF_RING_BUSY(uint32_t val)
615 {
616 	return ((val) << AXXX_CP_STAT_CSF_RING_BUSY__SHIFT) & AXXX_CP_STAT_CSF_RING_BUSY__MASK;
617 }
618 #define AXXX_CP_STAT_RCIU_BUSY__MASK				0x00000010
619 #define AXXX_CP_STAT_RCIU_BUSY__SHIFT				4
620 static inline uint32_t AXXX_CP_STAT_RCIU_BUSY(uint32_t val)
621 {
622 	return ((val) << AXXX_CP_STAT_RCIU_BUSY__SHIFT) & AXXX_CP_STAT_RCIU_BUSY__MASK;
623 }
624 #define AXXX_CP_STAT_RBIU_BUSY__MASK				0x00000008
625 #define AXXX_CP_STAT_RBIU_BUSY__SHIFT				3
626 static inline uint32_t AXXX_CP_STAT_RBIU_BUSY(uint32_t val)
627 {
628 	return ((val) << AXXX_CP_STAT_RBIU_BUSY__SHIFT) & AXXX_CP_STAT_RBIU_BUSY__MASK;
629 }
630 #define AXXX_CP_STAT_MIU_RD_RETURN_BUSY__MASK			0x00000004
631 #define AXXX_CP_STAT_MIU_RD_RETURN_BUSY__SHIFT			2
632 static inline uint32_t AXXX_CP_STAT_MIU_RD_RETURN_BUSY(uint32_t val)
633 {
634 	return ((val) << AXXX_CP_STAT_MIU_RD_RETURN_BUSY__SHIFT) & AXXX_CP_STAT_MIU_RD_RETURN_BUSY__MASK;
635 }
636 #define AXXX_CP_STAT_MIU_RD_REQ_BUSY__MASK			0x00000002
637 #define AXXX_CP_STAT_MIU_RD_REQ_BUSY__SHIFT			1
638 static inline uint32_t AXXX_CP_STAT_MIU_RD_REQ_BUSY(uint32_t val)
639 {
640 	return ((val) << AXXX_CP_STAT_MIU_RD_REQ_BUSY__SHIFT) & AXXX_CP_STAT_MIU_RD_REQ_BUSY__MASK;
641 }
642 #define AXXX_CP_STAT_MIU_WR_BUSY				0x00000001
643 
644 #define REG_AXXX_CP_SCRATCH_REG0				0x00000578
645 
646 #define REG_AXXX_CP_SCRATCH_REG1				0x00000579
647 
648 #define REG_AXXX_CP_SCRATCH_REG2				0x0000057a
649 
650 #define REG_AXXX_CP_SCRATCH_REG3				0x0000057b
651 
652 #define REG_AXXX_CP_SCRATCH_REG4				0x0000057c
653 
654 #define REG_AXXX_CP_SCRATCH_REG5				0x0000057d
655 
656 #define REG_AXXX_CP_SCRATCH_REG6				0x0000057e
657 
658 #define REG_AXXX_CP_SCRATCH_REG7				0x0000057f
659 
660 #define REG_AXXX_CP_ME_VS_EVENT_SRC				0x00000600
661 
662 #define REG_AXXX_CP_ME_VS_EVENT_ADDR				0x00000601
663 
664 #define REG_AXXX_CP_ME_VS_EVENT_DATA				0x00000602
665 
666 #define REG_AXXX_CP_ME_VS_EVENT_ADDR_SWM			0x00000603
667 
668 #define REG_AXXX_CP_ME_VS_EVENT_DATA_SWM			0x00000604
669 
670 #define REG_AXXX_CP_ME_PS_EVENT_SRC				0x00000605
671 
672 #define REG_AXXX_CP_ME_PS_EVENT_ADDR				0x00000606
673 
674 #define REG_AXXX_CP_ME_PS_EVENT_DATA				0x00000607
675 
676 #define REG_AXXX_CP_ME_PS_EVENT_ADDR_SWM			0x00000608
677 
678 #define REG_AXXX_CP_ME_PS_EVENT_DATA_SWM			0x00000609
679 
680 #define REG_AXXX_CP_ME_CF_EVENT_SRC				0x0000060a
681 
682 #define REG_AXXX_CP_ME_CF_EVENT_ADDR				0x0000060b
683 
684 #define REG_AXXX_CP_ME_CF_EVENT_DATA				0x0000060c
685 
686 #define REG_AXXX_CP_ME_NRT_ADDR					0x0000060d
687 
688 #define REG_AXXX_CP_ME_NRT_DATA					0x0000060e
689 
690 #define REG_AXXX_CP_ME_VS_FETCH_DONE_SRC			0x00000612
691 
692 #define REG_AXXX_CP_ME_VS_FETCH_DONE_ADDR			0x00000613
693 
694 #define REG_AXXX_CP_ME_VS_FETCH_DONE_DATA			0x00000614
695 
696 
697 #endif /* ADRENO_COMMON_XML */
698