1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. */
3 
4 #ifndef _A6XX_CRASH_DUMP_H_
5 #define _A6XX_CRASH_DUMP_H_
6 
7 #include "a6xx.xml.h"
8 
9 #define A6XX_NUM_CONTEXTS 2
10 #define A6XX_NUM_SHADER_BANKS 3
11 
12 static const u32 a6xx_gras_cluster[] = {
13 	0x8000, 0x8006, 0x8010, 0x8092, 0x8094, 0x809d, 0x80a0, 0x80a6,
14 	0x80af, 0x80f1, 0x8100, 0x8107, 0x8109, 0x8109, 0x8110, 0x8110,
15 	0x8400, 0x840b,
16 };
17 
18 static const u32 a6xx_ps_cluster_rac[] = {
19 	0x8800, 0x8806, 0x8809, 0x8811, 0x8818, 0x881e, 0x8820, 0x8865,
20 	0x8870, 0x8879, 0x8880, 0x8889, 0x8890, 0x8891, 0x8898, 0x8898,
21 	0x88c0, 0x88c1, 0x88d0, 0x88e3, 0x8900, 0x890c, 0x890f, 0x891a,
22 	0x8c00, 0x8c01, 0x8c08, 0x8c10, 0x8c17, 0x8c1f, 0x8c26, 0x8c33,
23 };
24 
25 static const u32 a6xx_ps_cluster_rbp[] = {
26 	0x88f0, 0x88f3, 0x890d, 0x890e, 0x8927, 0x8928, 0x8bf0, 0x8bf1,
27 	0x8c02, 0x8c07, 0x8c11, 0x8c16, 0x8c20, 0x8c25,
28 };
29 
30 static const u32 a6xx_ps_cluster[] = {
31 	0x9200, 0x9216, 0x9218, 0x9236, 0x9300, 0x9306,
32 };
33 
34 static const u32 a6xx_fe_cluster[] = {
35 	0x9300, 0x9306, 0x9800, 0x9806, 0x9b00, 0x9b07, 0xa000, 0xa009,
36 	0xa00e, 0xa0ef, 0xa0f8, 0xa0f8,
37 };
38 
39 static const u32 a6xx_pc_vs_cluster[] = {
40 	0x9100, 0x9108, 0x9300, 0x9306, 0x9980, 0x9981, 0x9b00, 0x9b07,
41 };
42 
43 #define CLUSTER_FE    0
44 #define CLUSTER_SP_VS 1
45 #define CLUSTER_PC_VS 2
46 #define CLUSTER_GRAS  3
47 #define CLUSTER_SP_PS 4
48 #define CLUSTER_PS    5
49 
50 #define CLUSTER(_id, _reg, _sel_reg, _sel_val) \
51 	{ .id = _id, .name = #_id,\
52 		.registers = _reg, \
53 		.count = ARRAY_SIZE(_reg), \
54 		.sel_reg = _sel_reg, .sel_val = _sel_val }
55 
56 static const struct a6xx_cluster {
57 	u32 id;
58 	const char *name;
59 	const u32 *registers;
60 	size_t count;
61 	u32 sel_reg;
62 	u32 sel_val;
63 } a6xx_clusters[] = {
64 	CLUSTER(CLUSTER_GRAS, a6xx_gras_cluster, 0, 0),
65 	CLUSTER(CLUSTER_PS, a6xx_ps_cluster_rac, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 0x0),
66 	CLUSTER(CLUSTER_PS, a6xx_ps_cluster_rbp, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 0x9),
67 	CLUSTER(CLUSTER_PS, a6xx_ps_cluster, 0, 0),
68 	CLUSTER(CLUSTER_FE, a6xx_fe_cluster, 0, 0),
69 	CLUSTER(CLUSTER_PC_VS, a6xx_pc_vs_cluster, 0, 0),
70 };
71 
72 static const u32 a6xx_sp_vs_hlsq_cluster[] = {
73 	0xb800, 0xb803, 0xb820, 0xb822,
74 };
75 
76 static const u32 a6xx_sp_vs_sp_cluster[] = {
77 	0xa800, 0xa824, 0xa830, 0xa83c, 0xa840, 0xa864, 0xa870, 0xa895,
78 	0xa8a0, 0xa8af, 0xa8c0, 0xa8c3,
79 };
80 
81 static const u32 a6xx_hlsq_duplicate_cluster[] = {
82 	0xbb10, 0xbb11, 0xbb20, 0xbb29,
83 };
84 
85 static const u32 a6xx_hlsq_2d_duplicate_cluster[] = {
86 	0xbd80, 0xbd80,
87 };
88 
89 static const u32 a6xx_sp_duplicate_cluster[] = {
90 	0xab00, 0xab00, 0xab04, 0xab05, 0xab10, 0xab1b, 0xab20, 0xab20,
91 };
92 
93 static const u32 a6xx_tp_duplicate_cluster[] = {
94 	0xb300, 0xb307, 0xb309, 0xb309, 0xb380, 0xb382,
95 };
96 
97 static const u32 a6xx_sp_ps_hlsq_cluster[] = {
98 	0xb980, 0xb980, 0xb982, 0xb987, 0xb990, 0xb99b, 0xb9a0, 0xb9a2,
99 	0xb9c0, 0xb9c9,
100 };
101 
102 static const u32 a6xx_sp_ps_hlsq_2d_cluster[] = {
103 	0xbd80, 0xbd80,
104 };
105 
106 static const u32 a6xx_sp_ps_sp_cluster[] = {
107 	0xa980, 0xa9a8, 0xa9b0, 0xa9bc, 0xa9d0, 0xa9d3, 0xa9e0, 0xa9f3,
108 	0xaa00, 0xaa00, 0xaa30, 0xaa31,
109 };
110 
111 static const u32 a6xx_sp_ps_sp_2d_cluster[] = {
112 	0xacc0, 0xacc0,
113 };
114 
115 static const u32 a6xx_sp_ps_tp_cluster[] = {
116 	0xb180, 0xb183, 0xb190, 0xb191,
117 };
118 
119 static const u32 a6xx_sp_ps_tp_2d_cluster[] = {
120 	0xb4c0, 0xb4d1,
121 };
122 
123 #define CLUSTER_DBGAHB(_id, _base, _type, _reg) \
124 	{ .name = #_id, .statetype = _type, .base = _base, \
125 		.registers = _reg, .count = ARRAY_SIZE(_reg) }
126 
127 static const struct a6xx_dbgahb_cluster {
128 	const char *name;
129 	u32 statetype;
130 	u32 base;
131 	const u32 *registers;
132 	size_t count;
133 } a6xx_dbgahb_clusters[] = {
134 	CLUSTER_DBGAHB(CLUSTER_SP_VS, 0x0002e000, 0x41, a6xx_sp_vs_hlsq_cluster),
135 	CLUSTER_DBGAHB(CLUSTER_SP_VS, 0x0002a000, 0x21, a6xx_sp_vs_sp_cluster),
136 	CLUSTER_DBGAHB(CLUSTER_SP_VS, 0x0002e000, 0x41, a6xx_hlsq_duplicate_cluster),
137 	CLUSTER_DBGAHB(CLUSTER_SP_VS, 0x0002f000, 0x45, a6xx_hlsq_2d_duplicate_cluster),
138 	CLUSTER_DBGAHB(CLUSTER_SP_VS, 0x0002a000, 0x21, a6xx_sp_duplicate_cluster),
139 	CLUSTER_DBGAHB(CLUSTER_SP_VS, 0x0002c000, 0x1, a6xx_tp_duplicate_cluster),
140 	CLUSTER_DBGAHB(CLUSTER_SP_PS, 0x0002e000, 0x42, a6xx_sp_ps_hlsq_cluster),
141 	CLUSTER_DBGAHB(CLUSTER_SP_PS, 0x0002f000, 0x46, a6xx_sp_ps_hlsq_2d_cluster),
142 	CLUSTER_DBGAHB(CLUSTER_SP_PS, 0x0002a000, 0x22, a6xx_sp_ps_sp_cluster),
143 	CLUSTER_DBGAHB(CLUSTER_SP_PS, 0x0002b000, 0x26, a6xx_sp_ps_sp_2d_cluster),
144 	CLUSTER_DBGAHB(CLUSTER_SP_PS, 0x0002c000, 0x2, a6xx_sp_ps_tp_cluster),
145 	CLUSTER_DBGAHB(CLUSTER_SP_PS, 0x0002d000, 0x6, a6xx_sp_ps_tp_2d_cluster),
146 	CLUSTER_DBGAHB(CLUSTER_SP_PS, 0x0002e000, 0x42, a6xx_hlsq_duplicate_cluster),
147 	CLUSTER_DBGAHB(CLUSTER_SP_PS, 0x0002a000, 0x22, a6xx_sp_duplicate_cluster),
148 	CLUSTER_DBGAHB(CLUSTER_SP_PS, 0x0002c000, 0x2, a6xx_tp_duplicate_cluster),
149 };
150 
151 static const u32 a6xx_hlsq_registers[] = {
152 	0xbe00, 0xbe01, 0xbe04, 0xbe05, 0xbe08, 0xbe09, 0xbe10, 0xbe15,
153 	0xbe20, 0xbe23,
154 };
155 
156 static const u32 a6xx_sp_registers[] = {
157 	0xae00, 0xae04, 0xae0c, 0xae0c, 0xae0f, 0xae2b, 0xae30, 0xae32,
158 	0xae35, 0xae35, 0xae3a, 0xae3f, 0xae50, 0xae52,
159 };
160 
161 static const u32 a6xx_tp_registers[] = {
162 	0xb600, 0xb601, 0xb604, 0xb605, 0xb610, 0xb61b, 0xb620, 0xb623,
163 };
164 
165 struct a6xx_registers {
166 	const u32 *registers;
167 	size_t count;
168 	u32 val0;
169 	u32 val1;
170 };
171 
172 #define HLSQ_DBG_REGS(_base, _type, _array) \
173 	{ .val0 = _base, .val1 = _type, .registers = _array, \
174 		.count = ARRAY_SIZE(_array), }
175 
176 static const struct a6xx_registers a6xx_hlsq_reglist[] = {
177 	HLSQ_DBG_REGS(0x0002F800, 0x40, a6xx_hlsq_registers),
178 	HLSQ_DBG_REGS(0x0002B800, 0x20, a6xx_sp_registers),
179 	HLSQ_DBG_REGS(0x0002D800, 0x0, a6xx_tp_registers),
180 };
181 
182 #define SHADER(_type, _size) \
183 	{ .type = _type, .name = #_type, .size = _size }
184 
185 static const struct a6xx_shader_block {
186 	const char *name;
187 	u32 type;
188 	u32 size;
189 } a6xx_shader_blocks[] = {
190 	SHADER(A6XX_TP0_TMO_DATA, 0x200),
191 	SHADER(A6XX_TP0_SMO_DATA, 0x80),
192 	SHADER(A6XX_TP0_MIPMAP_BASE_DATA, 0x3c0),
193 	SHADER(A6XX_TP1_TMO_DATA, 0x200),
194 	SHADER(A6XX_TP1_SMO_DATA, 0x80),
195 	SHADER(A6XX_TP1_MIPMAP_BASE_DATA, 0x3c0),
196 	SHADER(A6XX_SP_INST_DATA, 0x800),
197 	SHADER(A6XX_SP_LB_0_DATA, 0x800),
198 	SHADER(A6XX_SP_LB_1_DATA, 0x800),
199 	SHADER(A6XX_SP_LB_2_DATA, 0x800),
200 	SHADER(A6XX_SP_LB_3_DATA, 0x800),
201 	SHADER(A6XX_SP_LB_4_DATA, 0x800),
202 	SHADER(A6XX_SP_LB_5_DATA, 0x200),
203 	SHADER(A6XX_SP_CB_BINDLESS_DATA, 0x2000),
204 	SHADER(A6XX_SP_CB_LEGACY_DATA, 0x280),
205 	SHADER(A6XX_SP_UAV_DATA, 0x80),
206 	SHADER(A6XX_SP_INST_TAG, 0x80),
207 	SHADER(A6XX_SP_CB_BINDLESS_TAG, 0x80),
208 	SHADER(A6XX_SP_TMO_UMO_TAG, 0x80),
209 	SHADER(A6XX_SP_SMO_TAG, 0x80),
210 	SHADER(A6XX_SP_STATE_DATA, 0x3f),
211 	SHADER(A6XX_HLSQ_CHUNK_CVS_RAM, 0x1c0),
212 	SHADER(A6XX_HLSQ_CHUNK_CPS_RAM, 0x280),
213 	SHADER(A6XX_HLSQ_CHUNK_CVS_RAM_TAG, 0x40),
214 	SHADER(A6XX_HLSQ_CHUNK_CPS_RAM_TAG, 0x40),
215 	SHADER(A6XX_HLSQ_ICB_CVS_CB_BASE_TAG, 0x4),
216 	SHADER(A6XX_HLSQ_ICB_CPS_CB_BASE_TAG, 0x4),
217 	SHADER(A6XX_HLSQ_CVS_MISC_RAM, 0x1c0),
218 	SHADER(A6XX_HLSQ_CPS_MISC_RAM, 0x580),
219 	SHADER(A6XX_HLSQ_INST_RAM, 0x800),
220 	SHADER(A6XX_HLSQ_GFX_CVS_CONST_RAM, 0x800),
221 	SHADER(A6XX_HLSQ_GFX_CPS_CONST_RAM, 0x800),
222 	SHADER(A6XX_HLSQ_CVS_MISC_RAM_TAG, 0x8),
223 	SHADER(A6XX_HLSQ_CPS_MISC_RAM_TAG, 0x4),
224 	SHADER(A6XX_HLSQ_INST_RAM_TAG, 0x80),
225 	SHADER(A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG, 0xc),
226 	SHADER(A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG, 0x10),
227 	SHADER(A6XX_HLSQ_PWR_REST_RAM, 0x28),
228 	SHADER(A6XX_HLSQ_PWR_REST_TAG, 0x14),
229 	SHADER(A6XX_HLSQ_DATAPATH_META, 0x40),
230 	SHADER(A6XX_HLSQ_FRONTEND_META, 0x40),
231 	SHADER(A6XX_HLSQ_INDIRECT_META, 0x40),
232 };
233 
234 static const u32 a6xx_rb_rac_registers[] = {
235 	0x8e04, 0x8e05, 0x8e07, 0x8e08, 0x8e10, 0x8e1c, 0x8e20, 0x8e25,
236 	0x8e28, 0x8e28, 0x8e2c, 0x8e2f, 0x8e50, 0x8e52,
237 };
238 
239 static const u32 a6xx_rb_rbp_registers[] = {
240 	0x8e01, 0x8e01, 0x8e0c, 0x8e0c, 0x8e3b, 0x8e3e, 0x8e40, 0x8e43,
241 	0x8e53, 0x8e5f, 0x8e70, 0x8e77,
242 };
243 
244 static const u32 a6xx_registers[] = {
245 	/* RBBM */
246 	0x0000, 0x0002, 0x0010, 0x0010, 0x0012, 0x0012, 0x0018, 0x001b,
247 	0x001e, 0x0032, 0x0038, 0x003c, 0x0042, 0x0042, 0x0044, 0x0044,
248 	0x0047, 0x0047, 0x0056, 0x0056, 0x00ad, 0x00ae, 0x00b0, 0x00fb,
249 	0x0100, 0x011d, 0x0200, 0x020d, 0x0218, 0x023d, 0x0400, 0x04f9,
250 	0x0500, 0x0500, 0x0505, 0x050b, 0x050e, 0x0511, 0x0533, 0x0533,
251 	0x0540, 0x0555,
252 	/* CP */
253 	0x0800, 0x0808, 0x0810, 0x0813, 0x0820, 0x0821, 0x0823, 0x0824,
254 	0x0826, 0x0827, 0x0830, 0x0833, 0x0840, 0x0843, 0x084f, 0x086f,
255 	0x0880, 0x088a, 0x08a0, 0x08ab, 0x08c0, 0x08c4, 0x08d0, 0x08dd,
256 	0x08f0, 0x08f3, 0x0900, 0x0903, 0x0908, 0x0911, 0x0928, 0x093e,
257 	0x0942, 0x094d, 0x0980, 0x0984, 0x098d, 0x0996, 0x0998, 0x099e,
258 	0x09a0, 0x09a6, 0x09a8, 0x09ae, 0x09b0, 0x09b1, 0x09c2, 0x09c8,
259 	0x0a00, 0x0a03,
260 	/* VSC */
261 	0x0c00, 0x0c04, 0x0c06, 0x0c06, 0x0c10, 0x0cd9, 0x0e00, 0x0e0e,
262 	/* UCHE */
263 	0x0e10, 0x0e13, 0x0e17, 0x0e19, 0x0e1c, 0x0e2b, 0x0e30, 0x0e32,
264 	0x0e38, 0x0e39,
265 	/* GRAS */
266 	0x8600, 0x8601, 0x8610, 0x861b, 0x8620, 0x8620, 0x8628, 0x862b,
267 	0x8630, 0x8637,
268 	/* VPC */
269 	0x9600, 0x9604, 0x9624, 0x9637,
270 	/* PC */
271 	0x9e00, 0x9e01, 0x9e03, 0x9e0e, 0x9e11, 0x9e16, 0x9e19, 0x9e19,
272 	0x9e1c, 0x9e1c, 0x9e20, 0x9e23, 0x9e30, 0x9e31, 0x9e34, 0x9e34,
273 	0x9e70, 0x9e72, 0x9e78, 0x9e79, 0x9e80, 0x9fff,
274 	/* VFD */
275 	0xa600, 0xa601, 0xa603, 0xa603, 0xa60a, 0xa60a, 0xa610, 0xa617,
276 	0xa630, 0xa630,
277 };
278 
279 #define REGS(_array, _sel_reg, _sel_val) \
280 	{ .registers = _array, .count = ARRAY_SIZE(_array), \
281 		.val0 = _sel_reg, .val1 = _sel_val }
282 
283 static const struct a6xx_registers a6xx_reglist[] = {
284 	REGS(a6xx_registers, 0, 0),
285 	REGS(a6xx_rb_rac_registers, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 0),
286 	REGS(a6xx_rb_rbp_registers, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 9),
287 };
288 
289 static const u32 a6xx_ahb_registers[] = {
290 	/* RBBM_STATUS - RBBM_STATUS3 */
291 	0x210, 0x213,
292 	/* CP_STATUS_1 */
293 	0x825, 0x825,
294 };
295 
296 static const u32 a6xx_vbif_registers[] = {
297 	0x3000, 0x3007, 0x300c, 0x3014, 0x3018, 0x302d, 0x3030, 0x3031,
298 	0x3034, 0x3036, 0x303c, 0x303d, 0x3040, 0x3040, 0x3042, 0x3042,
299 	0x3049, 0x3049, 0x3058, 0x3058, 0x305a, 0x3061, 0x3064, 0x3068,
300 	0x306c, 0x306d, 0x3080, 0x3088, 0x308b, 0x308c, 0x3090, 0x3094,
301 	0x3098, 0x3098, 0x309c, 0x309c, 0x30c0, 0x30c0, 0x30c8, 0x30c8,
302 	0x30d0, 0x30d0, 0x30d8, 0x30d8, 0x30e0, 0x30e0, 0x3100, 0x3100,
303 	0x3108, 0x3108, 0x3110, 0x3110, 0x3118, 0x3118, 0x3120, 0x3120,
304 	0x3124, 0x3125, 0x3129, 0x3129, 0x3131, 0x3131, 0x3154, 0x3154,
305 	0x3156, 0x3156, 0x3158, 0x3158, 0x315a, 0x315a, 0x315c, 0x315c,
306 	0x315e, 0x315e, 0x3160, 0x3160, 0x3162, 0x3162, 0x340c, 0x340c,
307 	0x3410, 0x3410, 0x3800, 0x3801,
308 };
309 
310 static const u32 a6xx_gbif_registers[] = {
311 	0x3C00, 0X3C0B, 0X3C40, 0X3C47, 0X3CC0, 0X3CD1, 0xE3A, 0xE3A,
312 };
313 
314 static const struct a6xx_registers a6xx_ahb_reglist[] = {
315 	REGS(a6xx_ahb_registers, 0, 0),
316 };
317 
318 static const struct a6xx_registers a6xx_vbif_reglist =
319 			REGS(a6xx_vbif_registers, 0, 0);
320 
321 static const struct a6xx_registers a6xx_gbif_reglist =
322 			REGS(a6xx_gbif_registers, 0, 0);
323 
324 static const u32 a6xx_gmu_gx_registers[] = {
325 	/* GMU GX */
326 	0x0000, 0x0000, 0x0010, 0x0013, 0x0016, 0x0016, 0x0018, 0x001b,
327 	0x001e, 0x001e, 0x0020, 0x0023, 0x0026, 0x0026, 0x0028, 0x002b,
328 	0x002e, 0x002e, 0x0030, 0x0033, 0x0036, 0x0036, 0x0038, 0x003b,
329 	0x003e, 0x003e, 0x0040, 0x0043, 0x0046, 0x0046, 0x0080, 0x0084,
330 	0x0100, 0x012b, 0x0140, 0x0140,
331 };
332 
333 static const u32 a6xx_gmu_cx_registers[] = {
334 	/* GMU CX */
335 	0x4c00, 0x4c07, 0x4c10, 0x4c12, 0x4d00, 0x4d00, 0x4d07, 0x4d0a,
336 	0x5000, 0x5004, 0x5007, 0x5008, 0x500b, 0x500c, 0x500f, 0x501c,
337 	0x5024, 0x502a, 0x502d, 0x5030, 0x5040, 0x5053, 0x5087, 0x5089,
338 	0x50a0, 0x50a2, 0x50a4, 0x50af, 0x50c0, 0x50c3, 0x50d0, 0x50d0,
339 	0x50e4, 0x50e4, 0x50e8, 0x50ec, 0x5100, 0x5103, 0x5140, 0x5140,
340 	0x5142, 0x5144, 0x514c, 0x514d, 0x514f, 0x5151, 0x5154, 0x5154,
341 	0x5157, 0x5158, 0x515d, 0x515d, 0x5162, 0x5162, 0x5164, 0x5165,
342 	0x5180, 0x5186, 0x5190, 0x519e, 0x51c0, 0x51c0, 0x51c5, 0x51cc,
343 	0x51e0, 0x51e2, 0x51f0, 0x51f0, 0x5200, 0x5201,
344 	/* GMU AO */
345 	0x9300, 0x9316, 0x9400, 0x9400,
346 	/* GPU CC */
347 	0x9800, 0x9812, 0x9840, 0x9852, 0x9c00, 0x9c04, 0x9c07, 0x9c0b,
348 	0x9c15, 0x9c1c, 0x9c1e, 0x9c2d, 0x9c3c, 0x9c3d, 0x9c3f, 0x9c40,
349 	0x9c42, 0x9c49, 0x9c58, 0x9c5a, 0x9d40, 0x9d5e, 0xa000, 0xa002,
350 	0xa400, 0xa402, 0xac00, 0xac02, 0xb000, 0xb002, 0xb400, 0xb402,
351 	0xb800, 0xb802,
352 	/* GPU CC ACD */
353 	0xbc00, 0xbc16, 0xbc20, 0xbc27,
354 };
355 
356 static const u32 a6xx_gmu_cx_rscc_registers[] = {
357 	/* GPU RSCC */
358 	0x008c, 0x008c, 0x0101, 0x0102, 0x0340, 0x0342, 0x0344, 0x0347,
359 	0x034c, 0x0387, 0x03ec, 0x03ef, 0x03f4, 0x042f, 0x0494, 0x0497,
360 	0x049c, 0x04d7, 0x053c, 0x053f, 0x0544, 0x057f,
361 };
362 
363 static const struct a6xx_registers a6xx_gmu_reglist[] = {
364 	REGS(a6xx_gmu_cx_registers, 0, 0),
365 	REGS(a6xx_gmu_cx_rscc_registers, 0, 0),
366 	REGS(a6xx_gmu_gx_registers, 0, 0),
367 };
368 
369 static const struct a6xx_indexed_registers {
370 	const char *name;
371 	u32 addr;
372 	u32 data;
373 	u32 count;
374 } a6xx_indexed_reglist[] = {
375 	{ "CP_SEQ_STAT", REG_A6XX_CP_SQE_STAT_ADDR,
376 		REG_A6XX_CP_SQE_STAT_DATA, 0x33 },
377 	{ "CP_DRAW_STATE", REG_A6XX_CP_DRAW_STATE_ADDR,
378 		REG_A6XX_CP_DRAW_STATE_DATA, 0x100 },
379 	{ "CP_UCODE_DBG_DATA", REG_A6XX_CP_SQE_UCODE_DBG_ADDR,
380 		REG_A6XX_CP_SQE_UCODE_DBG_DATA, 0x6000 },
381 	{ "CP_ROQ", REG_A6XX_CP_ROQ_DBG_ADDR,
382 		REG_A6XX_CP_ROQ_DBG_DATA, 0x400 },
383 };
384 
385 static const struct a6xx_indexed_registers a6xx_cp_mempool_indexed = {
386 	"CP_MEMPOOL", REG_A6XX_CP_MEM_POOL_DBG_ADDR,
387 		REG_A6XX_CP_MEM_POOL_DBG_DATA, 0x2060,
388 };
389 
390 #define DEBUGBUS(_id, _count) { .id = _id, .name = #_id, .count = _count }
391 
392 static const struct a6xx_debugbus_block {
393 	const char *name;
394 	u32 id;
395 	u32 count;
396 } a6xx_debugbus_blocks[] = {
397 	DEBUGBUS(A6XX_DBGBUS_CP, 0x100),
398 	DEBUGBUS(A6XX_DBGBUS_RBBM, 0x100),
399 	DEBUGBUS(A6XX_DBGBUS_HLSQ, 0x100),
400 	DEBUGBUS(A6XX_DBGBUS_UCHE, 0x100),
401 	DEBUGBUS(A6XX_DBGBUS_DPM, 0x100),
402 	DEBUGBUS(A6XX_DBGBUS_TESS, 0x100),
403 	DEBUGBUS(A6XX_DBGBUS_PC, 0x100),
404 	DEBUGBUS(A6XX_DBGBUS_VFDP, 0x100),
405 	DEBUGBUS(A6XX_DBGBUS_VPC, 0x100),
406 	DEBUGBUS(A6XX_DBGBUS_TSE, 0x100),
407 	DEBUGBUS(A6XX_DBGBUS_RAS, 0x100),
408 	DEBUGBUS(A6XX_DBGBUS_VSC, 0x100),
409 	DEBUGBUS(A6XX_DBGBUS_COM, 0x100),
410 	DEBUGBUS(A6XX_DBGBUS_LRZ, 0x100),
411 	DEBUGBUS(A6XX_DBGBUS_A2D, 0x100),
412 	DEBUGBUS(A6XX_DBGBUS_CCUFCHE, 0x100),
413 	DEBUGBUS(A6XX_DBGBUS_RBP, 0x100),
414 	DEBUGBUS(A6XX_DBGBUS_DCS, 0x100),
415 	DEBUGBUS(A6XX_DBGBUS_DBGC, 0x100),
416 	DEBUGBUS(A6XX_DBGBUS_GMU_GX, 0x100),
417 	DEBUGBUS(A6XX_DBGBUS_TPFCHE, 0x100),
418 	DEBUGBUS(A6XX_DBGBUS_GPC, 0x100),
419 	DEBUGBUS(A6XX_DBGBUS_LARC, 0x100),
420 	DEBUGBUS(A6XX_DBGBUS_HLSQ_SPTP, 0x100),
421 	DEBUGBUS(A6XX_DBGBUS_RB_0, 0x100),
422 	DEBUGBUS(A6XX_DBGBUS_RB_1, 0x100),
423 	DEBUGBUS(A6XX_DBGBUS_UCHE_WRAPPER, 0x100),
424 	DEBUGBUS(A6XX_DBGBUS_CCU_0, 0x100),
425 	DEBUGBUS(A6XX_DBGBUS_CCU_1, 0x100),
426 	DEBUGBUS(A6XX_DBGBUS_VFD_0, 0x100),
427 	DEBUGBUS(A6XX_DBGBUS_VFD_1, 0x100),
428 	DEBUGBUS(A6XX_DBGBUS_VFD_2, 0x100),
429 	DEBUGBUS(A6XX_DBGBUS_VFD_3, 0x100),
430 	DEBUGBUS(A6XX_DBGBUS_SP_0, 0x100),
431 	DEBUGBUS(A6XX_DBGBUS_SP_1, 0x100),
432 	DEBUGBUS(A6XX_DBGBUS_TPL1_0, 0x100),
433 	DEBUGBUS(A6XX_DBGBUS_TPL1_1, 0x100),
434 	DEBUGBUS(A6XX_DBGBUS_TPL1_2, 0x100),
435 	DEBUGBUS(A6XX_DBGBUS_TPL1_3, 0x100),
436 };
437 
438 static const struct a6xx_debugbus_block a6xx_gbif_debugbus_block =
439 			DEBUGBUS(A6XX_DBGBUS_VBIF, 0x100);
440 
441 static const struct a6xx_debugbus_block a6xx_cx_debugbus_blocks[] = {
442 	DEBUGBUS(A6XX_DBGBUS_GMU_CX, 0x100),
443 	DEBUGBUS(A6XX_DBGBUS_CX, 0x100),
444 };
445 
446 #endif
447