1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2017, 2019 The Linux Foundation. All rights reserved. */ 3 4 #ifndef __A6XX_GPU_H__ 5 #define __A6XX_GPU_H__ 6 7 8 #include "adreno_gpu.h" 9 #include "a6xx.xml.h" 10 11 #include "a6xx_gmu.h" 12 13 extern bool hang_debug; 14 15 struct a6xx_gpu { 16 struct adreno_gpu base; 17 18 struct drm_gem_object *sqe_bo; 19 uint64_t sqe_iova; 20 21 struct msm_ringbuffer *cur_ring; 22 struct msm_file_private *cur_ctx; 23 24 struct a6xx_gmu gmu; 25 }; 26 27 #define to_a6xx_gpu(x) container_of(x, struct a6xx_gpu, base) 28 29 /* 30 * Given a register and a count, return a value to program into 31 * REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len 32 * registers starting at _reg. 33 */ 34 #define A6XX_PROTECT_RW(_reg, _len) \ 35 ((1 << 31) | \ 36 (((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF)) 37 38 /* 39 * Same as above, but allow reads over the range. For areas of mixed use (such 40 * as performance counters) this allows us to protect a much larger range with a 41 * single register 42 */ 43 #define A6XX_PROTECT_RDONLY(_reg, _len) \ 44 ((((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF)) 45 46 static inline bool a6xx_has_gbif(struct adreno_gpu *gpu) 47 { 48 if(adreno_is_a630(gpu)) 49 return false; 50 51 return true; 52 } 53 54 int a6xx_gmu_resume(struct a6xx_gpu *gpu); 55 int a6xx_gmu_stop(struct a6xx_gpu *gpu); 56 57 int a6xx_gmu_wait_for_idle(struct a6xx_gmu *gmu); 58 59 bool a6xx_gmu_isidle(struct a6xx_gmu *gmu); 60 61 int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state); 62 void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state); 63 64 int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node); 65 void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu); 66 67 void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp); 68 unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu); 69 70 void a6xx_show(struct msm_gpu *gpu, struct msm_gpu_state *state, 71 struct drm_printer *p); 72 73 struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu); 74 int a6xx_gpu_state_put(struct msm_gpu_state *state); 75 76 #endif /* __A6XX_GPU_H__ */ 77