1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2017, 2019 The Linux Foundation. All rights reserved. */ 3 4 #ifndef __A6XX_GPU_H__ 5 #define __A6XX_GPU_H__ 6 7 8 #include "adreno_gpu.h" 9 #include "a6xx.xml.h" 10 11 #include "a6xx_gmu.h" 12 13 extern bool hang_debug; 14 15 struct a6xx_gpu { 16 struct adreno_gpu base; 17 18 struct drm_gem_object *sqe_bo; 19 uint64_t sqe_iova; 20 21 struct msm_ringbuffer *cur_ring; 22 23 struct a6xx_gmu gmu; 24 25 struct drm_gem_object *shadow_bo; 26 uint64_t shadow_iova; 27 uint32_t *shadow; 28 29 bool has_whereami; 30 31 void __iomem *llc_mmio; 32 void *llc_slice; 33 void *htw_llc_slice; 34 bool have_mmu500; 35 }; 36 37 #define to_a6xx_gpu(x) container_of(x, struct a6xx_gpu, base) 38 39 /* 40 * Given a register and a count, return a value to program into 41 * REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len 42 * registers starting at _reg. 43 */ 44 #define A6XX_PROTECT_NORDWR(_reg, _len) \ 45 ((1 << 31) | \ 46 (((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF)) 47 48 /* 49 * Same as above, but allow reads over the range. For areas of mixed use (such 50 * as performance counters) this allows us to protect a much larger range with a 51 * single register 52 */ 53 #define A6XX_PROTECT_RDONLY(_reg, _len) \ 54 ((((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF)) 55 56 static inline bool a6xx_has_gbif(struct adreno_gpu *gpu) 57 { 58 if(adreno_is_a630(gpu)) 59 return false; 60 61 return true; 62 } 63 64 #define shadowptr(_a6xx_gpu, _ring) ((_a6xx_gpu)->shadow_iova + \ 65 ((_ring)->id * sizeof(uint32_t))) 66 67 int a6xx_gmu_resume(struct a6xx_gpu *gpu); 68 int a6xx_gmu_stop(struct a6xx_gpu *gpu); 69 70 int a6xx_gmu_wait_for_idle(struct a6xx_gmu *gmu); 71 72 bool a6xx_gmu_isidle(struct a6xx_gmu *gmu); 73 74 int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state); 75 void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state); 76 77 int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node); 78 void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu); 79 80 void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp); 81 unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu); 82 83 void a6xx_show(struct msm_gpu *gpu, struct msm_gpu_state *state, 84 struct drm_printer *p); 85 86 struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu); 87 int a6xx_gpu_state_put(struct msm_gpu_state *state); 88 89 #endif /* __A6XX_GPU_H__ */ 90