14b565ca5SJordan Crouse /* SPDX-License-Identifier: GPL-2.0 */ 2e812744cSSharat Masetty /* Copyright (c) 2017, 2019 The Linux Foundation. All rights reserved. */ 34b565ca5SJordan Crouse 44b565ca5SJordan Crouse #ifndef __A6XX_GPU_H__ 54b565ca5SJordan Crouse #define __A6XX_GPU_H__ 64b565ca5SJordan Crouse 74b565ca5SJordan Crouse 84b565ca5SJordan Crouse #include "adreno_gpu.h" 94b565ca5SJordan Crouse #include "a6xx.xml.h" 104b565ca5SJordan Crouse 114b565ca5SJordan Crouse #include "a6xx_gmu.h" 124b565ca5SJordan Crouse 134b565ca5SJordan Crouse extern bool hang_debug; 144b565ca5SJordan Crouse 154b565ca5SJordan Crouse struct a6xx_gpu { 164b565ca5SJordan Crouse struct adreno_gpu base; 174b565ca5SJordan Crouse 184b565ca5SJordan Crouse struct drm_gem_object *sqe_bo; 194b565ca5SJordan Crouse uint64_t sqe_iova; 204b565ca5SJordan Crouse 214b565ca5SJordan Crouse struct msm_ringbuffer *cur_ring; 2214eb0cb4SRob Clark 234b565ca5SJordan Crouse struct a6xx_gmu gmu; 24d3a569fcSJordan Crouse 25d3a569fcSJordan Crouse struct drm_gem_object *shadow_bo; 26d3a569fcSJordan Crouse uint64_t shadow_iova; 27d3a569fcSJordan Crouse uint32_t *shadow; 28d3a569fcSJordan Crouse 29d3a569fcSJordan Crouse bool has_whereami; 30474dadb8SSharat Masetty 31474dadb8SSharat Masetty void __iomem *llc_mmio; 32474dadb8SSharat Masetty void *llc_slice; 33474dadb8SSharat Masetty void *htw_llc_slice; 343d247123SJordan Crouse bool have_mmu500; 35f4a75b59SAkhil P Oommen bool hung; 364b565ca5SJordan Crouse }; 374b565ca5SJordan Crouse 384b565ca5SJordan Crouse #define to_a6xx_gpu(x) container_of(x, struct a6xx_gpu, base) 394b565ca5SJordan Crouse 404b565ca5SJordan Crouse /* 414b565ca5SJordan Crouse * Given a register and a count, return a value to program into 42*3bf84665SRob Clark * REG_CP_PROTECT_REG(n) - this will block both reads and writes for 43*3bf84665SRob Clark * _len + 1 registers starting at _reg. 444b565ca5SJordan Crouse */ 4540843403SJonathan Marek #define A6XX_PROTECT_NORDWR(_reg, _len) \ 464b565ca5SJordan Crouse ((1 << 31) | \ 474b565ca5SJordan Crouse (((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF)) 484b565ca5SJordan Crouse 494b565ca5SJordan Crouse /* 504b565ca5SJordan Crouse * Same as above, but allow reads over the range. For areas of mixed use (such 514b565ca5SJordan Crouse * as performance counters) this allows us to protect a much larger range with a 524b565ca5SJordan Crouse * single register 534b565ca5SJordan Crouse */ 544b565ca5SJordan Crouse #define A6XX_PROTECT_RDONLY(_reg, _len) \ 554b565ca5SJordan Crouse ((((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF)) 564b565ca5SJordan Crouse 57e812744cSSharat Masetty static inline bool a6xx_has_gbif(struct adreno_gpu *gpu) 58e812744cSSharat Masetty { 59e812744cSSharat Masetty if(adreno_is_a630(gpu)) 60e812744cSSharat Masetty return false; 61e812744cSSharat Masetty 62e812744cSSharat Masetty return true; 63e812744cSSharat Masetty } 644b565ca5SJordan Crouse 65d3a569fcSJordan Crouse #define shadowptr(_a6xx_gpu, _ring) ((_a6xx_gpu)->shadow_iova + \ 66d3a569fcSJordan Crouse ((_ring)->id * sizeof(uint32_t))) 67d3a569fcSJordan Crouse 684b565ca5SJordan Crouse int a6xx_gmu_resume(struct a6xx_gpu *gpu); 694b565ca5SJordan Crouse int a6xx_gmu_stop(struct a6xx_gpu *gpu); 704b565ca5SJordan Crouse 71e31fdb74SJordan Crouse int a6xx_gmu_wait_for_idle(struct a6xx_gmu *gmu); 724b565ca5SJordan Crouse 734b565ca5SJordan Crouse bool a6xx_gmu_isidle(struct a6xx_gmu *gmu); 744b565ca5SJordan Crouse 754b565ca5SJordan Crouse int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state); 764b565ca5SJordan Crouse void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state); 774b565ca5SJordan Crouse 78981f2aabSSean Paul int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node); 795a903a44SKonrad Dybcio int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node); 804b565ca5SJordan Crouse void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu); 811707add8SJordan Crouse 826694482aSDouglas Anderson void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp, 836694482aSDouglas Anderson bool suspended); 84a2c3c0a5SSharat Masetty unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu); 851707add8SJordan Crouse 861707add8SJordan Crouse void a6xx_show(struct msm_gpu *gpu, struct msm_gpu_state *state, 871707add8SJordan Crouse struct drm_printer *p); 881707add8SJordan Crouse 891707add8SJordan Crouse struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu); 901707add8SJordan Crouse int a6xx_gpu_state_put(struct msm_gpu_state *state); 911707add8SJordan Crouse 926e332c99SKonrad Dybcio void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu, bool gx_off); 93277b9678SKonrad Dybcio void a6xx_gpu_sw_reset(struct msm_gpu *gpu, bool assert); 946e332c99SKonrad Dybcio 954b565ca5SJordan Crouse #endif /* __A6XX_GPU_H__ */ 96