14b565ca5SJordan Crouse /* SPDX-License-Identifier: GPL-2.0 */ 24b565ca5SJordan Crouse /* Copyright (c) 2017 The Linux Foundation. All rights reserved. */ 34b565ca5SJordan Crouse 44b565ca5SJordan Crouse #ifndef __A6XX_GPU_H__ 54b565ca5SJordan Crouse #define __A6XX_GPU_H__ 64b565ca5SJordan Crouse 74b565ca5SJordan Crouse 84b565ca5SJordan Crouse #include "adreno_gpu.h" 94b565ca5SJordan Crouse #include "a6xx.xml.h" 104b565ca5SJordan Crouse 114b565ca5SJordan Crouse #include "a6xx_gmu.h" 124b565ca5SJordan Crouse 134b565ca5SJordan Crouse extern bool hang_debug; 144b565ca5SJordan Crouse 154b565ca5SJordan Crouse struct a6xx_gpu { 164b565ca5SJordan Crouse struct adreno_gpu base; 174b565ca5SJordan Crouse 184b565ca5SJordan Crouse struct drm_gem_object *sqe_bo; 194b565ca5SJordan Crouse uint64_t sqe_iova; 204b565ca5SJordan Crouse 214b565ca5SJordan Crouse struct msm_ringbuffer *cur_ring; 224b565ca5SJordan Crouse 234b565ca5SJordan Crouse struct a6xx_gmu gmu; 244b565ca5SJordan Crouse }; 254b565ca5SJordan Crouse 264b565ca5SJordan Crouse #define to_a6xx_gpu(x) container_of(x, struct a6xx_gpu, base) 274b565ca5SJordan Crouse 284b565ca5SJordan Crouse /* 294b565ca5SJordan Crouse * Given a register and a count, return a value to program into 304b565ca5SJordan Crouse * REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len 314b565ca5SJordan Crouse * registers starting at _reg. 324b565ca5SJordan Crouse */ 334b565ca5SJordan Crouse #define A6XX_PROTECT_RW(_reg, _len) \ 344b565ca5SJordan Crouse ((1 << 31) | \ 354b565ca5SJordan Crouse (((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF)) 364b565ca5SJordan Crouse 374b565ca5SJordan Crouse /* 384b565ca5SJordan Crouse * Same as above, but allow reads over the range. For areas of mixed use (such 394b565ca5SJordan Crouse * as performance counters) this allows us to protect a much larger range with a 404b565ca5SJordan Crouse * single register 414b565ca5SJordan Crouse */ 424b565ca5SJordan Crouse #define A6XX_PROTECT_RDONLY(_reg, _len) \ 434b565ca5SJordan Crouse ((((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF)) 444b565ca5SJordan Crouse 454b565ca5SJordan Crouse 464b565ca5SJordan Crouse int a6xx_gmu_resume(struct a6xx_gpu *gpu); 474b565ca5SJordan Crouse int a6xx_gmu_stop(struct a6xx_gpu *gpu); 484b565ca5SJordan Crouse 494b565ca5SJordan Crouse int a6xx_gmu_wait_for_idle(struct a6xx_gpu *gpu); 504b565ca5SJordan Crouse 514b565ca5SJordan Crouse int a6xx_gmu_reset(struct a6xx_gpu *a6xx_gpu); 524b565ca5SJordan Crouse bool a6xx_gmu_isidle(struct a6xx_gmu *gmu); 534b565ca5SJordan Crouse 544b565ca5SJordan Crouse int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state); 554b565ca5SJordan Crouse void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state); 564b565ca5SJordan Crouse 574b565ca5SJordan Crouse int a6xx_gmu_probe(struct a6xx_gpu *a6xx_gpu, struct device_node *node); 584b565ca5SJordan Crouse void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu); 591707add8SJordan Crouse 60a2c3c0a5SSharat Masetty void a6xx_gmu_set_freq(struct msm_gpu *gpu, unsigned long freq); 61a2c3c0a5SSharat Masetty unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu); 621707add8SJordan Crouse 631707add8SJordan Crouse void a6xx_show(struct msm_gpu *gpu, struct msm_gpu_state *state, 641707add8SJordan Crouse struct drm_printer *p); 651707add8SJordan Crouse 661707add8SJordan Crouse struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu); 671707add8SJordan Crouse int a6xx_gpu_state_put(struct msm_gpu_state *state); 681707add8SJordan Crouse 694b565ca5SJordan Crouse #endif /* __A6XX_GPU_H__ */ 70