14b565ca5SJordan Crouse /* SPDX-License-Identifier: GPL-2.0 */ 2e812744cSSharat Masetty /* Copyright (c) 2017, 2019 The Linux Foundation. All rights reserved. */ 34b565ca5SJordan Crouse 44b565ca5SJordan Crouse #ifndef __A6XX_GPU_H__ 54b565ca5SJordan Crouse #define __A6XX_GPU_H__ 64b565ca5SJordan Crouse 74b565ca5SJordan Crouse 84b565ca5SJordan Crouse #include "adreno_gpu.h" 94b565ca5SJordan Crouse #include "a6xx.xml.h" 104b565ca5SJordan Crouse 114b565ca5SJordan Crouse #include "a6xx_gmu.h" 124b565ca5SJordan Crouse 134b565ca5SJordan Crouse extern bool hang_debug; 144b565ca5SJordan Crouse 154b565ca5SJordan Crouse struct a6xx_gpu { 164b565ca5SJordan Crouse struct adreno_gpu base; 174b565ca5SJordan Crouse 184b565ca5SJordan Crouse struct drm_gem_object *sqe_bo; 194b565ca5SJordan Crouse uint64_t sqe_iova; 204b565ca5SJordan Crouse 214b565ca5SJordan Crouse struct msm_ringbuffer *cur_ring; 22*14eb0cb4SRob Clark 23*14eb0cb4SRob Clark /** 24*14eb0cb4SRob Clark * cur_ctx_seqno: 25*14eb0cb4SRob Clark * 26*14eb0cb4SRob Clark * The ctx->seqno value of the context with current pgtables 27*14eb0cb4SRob Clark * installed. Tracked by seqno rather than pointer value to 28*14eb0cb4SRob Clark * avoid dangling pointers, and cases where a ctx can be freed 29*14eb0cb4SRob Clark * and a new one created with the same address. 30*14eb0cb4SRob Clark */ 31*14eb0cb4SRob Clark int cur_ctx_seqno; 324b565ca5SJordan Crouse 334b565ca5SJordan Crouse struct a6xx_gmu gmu; 34d3a569fcSJordan Crouse 35d3a569fcSJordan Crouse struct drm_gem_object *shadow_bo; 36d3a569fcSJordan Crouse uint64_t shadow_iova; 37d3a569fcSJordan Crouse uint32_t *shadow; 38d3a569fcSJordan Crouse 39d3a569fcSJordan Crouse bool has_whereami; 40474dadb8SSharat Masetty 41474dadb8SSharat Masetty void __iomem *llc_mmio; 42474dadb8SSharat Masetty void *llc_slice; 43474dadb8SSharat Masetty void *htw_llc_slice; 443d247123SJordan Crouse bool have_mmu500; 454b565ca5SJordan Crouse }; 464b565ca5SJordan Crouse 474b565ca5SJordan Crouse #define to_a6xx_gpu(x) container_of(x, struct a6xx_gpu, base) 484b565ca5SJordan Crouse 494b565ca5SJordan Crouse /* 504b565ca5SJordan Crouse * Given a register and a count, return a value to program into 514b565ca5SJordan Crouse * REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len 524b565ca5SJordan Crouse * registers starting at _reg. 534b565ca5SJordan Crouse */ 5440843403SJonathan Marek #define A6XX_PROTECT_NORDWR(_reg, _len) \ 554b565ca5SJordan Crouse ((1 << 31) | \ 564b565ca5SJordan Crouse (((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF)) 574b565ca5SJordan Crouse 584b565ca5SJordan Crouse /* 594b565ca5SJordan Crouse * Same as above, but allow reads over the range. For areas of mixed use (such 604b565ca5SJordan Crouse * as performance counters) this allows us to protect a much larger range with a 614b565ca5SJordan Crouse * single register 624b565ca5SJordan Crouse */ 634b565ca5SJordan Crouse #define A6XX_PROTECT_RDONLY(_reg, _len) \ 644b565ca5SJordan Crouse ((((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF)) 654b565ca5SJordan Crouse 66e812744cSSharat Masetty static inline bool a6xx_has_gbif(struct adreno_gpu *gpu) 67e812744cSSharat Masetty { 68e812744cSSharat Masetty if(adreno_is_a630(gpu)) 69e812744cSSharat Masetty return false; 70e812744cSSharat Masetty 71e812744cSSharat Masetty return true; 72e812744cSSharat Masetty } 734b565ca5SJordan Crouse 74d3a569fcSJordan Crouse #define shadowptr(_a6xx_gpu, _ring) ((_a6xx_gpu)->shadow_iova + \ 75d3a569fcSJordan Crouse ((_ring)->id * sizeof(uint32_t))) 76d3a569fcSJordan Crouse 774b565ca5SJordan Crouse int a6xx_gmu_resume(struct a6xx_gpu *gpu); 784b565ca5SJordan Crouse int a6xx_gmu_stop(struct a6xx_gpu *gpu); 794b565ca5SJordan Crouse 80e31fdb74SJordan Crouse int a6xx_gmu_wait_for_idle(struct a6xx_gmu *gmu); 814b565ca5SJordan Crouse 824b565ca5SJordan Crouse bool a6xx_gmu_isidle(struct a6xx_gmu *gmu); 834b565ca5SJordan Crouse 844b565ca5SJordan Crouse int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state); 854b565ca5SJordan Crouse void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state); 864b565ca5SJordan Crouse 87981f2aabSSean Paul int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node); 884b565ca5SJordan Crouse void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu); 891707add8SJordan Crouse 901f60d114SSharat Masetty void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp); 91a2c3c0a5SSharat Masetty unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu); 921707add8SJordan Crouse 931707add8SJordan Crouse void a6xx_show(struct msm_gpu *gpu, struct msm_gpu_state *state, 941707add8SJordan Crouse struct drm_printer *p); 951707add8SJordan Crouse 961707add8SJordan Crouse struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu); 971707add8SJordan Crouse int a6xx_gpu_state_put(struct msm_gpu_state *state); 981707add8SJordan Crouse 994b565ca5SJordan Crouse #endif /* __A6XX_GPU_H__ */ 100