1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */ 3 4 5 #include "msm_gem.h" 6 #include "msm_mmu.h" 7 #include "msm_gpu_trace.h" 8 #include "a6xx_gpu.h" 9 #include "a6xx_gmu.xml.h" 10 11 #include <linux/bitfield.h> 12 #include <linux/devfreq.h> 13 #include <linux/nvmem-consumer.h> 14 #include <linux/soc/qcom/llcc-qcom.h> 15 16 #define GPU_PAS_ID 13 17 18 static inline bool _a6xx_check_idle(struct msm_gpu *gpu) 19 { 20 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 21 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 22 23 /* Check that the GMU is idle */ 24 if (!a6xx_gmu_isidle(&a6xx_gpu->gmu)) 25 return false; 26 27 /* Check tha the CX master is idle */ 28 if (gpu_read(gpu, REG_A6XX_RBBM_STATUS) & 29 ~A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER) 30 return false; 31 32 return !(gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS) & 33 A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT); 34 } 35 36 static bool a6xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 37 { 38 /* wait for CP to drain ringbuffer: */ 39 if (!adreno_idle(gpu, ring)) 40 return false; 41 42 if (spin_until(_a6xx_check_idle(gpu))) { 43 DRM_ERROR("%s: %ps: timeout waiting for GPU to idle: status %8.8X irq %8.8X rptr/wptr %d/%d\n", 44 gpu->name, __builtin_return_address(0), 45 gpu_read(gpu, REG_A6XX_RBBM_STATUS), 46 gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS), 47 gpu_read(gpu, REG_A6XX_CP_RB_RPTR), 48 gpu_read(gpu, REG_A6XX_CP_RB_WPTR)); 49 return false; 50 } 51 52 return true; 53 } 54 55 static void a6xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 56 { 57 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 58 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 59 uint32_t wptr; 60 unsigned long flags; 61 62 /* Expanded APRIV doesn't need to issue the WHERE_AM_I opcode */ 63 if (a6xx_gpu->has_whereami && !adreno_gpu->base.hw_apriv) { 64 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 65 66 OUT_PKT7(ring, CP_WHERE_AM_I, 2); 67 OUT_RING(ring, lower_32_bits(shadowptr(a6xx_gpu, ring))); 68 OUT_RING(ring, upper_32_bits(shadowptr(a6xx_gpu, ring))); 69 } 70 71 spin_lock_irqsave(&ring->preempt_lock, flags); 72 73 /* Copy the shadow to the actual register */ 74 ring->cur = ring->next; 75 76 /* Make sure to wrap wptr if we need to */ 77 wptr = get_wptr(ring); 78 79 spin_unlock_irqrestore(&ring->preempt_lock, flags); 80 81 /* Make sure everything is posted before making a decision */ 82 mb(); 83 84 gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr); 85 } 86 87 static void get_stats_counter(struct msm_ringbuffer *ring, u32 counter, 88 u64 iova) 89 { 90 OUT_PKT7(ring, CP_REG_TO_MEM, 3); 91 OUT_RING(ring, CP_REG_TO_MEM_0_REG(counter) | 92 CP_REG_TO_MEM_0_CNT(2) | 93 CP_REG_TO_MEM_0_64B); 94 OUT_RING(ring, lower_32_bits(iova)); 95 OUT_RING(ring, upper_32_bits(iova)); 96 } 97 98 static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu, 99 struct msm_ringbuffer *ring, struct msm_file_private *ctx) 100 { 101 phys_addr_t ttbr; 102 u32 asid; 103 u64 memptr = rbmemptr(ring, ttbr0); 104 105 if (ctx == a6xx_gpu->cur_ctx) 106 return; 107 108 if (msm_iommu_pagetable_params(ctx->aspace->mmu, &ttbr, &asid)) 109 return; 110 111 /* Execute the table update */ 112 OUT_PKT7(ring, CP_SMMU_TABLE_UPDATE, 4); 113 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(lower_32_bits(ttbr))); 114 115 OUT_RING(ring, 116 CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(upper_32_bits(ttbr)) | 117 CP_SMMU_TABLE_UPDATE_1_ASID(asid)); 118 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(0)); 119 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(0)); 120 121 /* 122 * Write the new TTBR0 to the memstore. This is good for debugging. 123 */ 124 OUT_PKT7(ring, CP_MEM_WRITE, 4); 125 OUT_RING(ring, CP_MEM_WRITE_0_ADDR_LO(lower_32_bits(memptr))); 126 OUT_RING(ring, CP_MEM_WRITE_1_ADDR_HI(upper_32_bits(memptr))); 127 OUT_RING(ring, lower_32_bits(ttbr)); 128 OUT_RING(ring, (asid << 16) | upper_32_bits(ttbr)); 129 130 /* 131 * And finally, trigger a uche flush to be sure there isn't anything 132 * lingering in that part of the GPU 133 */ 134 135 OUT_PKT7(ring, CP_EVENT_WRITE, 1); 136 OUT_RING(ring, 0x31); 137 138 a6xx_gpu->cur_ctx = ctx; 139 } 140 141 static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) 142 { 143 unsigned int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT; 144 struct msm_drm_private *priv = gpu->dev->dev_private; 145 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 146 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 147 struct msm_ringbuffer *ring = submit->ring; 148 unsigned int i; 149 150 a6xx_set_pagetable(a6xx_gpu, ring, submit->queue->ctx); 151 152 get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP_0_LO, 153 rbmemptr_stats(ring, index, cpcycles_start)); 154 155 /* 156 * For PM4 the GMU register offsets are calculated from the base of the 157 * GPU registers so we need to add 0x1a800 to the register value on A630 158 * to get the right value from PM4. 159 */ 160 get_stats_counter(ring, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L + 0x1a800, 161 rbmemptr_stats(ring, index, alwayson_start)); 162 163 /* Invalidate CCU depth and color */ 164 OUT_PKT7(ring, CP_EVENT_WRITE, 1); 165 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(PC_CCU_INVALIDATE_DEPTH)); 166 167 OUT_PKT7(ring, CP_EVENT_WRITE, 1); 168 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(PC_CCU_INVALIDATE_COLOR)); 169 170 /* Submit the commands */ 171 for (i = 0; i < submit->nr_cmds; i++) { 172 switch (submit->cmd[i].type) { 173 case MSM_SUBMIT_CMD_IB_TARGET_BUF: 174 break; 175 case MSM_SUBMIT_CMD_CTX_RESTORE_BUF: 176 if (priv->lastctx == submit->queue->ctx) 177 break; 178 fallthrough; 179 case MSM_SUBMIT_CMD_BUF: 180 OUT_PKT7(ring, CP_INDIRECT_BUFFER_PFE, 3); 181 OUT_RING(ring, lower_32_bits(submit->cmd[i].iova)); 182 OUT_RING(ring, upper_32_bits(submit->cmd[i].iova)); 183 OUT_RING(ring, submit->cmd[i].size); 184 break; 185 } 186 } 187 188 get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP_0_LO, 189 rbmemptr_stats(ring, index, cpcycles_end)); 190 get_stats_counter(ring, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L + 0x1a800, 191 rbmemptr_stats(ring, index, alwayson_end)); 192 193 /* Write the fence to the scratch register */ 194 OUT_PKT4(ring, REG_A6XX_CP_SCRATCH_REG(2), 1); 195 OUT_RING(ring, submit->seqno); 196 197 /* 198 * Execute a CACHE_FLUSH_TS event. This will ensure that the 199 * timestamp is written to the memory and then triggers the interrupt 200 */ 201 OUT_PKT7(ring, CP_EVENT_WRITE, 4); 202 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(CACHE_FLUSH_TS) | 203 CP_EVENT_WRITE_0_IRQ); 204 OUT_RING(ring, lower_32_bits(rbmemptr(ring, fence))); 205 OUT_RING(ring, upper_32_bits(rbmemptr(ring, fence))); 206 OUT_RING(ring, submit->seqno); 207 208 trace_msm_gpu_submit_flush(submit, 209 gmu_read64(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L, 210 REG_A6XX_GMU_ALWAYS_ON_COUNTER_H)); 211 212 a6xx_flush(gpu, ring); 213 } 214 215 const struct adreno_reglist a630_hwcg[] = { 216 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222}, 217 {REG_A6XX_RBBM_CLOCK_CNTL_SP1, 0x22222222}, 218 {REG_A6XX_RBBM_CLOCK_CNTL_SP2, 0x22222222}, 219 {REG_A6XX_RBBM_CLOCK_CNTL_SP3, 0x22222222}, 220 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02022220}, 221 {REG_A6XX_RBBM_CLOCK_CNTL2_SP1, 0x02022220}, 222 {REG_A6XX_RBBM_CLOCK_CNTL2_SP2, 0x02022220}, 223 {REG_A6XX_RBBM_CLOCK_CNTL2_SP3, 0x02022220}, 224 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, 225 {REG_A6XX_RBBM_CLOCK_DELAY_SP1, 0x00000080}, 226 {REG_A6XX_RBBM_CLOCK_DELAY_SP2, 0x00000080}, 227 {REG_A6XX_RBBM_CLOCK_DELAY_SP3, 0x00000080}, 228 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf}, 229 {REG_A6XX_RBBM_CLOCK_HYST_SP1, 0x0000f3cf}, 230 {REG_A6XX_RBBM_CLOCK_HYST_SP2, 0x0000f3cf}, 231 {REG_A6XX_RBBM_CLOCK_HYST_SP3, 0x0000f3cf}, 232 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222}, 233 {REG_A6XX_RBBM_CLOCK_CNTL_TP1, 0x02222222}, 234 {REG_A6XX_RBBM_CLOCK_CNTL_TP2, 0x02222222}, 235 {REG_A6XX_RBBM_CLOCK_CNTL_TP3, 0x02222222}, 236 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, 237 {REG_A6XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222}, 238 {REG_A6XX_RBBM_CLOCK_CNTL2_TP2, 0x22222222}, 239 {REG_A6XX_RBBM_CLOCK_CNTL2_TP3, 0x22222222}, 240 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, 241 {REG_A6XX_RBBM_CLOCK_CNTL3_TP1, 0x22222222}, 242 {REG_A6XX_RBBM_CLOCK_CNTL3_TP2, 0x22222222}, 243 {REG_A6XX_RBBM_CLOCK_CNTL3_TP3, 0x22222222}, 244 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, 245 {REG_A6XX_RBBM_CLOCK_CNTL4_TP1, 0x00022222}, 246 {REG_A6XX_RBBM_CLOCK_CNTL4_TP2, 0x00022222}, 247 {REG_A6XX_RBBM_CLOCK_CNTL4_TP3, 0x00022222}, 248 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, 249 {REG_A6XX_RBBM_CLOCK_HYST_TP1, 0x77777777}, 250 {REG_A6XX_RBBM_CLOCK_HYST_TP2, 0x77777777}, 251 {REG_A6XX_RBBM_CLOCK_HYST_TP3, 0x77777777}, 252 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, 253 {REG_A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777}, 254 {REG_A6XX_RBBM_CLOCK_HYST2_TP2, 0x77777777}, 255 {REG_A6XX_RBBM_CLOCK_HYST2_TP3, 0x77777777}, 256 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, 257 {REG_A6XX_RBBM_CLOCK_HYST3_TP1, 0x77777777}, 258 {REG_A6XX_RBBM_CLOCK_HYST3_TP2, 0x77777777}, 259 {REG_A6XX_RBBM_CLOCK_HYST3_TP3, 0x77777777}, 260 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, 261 {REG_A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777}, 262 {REG_A6XX_RBBM_CLOCK_HYST4_TP2, 0x00077777}, 263 {REG_A6XX_RBBM_CLOCK_HYST4_TP3, 0x00077777}, 264 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, 265 {REG_A6XX_RBBM_CLOCK_DELAY_TP1, 0x11111111}, 266 {REG_A6XX_RBBM_CLOCK_DELAY_TP2, 0x11111111}, 267 {REG_A6XX_RBBM_CLOCK_DELAY_TP3, 0x11111111}, 268 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, 269 {REG_A6XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111}, 270 {REG_A6XX_RBBM_CLOCK_DELAY2_TP2, 0x11111111}, 271 {REG_A6XX_RBBM_CLOCK_DELAY2_TP3, 0x11111111}, 272 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, 273 {REG_A6XX_RBBM_CLOCK_DELAY3_TP1, 0x11111111}, 274 {REG_A6XX_RBBM_CLOCK_DELAY3_TP2, 0x11111111}, 275 {REG_A6XX_RBBM_CLOCK_DELAY3_TP3, 0x11111111}, 276 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, 277 {REG_A6XX_RBBM_CLOCK_DELAY4_TP1, 0x00011111}, 278 {REG_A6XX_RBBM_CLOCK_DELAY4_TP2, 0x00011111}, 279 {REG_A6XX_RBBM_CLOCK_DELAY4_TP3, 0x00011111}, 280 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, 281 {REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222}, 282 {REG_A6XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222}, 283 {REG_A6XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222}, 284 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, 285 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, 286 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, 287 {REG_A6XX_RBBM_CLOCK_CNTL_RB1, 0x22222222}, 288 {REG_A6XX_RBBM_CLOCK_CNTL_RB2, 0x22222222}, 289 {REG_A6XX_RBBM_CLOCK_CNTL_RB3, 0x22222222}, 290 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x00002222}, 291 {REG_A6XX_RBBM_CLOCK_CNTL2_RB1, 0x00002222}, 292 {REG_A6XX_RBBM_CLOCK_CNTL2_RB2, 0x00002222}, 293 {REG_A6XX_RBBM_CLOCK_CNTL2_RB3, 0x00002222}, 294 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, 295 {REG_A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220}, 296 {REG_A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220}, 297 {REG_A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220}, 298 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00}, 299 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040f00}, 300 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040f00}, 301 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040f00}, 302 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05022022}, 303 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, 304 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, 305 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, 306 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, 307 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222}, 308 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, 309 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, 310 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, 311 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, 312 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, 313 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, 314 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, 315 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, 316 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, 317 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, 318 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, 319 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, 320 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, 321 {}, 322 }; 323 324 const struct adreno_reglist a640_hwcg[] = { 325 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222}, 326 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, 327 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, 328 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF}, 329 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222}, 330 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, 331 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, 332 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, 333 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, 334 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, 335 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, 336 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, 337 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, 338 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, 339 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, 340 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, 341 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, 342 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222}, 343 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, 344 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00}, 345 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05222022}, 346 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, 347 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, 348 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, 349 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, 350 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, 351 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222}, 352 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, 353 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, 354 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, 355 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, 356 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, 357 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, 358 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, 359 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, 360 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, 361 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000}, 362 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222}, 363 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111}, 364 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000}, 365 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, 366 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, 367 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, 368 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182}, 369 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000}, 370 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000}, 371 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, 372 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, 373 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, 374 {}, 375 }; 376 377 const struct adreno_reglist a650_hwcg[] = { 378 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222}, 379 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, 380 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, 381 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF}, 382 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222}, 383 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, 384 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, 385 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, 386 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, 387 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, 388 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, 389 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, 390 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, 391 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, 392 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, 393 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, 394 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, 395 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222}, 396 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, 397 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00}, 398 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022}, 399 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, 400 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, 401 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, 402 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, 403 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, 404 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222}, 405 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, 406 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, 407 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, 408 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, 409 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, 410 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, 411 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, 412 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, 413 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, 414 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000}, 415 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222}, 416 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111}, 417 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000777}, 418 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, 419 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, 420 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, 421 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182}, 422 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000}, 423 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000}, 424 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, 425 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, 426 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, 427 {}, 428 }; 429 430 static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) 431 { 432 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 433 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 434 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 435 const struct adreno_reglist *reg; 436 unsigned int i; 437 u32 val, clock_cntl_on; 438 439 if (!adreno_gpu->info->hwcg) 440 return; 441 442 if (adreno_is_a630(adreno_gpu)) 443 clock_cntl_on = 0x8aa8aa02; 444 else 445 clock_cntl_on = 0x8aa8aa82; 446 447 val = gpu_read(gpu, REG_A6XX_RBBM_CLOCK_CNTL); 448 449 /* Don't re-program the registers if they are already correct */ 450 if ((!state && !val) || (state && (val == clock_cntl_on))) 451 return; 452 453 /* Disable SP clock before programming HWCG registers */ 454 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0); 455 456 for (i = 0; (reg = &adreno_gpu->info->hwcg[i], reg->offset); i++) 457 gpu_write(gpu, reg->offset, state ? reg->value : 0); 458 459 /* Enable SP clock */ 460 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1); 461 462 gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? clock_cntl_on : 0); 463 } 464 465 static void a6xx_set_ubwc_config(struct msm_gpu *gpu) 466 { 467 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 468 u32 lower_bit = 2; 469 u32 amsbc = 0; 470 u32 rgb565_predicator = 0; 471 u32 uavflagprd_inv = 0; 472 473 /* a618 is using the hw default values */ 474 if (adreno_is_a618(adreno_gpu)) 475 return; 476 477 if (adreno_is_a640(adreno_gpu)) 478 amsbc = 1; 479 480 if (adreno_is_a650(adreno_gpu)) { 481 /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */ 482 lower_bit = 3; 483 amsbc = 1; 484 rgb565_predicator = 1; 485 uavflagprd_inv = 2; 486 } 487 488 gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, 489 rgb565_predicator << 11 | amsbc << 4 | lower_bit << 1); 490 gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, lower_bit << 1); 491 gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, 492 uavflagprd_inv >> 4 | lower_bit << 1); 493 gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, lower_bit << 21); 494 } 495 496 static int a6xx_cp_init(struct msm_gpu *gpu) 497 { 498 struct msm_ringbuffer *ring = gpu->rb[0]; 499 500 OUT_PKT7(ring, CP_ME_INIT, 8); 501 502 OUT_RING(ring, 0x0000002f); 503 504 /* Enable multiple hardware contexts */ 505 OUT_RING(ring, 0x00000003); 506 507 /* Enable error detection */ 508 OUT_RING(ring, 0x20000000); 509 510 /* Don't enable header dump */ 511 OUT_RING(ring, 0x00000000); 512 OUT_RING(ring, 0x00000000); 513 514 /* No workarounds enabled */ 515 OUT_RING(ring, 0x00000000); 516 517 /* Pad rest of the cmds with 0's */ 518 OUT_RING(ring, 0x00000000); 519 OUT_RING(ring, 0x00000000); 520 521 a6xx_flush(gpu, ring); 522 return a6xx_idle(gpu, ring) ? 0 : -EINVAL; 523 } 524 525 static void a6xx_ucode_check_version(struct a6xx_gpu *a6xx_gpu, 526 struct drm_gem_object *obj) 527 { 528 u32 *buf = msm_gem_get_vaddr(obj); 529 530 if (IS_ERR(buf)) 531 return; 532 533 /* 534 * If the lowest nibble is 0xa that is an indication that this microcode 535 * has been patched. The actual version is in dword [3] but we only care 536 * about the patchlevel which is the lowest nibble of dword [3] 537 * 538 * Otherwise check that the firmware is greater than or equal to 1.90 539 * which was the first version that had this fix built in 540 */ 541 if (((buf[0] & 0xf) == 0xa) && (buf[2] & 0xf) >= 1) 542 a6xx_gpu->has_whereami = true; 543 else if ((buf[0] & 0xfff) > 0x190) 544 a6xx_gpu->has_whereami = true; 545 546 msm_gem_put_vaddr(obj); 547 } 548 549 static int a6xx_ucode_init(struct msm_gpu *gpu) 550 { 551 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 552 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 553 554 if (!a6xx_gpu->sqe_bo) { 555 a6xx_gpu->sqe_bo = adreno_fw_create_bo(gpu, 556 adreno_gpu->fw[ADRENO_FW_SQE], &a6xx_gpu->sqe_iova); 557 558 if (IS_ERR(a6xx_gpu->sqe_bo)) { 559 int ret = PTR_ERR(a6xx_gpu->sqe_bo); 560 561 a6xx_gpu->sqe_bo = NULL; 562 DRM_DEV_ERROR(&gpu->pdev->dev, 563 "Could not allocate SQE ucode: %d\n", ret); 564 565 return ret; 566 } 567 568 msm_gem_object_set_name(a6xx_gpu->sqe_bo, "sqefw"); 569 a6xx_ucode_check_version(a6xx_gpu, a6xx_gpu->sqe_bo); 570 } 571 572 gpu_write64(gpu, REG_A6XX_CP_SQE_INSTR_BASE_LO, 573 REG_A6XX_CP_SQE_INSTR_BASE_HI, a6xx_gpu->sqe_iova); 574 575 return 0; 576 } 577 578 static int a6xx_zap_shader_init(struct msm_gpu *gpu) 579 { 580 static bool loaded; 581 int ret; 582 583 if (loaded) 584 return 0; 585 586 ret = adreno_zap_shader_load(gpu, GPU_PAS_ID); 587 588 loaded = !ret; 589 return ret; 590 } 591 592 #define A6XX_INT_MASK (A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR | \ 593 A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW | \ 594 A6XX_RBBM_INT_0_MASK_CP_HW_ERROR | \ 595 A6XX_RBBM_INT_0_MASK_CP_IB2 | \ 596 A6XX_RBBM_INT_0_MASK_CP_IB1 | \ 597 A6XX_RBBM_INT_0_MASK_CP_RB | \ 598 A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS | \ 599 A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW | \ 600 A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \ 601 A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \ 602 A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR) 603 604 static int a6xx_hw_init(struct msm_gpu *gpu) 605 { 606 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 607 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 608 int ret; 609 610 /* Make sure the GMU keeps the GPU on while we set it up */ 611 a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); 612 613 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0); 614 615 /* 616 * Disable the trusted memory range - we don't actually supported secure 617 * memory rendering at this point in time and we don't want to block off 618 * part of the virtual memory space. 619 */ 620 gpu_write64(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO, 621 REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI, 0x00000000); 622 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000); 623 624 /* Turn on 64 bit addressing for all blocks */ 625 gpu_write(gpu, REG_A6XX_CP_ADDR_MODE_CNTL, 0x1); 626 gpu_write(gpu, REG_A6XX_VSC_ADDR_MODE_CNTL, 0x1); 627 gpu_write(gpu, REG_A6XX_GRAS_ADDR_MODE_CNTL, 0x1); 628 gpu_write(gpu, REG_A6XX_RB_ADDR_MODE_CNTL, 0x1); 629 gpu_write(gpu, REG_A6XX_PC_ADDR_MODE_CNTL, 0x1); 630 gpu_write(gpu, REG_A6XX_HLSQ_ADDR_MODE_CNTL, 0x1); 631 gpu_write(gpu, REG_A6XX_VFD_ADDR_MODE_CNTL, 0x1); 632 gpu_write(gpu, REG_A6XX_VPC_ADDR_MODE_CNTL, 0x1); 633 gpu_write(gpu, REG_A6XX_UCHE_ADDR_MODE_CNTL, 0x1); 634 gpu_write(gpu, REG_A6XX_SP_ADDR_MODE_CNTL, 0x1); 635 gpu_write(gpu, REG_A6XX_TPL1_ADDR_MODE_CNTL, 0x1); 636 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1); 637 638 /* enable hardware clockgating */ 639 a6xx_set_hwcg(gpu, true); 640 641 /* VBIF/GBIF start*/ 642 if (adreno_is_a640(adreno_gpu) || adreno_is_a650(adreno_gpu)) { 643 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620); 644 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620); 645 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620); 646 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620); 647 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620); 648 gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x3); 649 } else { 650 gpu_write(gpu, REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3); 651 } 652 653 if (adreno_is_a630(adreno_gpu)) 654 gpu_write(gpu, REG_A6XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009); 655 656 /* Make all blocks contribute to the GPU BUSY perf counter */ 657 gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xffffffff); 658 659 /* Disable L2 bypass in the UCHE */ 660 gpu_write(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX_LO, 0xffffffc0); 661 gpu_write(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX_HI, 0x0001ffff); 662 gpu_write(gpu, REG_A6XX_UCHE_TRAP_BASE_LO, 0xfffff000); 663 gpu_write(gpu, REG_A6XX_UCHE_TRAP_BASE_HI, 0x0001ffff); 664 gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_LO, 0xfffff000); 665 gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_HI, 0x0001ffff); 666 667 if (!adreno_is_a650(adreno_gpu)) { 668 /* Set the GMEM VA range [0x100000:0x100000 + gpu->gmem - 1] */ 669 gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MIN_LO, 670 REG_A6XX_UCHE_GMEM_RANGE_MIN_HI, 0x00100000); 671 672 gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MAX_LO, 673 REG_A6XX_UCHE_GMEM_RANGE_MAX_HI, 674 0x00100000 + adreno_gpu->gmem - 1); 675 } 676 677 gpu_write(gpu, REG_A6XX_UCHE_FILTER_CNTL, 0x804); 678 gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, 0x4); 679 680 if (adreno_is_a640(adreno_gpu) || adreno_is_a650(adreno_gpu)) 681 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140); 682 else 683 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x010000c0); 684 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c); 685 686 /* Setting the mem pool size */ 687 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128); 688 689 /* Setting the primFifo thresholds default values */ 690 if (adreno_is_a650(adreno_gpu)) 691 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300000); 692 else if (adreno_is_a640(adreno_gpu)) 693 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200000); 694 else 695 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, (0x300 << 11)); 696 697 /* Set the AHB default slave response to "ERROR" */ 698 gpu_write(gpu, REG_A6XX_CP_AHB_CNTL, 0x1); 699 700 /* Turn on performance counters */ 701 gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_CNTL, 0x1); 702 703 /* Select CP0 to always count cycles */ 704 gpu_write(gpu, REG_A6XX_CP_PERFCTR_CP_SEL_0, PERF_CP_ALWAYS_COUNT); 705 706 a6xx_set_ubwc_config(gpu); 707 708 /* Enable fault detection */ 709 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, 710 (1 << 30) | 0x1fffff); 711 712 gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, 1); 713 714 /* Set weights for bicubic filtering */ 715 if (adreno_is_a650(adreno_gpu)) { 716 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0, 0); 717 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1, 718 0x3fe05ff4); 719 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2, 720 0x3fa0ebee); 721 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3, 722 0x3f5193ed); 723 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4, 724 0x3f0243f0); 725 } 726 727 /* Protect registers from the CP */ 728 gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL, 0x00000003); 729 730 gpu_write(gpu, REG_A6XX_CP_PROTECT(0), 731 A6XX_PROTECT_RDONLY(0x600, 0x51)); 732 gpu_write(gpu, REG_A6XX_CP_PROTECT(1), A6XX_PROTECT_RW(0xae50, 0x2)); 733 gpu_write(gpu, REG_A6XX_CP_PROTECT(2), A6XX_PROTECT_RW(0x9624, 0x13)); 734 gpu_write(gpu, REG_A6XX_CP_PROTECT(3), A6XX_PROTECT_RW(0x8630, 0x8)); 735 gpu_write(gpu, REG_A6XX_CP_PROTECT(4), A6XX_PROTECT_RW(0x9e70, 0x1)); 736 gpu_write(gpu, REG_A6XX_CP_PROTECT(5), A6XX_PROTECT_RW(0x9e78, 0x187)); 737 gpu_write(gpu, REG_A6XX_CP_PROTECT(6), A6XX_PROTECT_RW(0xf000, 0x810)); 738 gpu_write(gpu, REG_A6XX_CP_PROTECT(7), 739 A6XX_PROTECT_RDONLY(0xfc00, 0x3)); 740 gpu_write(gpu, REG_A6XX_CP_PROTECT(8), A6XX_PROTECT_RW(0x50e, 0x0)); 741 gpu_write(gpu, REG_A6XX_CP_PROTECT(9), A6XX_PROTECT_RDONLY(0x50f, 0x0)); 742 gpu_write(gpu, REG_A6XX_CP_PROTECT(10), A6XX_PROTECT_RW(0x510, 0x0)); 743 gpu_write(gpu, REG_A6XX_CP_PROTECT(11), 744 A6XX_PROTECT_RDONLY(0x0, 0x4f9)); 745 gpu_write(gpu, REG_A6XX_CP_PROTECT(12), 746 A6XX_PROTECT_RDONLY(0x501, 0xa)); 747 gpu_write(gpu, REG_A6XX_CP_PROTECT(13), 748 A6XX_PROTECT_RDONLY(0x511, 0x44)); 749 gpu_write(gpu, REG_A6XX_CP_PROTECT(14), A6XX_PROTECT_RW(0xe00, 0xe)); 750 gpu_write(gpu, REG_A6XX_CP_PROTECT(15), A6XX_PROTECT_RW(0x8e00, 0x0)); 751 gpu_write(gpu, REG_A6XX_CP_PROTECT(16), A6XX_PROTECT_RW(0x8e50, 0xf)); 752 gpu_write(gpu, REG_A6XX_CP_PROTECT(17), A6XX_PROTECT_RW(0xbe02, 0x0)); 753 gpu_write(gpu, REG_A6XX_CP_PROTECT(18), 754 A6XX_PROTECT_RW(0xbe20, 0x11f3)); 755 gpu_write(gpu, REG_A6XX_CP_PROTECT(19), A6XX_PROTECT_RW(0x800, 0x82)); 756 gpu_write(gpu, REG_A6XX_CP_PROTECT(20), A6XX_PROTECT_RW(0x8a0, 0x8)); 757 gpu_write(gpu, REG_A6XX_CP_PROTECT(21), A6XX_PROTECT_RW(0x8ab, 0x19)); 758 gpu_write(gpu, REG_A6XX_CP_PROTECT(22), A6XX_PROTECT_RW(0x900, 0x4d)); 759 gpu_write(gpu, REG_A6XX_CP_PROTECT(23), A6XX_PROTECT_RW(0x98d, 0x76)); 760 gpu_write(gpu, REG_A6XX_CP_PROTECT(24), 761 A6XX_PROTECT_RDONLY(0x980, 0x4)); 762 gpu_write(gpu, REG_A6XX_CP_PROTECT(25), A6XX_PROTECT_RW(0xa630, 0x0)); 763 764 /* Enable expanded apriv for targets that support it */ 765 if (gpu->hw_apriv) { 766 gpu_write(gpu, REG_A6XX_CP_APRIV_CNTL, 767 (1 << 6) | (1 << 5) | (1 << 3) | (1 << 2) | (1 << 1)); 768 } 769 770 /* Enable interrupts */ 771 gpu_write(gpu, REG_A6XX_RBBM_INT_0_MASK, A6XX_INT_MASK); 772 773 ret = adreno_hw_init(gpu); 774 if (ret) 775 goto out; 776 777 ret = a6xx_ucode_init(gpu); 778 if (ret) 779 goto out; 780 781 /* Set the ringbuffer address */ 782 gpu_write64(gpu, REG_A6XX_CP_RB_BASE, REG_A6XX_CP_RB_BASE_HI, 783 gpu->rb[0]->iova); 784 785 /* Targets that support extended APRIV can use the RPTR shadow from 786 * hardware but all the other ones need to disable the feature. Targets 787 * that support the WHERE_AM_I opcode can use that instead 788 */ 789 if (adreno_gpu->base.hw_apriv) 790 gpu_write(gpu, REG_A6XX_CP_RB_CNTL, MSM_GPU_RB_CNTL_DEFAULT); 791 else 792 gpu_write(gpu, REG_A6XX_CP_RB_CNTL, 793 MSM_GPU_RB_CNTL_DEFAULT | AXXX_CP_RB_CNTL_NO_UPDATE); 794 795 /* 796 * Expanded APRIV and targets that support WHERE_AM_I both need a 797 * privileged buffer to store the RPTR shadow 798 */ 799 800 if (adreno_gpu->base.hw_apriv || a6xx_gpu->has_whereami) { 801 if (!a6xx_gpu->shadow_bo) { 802 a6xx_gpu->shadow = msm_gem_kernel_new_locked(gpu->dev, 803 sizeof(u32) * gpu->nr_rings, 804 MSM_BO_UNCACHED | MSM_BO_MAP_PRIV, 805 gpu->aspace, &a6xx_gpu->shadow_bo, 806 &a6xx_gpu->shadow_iova); 807 808 if (IS_ERR(a6xx_gpu->shadow)) 809 return PTR_ERR(a6xx_gpu->shadow); 810 } 811 812 gpu_write64(gpu, REG_A6XX_CP_RB_RPTR_ADDR_LO, 813 REG_A6XX_CP_RB_RPTR_ADDR_HI, 814 shadowptr(a6xx_gpu, gpu->rb[0])); 815 } 816 817 /* Always come up on rb 0 */ 818 a6xx_gpu->cur_ring = gpu->rb[0]; 819 820 a6xx_gpu->cur_ctx = NULL; 821 822 /* Enable the SQE_to start the CP engine */ 823 gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 1); 824 825 ret = a6xx_cp_init(gpu); 826 if (ret) 827 goto out; 828 829 /* 830 * Try to load a zap shader into the secure world. If successful 831 * we can use the CP to switch out of secure mode. If not then we 832 * have no resource but to try to switch ourselves out manually. If we 833 * guessed wrong then access to the RBBM_SECVID_TRUST_CNTL register will 834 * be blocked and a permissions violation will soon follow. 835 */ 836 ret = a6xx_zap_shader_init(gpu); 837 if (!ret) { 838 OUT_PKT7(gpu->rb[0], CP_SET_SECURE_MODE, 1); 839 OUT_RING(gpu->rb[0], 0x00000000); 840 841 a6xx_flush(gpu, gpu->rb[0]); 842 if (!a6xx_idle(gpu, gpu->rb[0])) 843 return -EINVAL; 844 } else if (ret == -ENODEV) { 845 /* 846 * This device does not use zap shader (but print a warning 847 * just in case someone got their dt wrong.. hopefully they 848 * have a debug UART to realize the error of their ways... 849 * if you mess this up you are about to crash horribly) 850 */ 851 dev_warn_once(gpu->dev->dev, 852 "Zap shader not enabled - using SECVID_TRUST_CNTL instead\n"); 853 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TRUST_CNTL, 0x0); 854 ret = 0; 855 } else { 856 return ret; 857 } 858 859 out: 860 /* 861 * Tell the GMU that we are done touching the GPU and it can start power 862 * management 863 */ 864 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); 865 866 if (a6xx_gpu->gmu.legacy) { 867 /* Take the GMU out of its special boot mode */ 868 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_BOOT_SLUMBER); 869 } 870 871 return ret; 872 } 873 874 static void a6xx_dump(struct msm_gpu *gpu) 875 { 876 DRM_DEV_INFO(&gpu->pdev->dev, "status: %08x\n", 877 gpu_read(gpu, REG_A6XX_RBBM_STATUS)); 878 adreno_dump(gpu); 879 } 880 881 #define VBIF_RESET_ACK_TIMEOUT 100 882 #define VBIF_RESET_ACK_MASK 0x00f0 883 884 static void a6xx_recover(struct msm_gpu *gpu) 885 { 886 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 887 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 888 int i; 889 890 adreno_dump_info(gpu); 891 892 for (i = 0; i < 8; i++) 893 DRM_DEV_INFO(&gpu->pdev->dev, "CP_SCRATCH_REG%d: %u\n", i, 894 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(i))); 895 896 if (hang_debug) 897 a6xx_dump(gpu); 898 899 /* 900 * Turn off keep alive that might have been enabled by the hang 901 * interrupt 902 */ 903 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 0); 904 905 gpu->funcs->pm_suspend(gpu); 906 gpu->funcs->pm_resume(gpu); 907 908 msm_gpu_hw_init(gpu); 909 } 910 911 static int a6xx_fault_handler(void *arg, unsigned long iova, int flags) 912 { 913 struct msm_gpu *gpu = arg; 914 915 pr_warn_ratelimited("*** gpu fault: iova=%08lx, flags=%d (%u,%u,%u,%u)\n", 916 iova, flags, 917 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)), 918 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(5)), 919 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(6)), 920 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(7))); 921 922 return -EFAULT; 923 } 924 925 static void a6xx_cp_hw_err_irq(struct msm_gpu *gpu) 926 { 927 u32 status = gpu_read(gpu, REG_A6XX_CP_INTERRUPT_STATUS); 928 929 if (status & A6XX_CP_INT_CP_OPCODE_ERROR) { 930 u32 val; 931 932 gpu_write(gpu, REG_A6XX_CP_SQE_STAT_ADDR, 1); 933 val = gpu_read(gpu, REG_A6XX_CP_SQE_STAT_DATA); 934 dev_err_ratelimited(&gpu->pdev->dev, 935 "CP | opcode error | possible opcode=0x%8.8X\n", 936 val); 937 } 938 939 if (status & A6XX_CP_INT_CP_UCODE_ERROR) 940 dev_err_ratelimited(&gpu->pdev->dev, 941 "CP ucode error interrupt\n"); 942 943 if (status & A6XX_CP_INT_CP_HW_FAULT_ERROR) 944 dev_err_ratelimited(&gpu->pdev->dev, "CP | HW fault | status=0x%8.8X\n", 945 gpu_read(gpu, REG_A6XX_CP_HW_FAULT)); 946 947 if (status & A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR) { 948 u32 val = gpu_read(gpu, REG_A6XX_CP_PROTECT_STATUS); 949 950 dev_err_ratelimited(&gpu->pdev->dev, 951 "CP | protected mode error | %s | addr=0x%8.8X | status=0x%8.8X\n", 952 val & (1 << 20) ? "READ" : "WRITE", 953 (val & 0x3ffff), val); 954 } 955 956 if (status & A6XX_CP_INT_CP_AHB_ERROR) 957 dev_err_ratelimited(&gpu->pdev->dev, "CP AHB error interrupt\n"); 958 959 if (status & A6XX_CP_INT_CP_VSD_PARITY_ERROR) 960 dev_err_ratelimited(&gpu->pdev->dev, "CP VSD decoder parity error\n"); 961 962 if (status & A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR) 963 dev_err_ratelimited(&gpu->pdev->dev, "CP illegal instruction error\n"); 964 965 } 966 967 static void a6xx_fault_detect_irq(struct msm_gpu *gpu) 968 { 969 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 970 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 971 struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu); 972 973 /* 974 * Force the GPU to stay on until after we finish 975 * collecting information 976 */ 977 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 1); 978 979 DRM_DEV_ERROR(&gpu->pdev->dev, 980 "gpu fault ring %d fence %x status %8.8X rb %4.4x/%4.4x ib1 %16.16llX/%4.4x ib2 %16.16llX/%4.4x\n", 981 ring ? ring->id : -1, ring ? ring->seqno : 0, 982 gpu_read(gpu, REG_A6XX_RBBM_STATUS), 983 gpu_read(gpu, REG_A6XX_CP_RB_RPTR), 984 gpu_read(gpu, REG_A6XX_CP_RB_WPTR), 985 gpu_read64(gpu, REG_A6XX_CP_IB1_BASE, REG_A6XX_CP_IB1_BASE_HI), 986 gpu_read(gpu, REG_A6XX_CP_IB1_REM_SIZE), 987 gpu_read64(gpu, REG_A6XX_CP_IB2_BASE, REG_A6XX_CP_IB2_BASE_HI), 988 gpu_read(gpu, REG_A6XX_CP_IB2_REM_SIZE)); 989 990 /* Turn off the hangcheck timer to keep it from bothering us */ 991 del_timer(&gpu->hangcheck_timer); 992 993 kthread_queue_work(gpu->worker, &gpu->recover_work); 994 } 995 996 static irqreturn_t a6xx_irq(struct msm_gpu *gpu) 997 { 998 u32 status = gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS); 999 1000 gpu_write(gpu, REG_A6XX_RBBM_INT_CLEAR_CMD, status); 1001 1002 if (status & A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT) 1003 a6xx_fault_detect_irq(gpu); 1004 1005 if (status & A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR) 1006 dev_err_ratelimited(&gpu->pdev->dev, "CP | AHB bus error\n"); 1007 1008 if (status & A6XX_RBBM_INT_0_MASK_CP_HW_ERROR) 1009 a6xx_cp_hw_err_irq(gpu); 1010 1011 if (status & A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW) 1012 dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB ASYNC overflow\n"); 1013 1014 if (status & A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW) 1015 dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB bus overflow\n"); 1016 1017 if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS) 1018 dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Out of bounds access\n"); 1019 1020 if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS) 1021 msm_gpu_retire(gpu); 1022 1023 return IRQ_HANDLED; 1024 } 1025 1026 static void a6xx_llc_rmw(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 mask, u32 or) 1027 { 1028 return msm_rmw(a6xx_gpu->llc_mmio + (reg << 2), mask, or); 1029 } 1030 1031 static void a6xx_llc_write(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 value) 1032 { 1033 return msm_writel(value, a6xx_gpu->llc_mmio + (reg << 2)); 1034 } 1035 1036 static void a6xx_llc_deactivate(struct a6xx_gpu *a6xx_gpu) 1037 { 1038 llcc_slice_deactivate(a6xx_gpu->llc_slice); 1039 llcc_slice_deactivate(a6xx_gpu->htw_llc_slice); 1040 } 1041 1042 static void a6xx_llc_activate(struct a6xx_gpu *a6xx_gpu) 1043 { 1044 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1045 struct msm_gpu *gpu = &adreno_gpu->base; 1046 u32 cntl1_regval = 0; 1047 1048 if (IS_ERR(a6xx_gpu->llc_mmio)) 1049 return; 1050 1051 if (!llcc_slice_activate(a6xx_gpu->llc_slice)) { 1052 u32 gpu_scid = llcc_get_slice_id(a6xx_gpu->llc_slice); 1053 1054 gpu_scid &= 0x1f; 1055 cntl1_regval = (gpu_scid << 0) | (gpu_scid << 5) | (gpu_scid << 10) | 1056 (gpu_scid << 15) | (gpu_scid << 20); 1057 } 1058 1059 /* 1060 * For targets with a MMU500, activate the slice but don't program the 1061 * register. The XBL will take care of that. 1062 */ 1063 if (!llcc_slice_activate(a6xx_gpu->htw_llc_slice)) { 1064 if (!a6xx_gpu->have_mmu500) { 1065 u32 gpuhtw_scid = llcc_get_slice_id(a6xx_gpu->htw_llc_slice); 1066 1067 gpuhtw_scid &= 0x1f; 1068 cntl1_regval |= FIELD_PREP(GENMASK(29, 25), gpuhtw_scid); 1069 } 1070 } 1071 1072 if (cntl1_regval) { 1073 /* 1074 * Program the slice IDs for the various GPU blocks and GPU MMU 1075 * pagetables 1076 */ 1077 if (a6xx_gpu->have_mmu500) 1078 gpu_rmw(gpu, REG_A6XX_GBIF_SCACHE_CNTL1, GENMASK(24, 0), 1079 cntl1_regval); 1080 else { 1081 a6xx_llc_write(a6xx_gpu, 1082 REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1, cntl1_regval); 1083 1084 /* 1085 * Program cacheability overrides to not allocate cache 1086 * lines on a write miss 1087 */ 1088 a6xx_llc_rmw(a6xx_gpu, 1089 REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0, 0xF, 0x03); 1090 } 1091 } 1092 } 1093 1094 static void a6xx_llc_slices_destroy(struct a6xx_gpu *a6xx_gpu) 1095 { 1096 llcc_slice_putd(a6xx_gpu->llc_slice); 1097 llcc_slice_putd(a6xx_gpu->htw_llc_slice); 1098 } 1099 1100 static void a6xx_llc_slices_init(struct platform_device *pdev, 1101 struct a6xx_gpu *a6xx_gpu) 1102 { 1103 struct device_node *phandle; 1104 1105 a6xx_gpu->llc_mmio = msm_ioremap(pdev, "cx_mem", "gpu_cx"); 1106 if (IS_ERR(a6xx_gpu->llc_mmio)) 1107 return; 1108 1109 /* 1110 * There is a different programming path for targets with an mmu500 1111 * attached, so detect if that is the case 1112 */ 1113 phandle = of_parse_phandle(pdev->dev.of_node, "iommus", 0); 1114 a6xx_gpu->have_mmu500 = (phandle && 1115 of_device_is_compatible(phandle, "arm,mmu-500")); 1116 of_node_put(phandle); 1117 1118 a6xx_gpu->llc_slice = llcc_slice_getd(LLCC_GPU); 1119 a6xx_gpu->htw_llc_slice = llcc_slice_getd(LLCC_GPUHTW); 1120 1121 if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice)) 1122 a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL); 1123 } 1124 1125 static int a6xx_pm_resume(struct msm_gpu *gpu) 1126 { 1127 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1128 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1129 int ret; 1130 1131 gpu->needs_hw_init = true; 1132 1133 trace_msm_gpu_resume(0); 1134 1135 ret = a6xx_gmu_resume(a6xx_gpu); 1136 if (ret) 1137 return ret; 1138 1139 msm_gpu_resume_devfreq(gpu); 1140 1141 a6xx_llc_activate(a6xx_gpu); 1142 1143 return 0; 1144 } 1145 1146 static int a6xx_pm_suspend(struct msm_gpu *gpu) 1147 { 1148 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1149 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1150 int i, ret; 1151 1152 trace_msm_gpu_suspend(0); 1153 1154 a6xx_llc_deactivate(a6xx_gpu); 1155 1156 devfreq_suspend_device(gpu->devfreq.devfreq); 1157 1158 ret = a6xx_gmu_stop(a6xx_gpu); 1159 if (ret) 1160 return ret; 1161 1162 if (adreno_gpu->base.hw_apriv || a6xx_gpu->has_whereami) 1163 for (i = 0; i < gpu->nr_rings; i++) 1164 a6xx_gpu->shadow[i] = 0; 1165 1166 return 0; 1167 } 1168 1169 static int a6xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value) 1170 { 1171 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1172 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1173 static DEFINE_MUTEX(perfcounter_oob); 1174 1175 mutex_lock(&perfcounter_oob); 1176 1177 /* Force the GPU power on so we can read this register */ 1178 a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET); 1179 1180 *value = gpu_read64(gpu, REG_A6XX_RBBM_PERFCTR_CP_0_LO, 1181 REG_A6XX_RBBM_PERFCTR_CP_0_HI); 1182 1183 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET); 1184 mutex_unlock(&perfcounter_oob); 1185 return 0; 1186 } 1187 1188 static struct msm_ringbuffer *a6xx_active_ring(struct msm_gpu *gpu) 1189 { 1190 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1191 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1192 1193 return a6xx_gpu->cur_ring; 1194 } 1195 1196 static void a6xx_destroy(struct msm_gpu *gpu) 1197 { 1198 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1199 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1200 1201 if (a6xx_gpu->sqe_bo) { 1202 msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->aspace); 1203 drm_gem_object_put(a6xx_gpu->sqe_bo); 1204 } 1205 1206 if (a6xx_gpu->shadow_bo) { 1207 msm_gem_unpin_iova(a6xx_gpu->shadow_bo, gpu->aspace); 1208 drm_gem_object_put(a6xx_gpu->shadow_bo); 1209 } 1210 1211 a6xx_llc_slices_destroy(a6xx_gpu); 1212 1213 a6xx_gmu_remove(a6xx_gpu); 1214 1215 adreno_gpu_cleanup(adreno_gpu); 1216 1217 if (a6xx_gpu->opp_table) 1218 dev_pm_opp_put_supported_hw(a6xx_gpu->opp_table); 1219 1220 kfree(a6xx_gpu); 1221 } 1222 1223 static unsigned long a6xx_gpu_busy(struct msm_gpu *gpu) 1224 { 1225 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1226 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1227 u64 busy_cycles, busy_time; 1228 1229 1230 /* Only read the gpu busy if the hardware is already active */ 1231 if (pm_runtime_get_if_in_use(a6xx_gpu->gmu.dev) == 0) 1232 return 0; 1233 1234 busy_cycles = gmu_read64(&a6xx_gpu->gmu, 1235 REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L, 1236 REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H); 1237 1238 busy_time = (busy_cycles - gpu->devfreq.busy_cycles) * 10; 1239 do_div(busy_time, 192); 1240 1241 gpu->devfreq.busy_cycles = busy_cycles; 1242 1243 pm_runtime_put(a6xx_gpu->gmu.dev); 1244 1245 if (WARN_ON(busy_time > ~0LU)) 1246 return ~0LU; 1247 1248 return (unsigned long)busy_time; 1249 } 1250 1251 static struct msm_gem_address_space * 1252 a6xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev) 1253 { 1254 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1255 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1256 struct iommu_domain *iommu; 1257 struct msm_mmu *mmu; 1258 struct msm_gem_address_space *aspace; 1259 u64 start, size; 1260 1261 iommu = iommu_domain_alloc(&platform_bus_type); 1262 if (!iommu) 1263 return NULL; 1264 1265 /* 1266 * This allows GPU to set the bus attributes required to use system 1267 * cache on behalf of the iommu page table walker. 1268 */ 1269 if (!IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice)) 1270 adreno_set_llc_attributes(iommu); 1271 1272 mmu = msm_iommu_new(&pdev->dev, iommu); 1273 if (IS_ERR(mmu)) { 1274 iommu_domain_free(iommu); 1275 return ERR_CAST(mmu); 1276 } 1277 1278 /* 1279 * Use the aperture start or SZ_16M, whichever is greater. This will 1280 * ensure that we align with the allocated pagetable range while still 1281 * allowing room in the lower 32 bits for GMEM and whatnot 1282 */ 1283 start = max_t(u64, SZ_16M, iommu->geometry.aperture_start); 1284 size = iommu->geometry.aperture_end - start + 1; 1285 1286 aspace = msm_gem_address_space_create(mmu, "gpu", 1287 start & GENMASK_ULL(48, 0), size); 1288 1289 if (IS_ERR(aspace) && !IS_ERR(mmu)) 1290 mmu->funcs->destroy(mmu); 1291 1292 return aspace; 1293 } 1294 1295 static struct msm_gem_address_space * 1296 a6xx_create_private_address_space(struct msm_gpu *gpu) 1297 { 1298 struct msm_mmu *mmu; 1299 1300 mmu = msm_iommu_pagetable_create(gpu->aspace->mmu); 1301 1302 if (IS_ERR(mmu)) 1303 return ERR_CAST(mmu); 1304 1305 return msm_gem_address_space_create(mmu, 1306 "gpu", 0x100000000ULL, 0x1ffffffffULL); 1307 } 1308 1309 static uint32_t a6xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 1310 { 1311 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1312 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1313 1314 if (adreno_gpu->base.hw_apriv || a6xx_gpu->has_whereami) 1315 return a6xx_gpu->shadow[ring->id]; 1316 1317 return ring->memptrs->rptr = gpu_read(gpu, REG_A6XX_CP_RB_RPTR); 1318 } 1319 1320 static u32 a618_get_speed_bin(u32 fuse) 1321 { 1322 if (fuse == 0) 1323 return 0; 1324 else if (fuse == 169) 1325 return 1; 1326 else if (fuse == 174) 1327 return 2; 1328 1329 return UINT_MAX; 1330 } 1331 1332 static u32 fuse_to_supp_hw(struct device *dev, u32 revn, u32 fuse) 1333 { 1334 u32 val = UINT_MAX; 1335 1336 if (revn == 618) 1337 val = a618_get_speed_bin(fuse); 1338 1339 if (val == UINT_MAX) { 1340 DRM_DEV_ERROR(dev, 1341 "missing support for speed-bin: %u. Some OPPs may not be supported by hardware", 1342 fuse); 1343 return UINT_MAX; 1344 } 1345 1346 return (1 << val); 1347 } 1348 1349 static int a6xx_set_supported_hw(struct device *dev, struct a6xx_gpu *a6xx_gpu, 1350 u32 revn) 1351 { 1352 struct opp_table *opp_table; 1353 struct nvmem_cell *cell; 1354 u32 supp_hw = UINT_MAX; 1355 void *buf; 1356 1357 cell = nvmem_cell_get(dev, "speed_bin"); 1358 /* 1359 * -ENOENT means that the platform doesn't support speedbin which is 1360 * fine 1361 */ 1362 if (PTR_ERR(cell) == -ENOENT) 1363 return 0; 1364 else if (IS_ERR(cell)) { 1365 DRM_DEV_ERROR(dev, 1366 "failed to read speed-bin. Some OPPs may not be supported by hardware"); 1367 goto done; 1368 } 1369 1370 buf = nvmem_cell_read(cell, NULL); 1371 if (IS_ERR(buf)) { 1372 nvmem_cell_put(cell); 1373 DRM_DEV_ERROR(dev, 1374 "failed to read speed-bin. Some OPPs may not be supported by hardware"); 1375 goto done; 1376 } 1377 1378 supp_hw = fuse_to_supp_hw(dev, revn, *((u32 *) buf)); 1379 1380 kfree(buf); 1381 nvmem_cell_put(cell); 1382 1383 done: 1384 opp_table = dev_pm_opp_set_supported_hw(dev, &supp_hw, 1); 1385 if (IS_ERR(opp_table)) 1386 return PTR_ERR(opp_table); 1387 1388 a6xx_gpu->opp_table = opp_table; 1389 return 0; 1390 } 1391 1392 static const struct adreno_gpu_funcs funcs = { 1393 .base = { 1394 .get_param = adreno_get_param, 1395 .hw_init = a6xx_hw_init, 1396 .pm_suspend = a6xx_pm_suspend, 1397 .pm_resume = a6xx_pm_resume, 1398 .recover = a6xx_recover, 1399 .submit = a6xx_submit, 1400 .active_ring = a6xx_active_ring, 1401 .irq = a6xx_irq, 1402 .destroy = a6xx_destroy, 1403 #if defined(CONFIG_DRM_MSM_GPU_STATE) 1404 .show = a6xx_show, 1405 #endif 1406 .gpu_busy = a6xx_gpu_busy, 1407 .gpu_get_freq = a6xx_gmu_get_freq, 1408 .gpu_set_freq = a6xx_gmu_set_freq, 1409 #if defined(CONFIG_DRM_MSM_GPU_STATE) 1410 .gpu_state_get = a6xx_gpu_state_get, 1411 .gpu_state_put = a6xx_gpu_state_put, 1412 #endif 1413 .create_address_space = a6xx_create_address_space, 1414 .create_private_address_space = a6xx_create_private_address_space, 1415 .get_rptr = a6xx_get_rptr, 1416 }, 1417 .get_timestamp = a6xx_get_timestamp, 1418 }; 1419 1420 struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) 1421 { 1422 struct msm_drm_private *priv = dev->dev_private; 1423 struct platform_device *pdev = priv->gpu_pdev; 1424 struct adreno_platform_config *config = pdev->dev.platform_data; 1425 const struct adreno_info *info; 1426 struct device_node *node; 1427 struct a6xx_gpu *a6xx_gpu; 1428 struct adreno_gpu *adreno_gpu; 1429 struct msm_gpu *gpu; 1430 int ret; 1431 1432 a6xx_gpu = kzalloc(sizeof(*a6xx_gpu), GFP_KERNEL); 1433 if (!a6xx_gpu) 1434 return ERR_PTR(-ENOMEM); 1435 1436 adreno_gpu = &a6xx_gpu->base; 1437 gpu = &adreno_gpu->base; 1438 1439 adreno_gpu->registers = NULL; 1440 1441 /* 1442 * We need to know the platform type before calling into adreno_gpu_init 1443 * so that the hw_apriv flag can be correctly set. Snoop into the info 1444 * and grab the revision number 1445 */ 1446 info = adreno_info(config->rev); 1447 1448 if (info && info->revn == 650) 1449 adreno_gpu->base.hw_apriv = true; 1450 1451 a6xx_llc_slices_init(pdev, a6xx_gpu); 1452 1453 ret = a6xx_set_supported_hw(&pdev->dev, a6xx_gpu, info->revn); 1454 if (ret) { 1455 a6xx_destroy(&(a6xx_gpu->base.base)); 1456 return ERR_PTR(ret); 1457 } 1458 1459 ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1); 1460 if (ret) { 1461 a6xx_destroy(&(a6xx_gpu->base.base)); 1462 return ERR_PTR(ret); 1463 } 1464 1465 /* Check if there is a GMU phandle and set it up */ 1466 node = of_parse_phandle(pdev->dev.of_node, "qcom,gmu", 0); 1467 1468 /* FIXME: How do we gracefully handle this? */ 1469 BUG_ON(!node); 1470 1471 ret = a6xx_gmu_init(a6xx_gpu, node); 1472 if (ret) { 1473 a6xx_destroy(&(a6xx_gpu->base.base)); 1474 return ERR_PTR(ret); 1475 } 1476 1477 if (gpu->aspace) 1478 msm_mmu_set_fault_handler(gpu->aspace->mmu, gpu, 1479 a6xx_fault_handler); 1480 1481 return gpu; 1482 } 1483